Lines Matching refs:misc_base
20 #define PLL1_CTR (misc_base + 0x008)
21 #define PLL1_FRQ (misc_base + 0x00C)
22 #define PLL2_CTR (misc_base + 0x014)
23 #define PLL2_FRQ (misc_base + 0x018)
24 #define PLL_CLK_CFG (misc_base + 0x020)
29 #define CORE_CLK_CFG (misc_base + 0x024)
39 #define PERIP_CLK_CFG (misc_base + 0x028)
50 #define PERIP1_CLK_ENB (misc_base + 0x02C)
69 #define RAS_CLK_ENB (misc_base + 0x034)
82 #define PRSC0_CLK_CFG (misc_base + 0x044)
83 #define PRSC1_CLK_CFG (misc_base + 0x048)
84 #define PRSC2_CLK_CFG (misc_base + 0x04C)
85 #define AMEM_CLK_CFG (misc_base + 0x050)
88 #define CLCD_CLK_SYNT (misc_base + 0x05C)
89 #define FIRDA_CLK_SYNT (misc_base + 0x060)
90 #define UART_CLK_SYNT (misc_base + 0x064)
91 #define GMAC_CLK_SYNT (misc_base + 0x068)
92 #define GEN0_CLK_SYNT (misc_base + 0x06C)
93 #define GEN1_CLK_SYNT (misc_base + 0x070)
94 #define GEN2_CLK_SYNT (misc_base + 0x074)
95 #define GEN3_CLK_SYNT (misc_base + 0x078)
388 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) in spear3xx_clk_init() argument