Lines Matching refs:common
37 .common = {
101 .common = {
129 .common = {
314 &pll_cpu_clk.common,
315 &pll_audio_base_clk.common,
316 &pll_video_clk.common,
317 &pll_ve_clk.common,
318 &pll_ddr0_clk.common,
319 &pll_periph_clk.common,
320 &cpu_clk.common,
321 &ahb_clk.common,
322 &apb_clk.common,
323 &bus_dma_clk.common,
324 &bus_mmc0_clk.common,
325 &bus_mmc1_clk.common,
326 &bus_dram_clk.common,
327 &bus_spi0_clk.common,
328 &bus_spi1_clk.common,
329 &bus_otg_clk.common,
330 &bus_ve_clk.common,
331 &bus_lcd_clk.common,
332 &bus_deinterlace_clk.common,
333 &bus_csi_clk.common,
334 &bus_tve_clk.common,
335 &bus_tvd_clk.common,
336 &bus_de_be_clk.common,
337 &bus_de_fe_clk.common,
338 &bus_codec_clk.common,
339 &bus_spdif_clk.common,
340 &bus_ir_clk.common,
341 &bus_rsb_clk.common,
342 &bus_i2s0_clk.common,
343 &bus_i2c0_clk.common,
344 &bus_i2c1_clk.common,
345 &bus_i2c2_clk.common,
346 &bus_pio_clk.common,
347 &bus_uart0_clk.common,
348 &bus_uart1_clk.common,
349 &bus_uart2_clk.common,
350 &mmc0_clk.common,
351 &mmc0_sample_clk.common,
352 &mmc0_output_clk.common,
353 &mmc1_clk.common,
354 &mmc1_sample_clk.common,
355 &mmc1_output_clk.common,
356 &i2s_clk.common,
357 &spdif_clk.common,
358 &usb_phy0_clk.common,
359 &dram_ve_clk.common,
360 &dram_csi_clk.common,
361 &dram_deinterlace_clk.common,
362 &dram_tvd_clk.common,
363 &dram_de_fe_clk.common,
364 &dram_de_be_clk.common,
365 &de_be_clk.common,
366 &de_fe_clk.common,
367 &tcon_clk.common,
368 &deinterlace_clk.common,
369 &tve_clk2_clk.common,
370 &tve_clk1_clk.common,
371 &tvd_clk.common,
372 &csi_clk.common,
373 &ve_clk.common,
374 &codec_clk.common,
375 &avs_clk.common,
379 &pll_audio_base_clk.common.hw
395 &pll_video_clk.common.hw,
400 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
401 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
406 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
408 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
409 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
410 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
411 [CLK_CPU] = &cpu_clk.common.hw,
412 [CLK_AHB] = &ahb_clk.common.hw,
413 [CLK_APB] = &apb_clk.common.hw,
414 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
415 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
416 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
417 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
418 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
419 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
420 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
421 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
422 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
423 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
424 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
425 [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
426 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
427 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
428 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
429 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
430 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
431 [CLK_BUS_IR] = &bus_ir_clk.common.hw,
432 [CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
433 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
434 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
435 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
436 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
437 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
438 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
439 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
440 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
441 [CLK_MMC0] = &mmc0_clk.common.hw,
442 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
443 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
444 [CLK_MMC1] = &mmc1_clk.common.hw,
445 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
446 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
447 [CLK_I2S] = &i2s_clk.common.hw,
448 [CLK_SPDIF] = &spdif_clk.common.hw,
449 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
450 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
451 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
452 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
453 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
454 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
455 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
456 [CLK_DE_BE] = &de_be_clk.common.hw,
457 [CLK_DE_FE] = &de_fe_clk.common.hw,
458 [CLK_TCON] = &tcon_clk.common.hw,
459 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
460 [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
461 [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
462 [CLK_TVD] = &tvd_clk.common.hw,
463 [CLK_CSI] = &csi_clk.common.hw,
464 [CLK_VE] = &ve_clk.common.hw,
465 [CLK_CODEC] = &codec_clk.common.hw,
466 [CLK_AVS] = &avs_clk.common.hw,
513 .common = &pll_cpu_clk.common,
520 .common = &cpu_clk.common,
549 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, in suniv_f1c100s_ccu_probe()