Lines Matching refs:NULL
23 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
28 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
35 NULL,
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
53 NULL,
71 NULL,
75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
94 NULL,
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
120 NULL,
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
134 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
140 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
145 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
152 NULL,
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
168 { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
173 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
174 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
179 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
180 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
181 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
183 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
184 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
195 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
200 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
209 NULL,
216 NULL,
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
231 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
232 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
233 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
234 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
235 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
236 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
237 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
238 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
239 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
240 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
241 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
242 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
243 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
244 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
245 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
250 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
251 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
256 { DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },
257 { DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
263 NULL,
268 NULL,
273 NULL,
278 NULL,
283 NULL,
288 NULL,
292 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
293 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
294 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
295 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
296 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
297 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
303 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
311 NULL,
318 NULL,
322 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
323 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
335 NULL,
340 NULL,
349 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
350 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
357 NULL,
366 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
367 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
374 NULL,
378 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
384 NULL,
388 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
393 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
401 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
402 …{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core…
404 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
405 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
412 NULL,
417 NULL,
421 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
422 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
423 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
428 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
429 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
430 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
443 NULL,
452 NULL,
456 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
457 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
478 NULL,
482 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
487 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
492 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
497 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
502 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
512 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
517 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
522 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
527 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
532 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
537 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
542 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
548 NULL,
557 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
558 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
565 NULL,
574 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
601 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
612 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
618 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
619 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
620 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
621 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
622 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
623 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
624 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
625 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
626 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
627 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
641 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
642 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
643 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
644 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
645 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
646 { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
653 NULL,
658 NULL,
667 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
673 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
674 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
675 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
698 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
699 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
704 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
709 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
725 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
726 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
731 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
732 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
733 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
734 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
735 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
736 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
746 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
753 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
758 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
763 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
768 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
773 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
782 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
787 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
792 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
799 NULL,
803 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
808 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
809 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
812 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
813 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
816 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
852 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
853 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
854 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
855 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
856 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
857 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
858 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
859 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
860 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
861 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
862 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
863 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
864 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
865 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
866 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
867 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
868 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
869 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
870 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
871 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
872 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
873 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
874 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
875 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
876 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
877 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
878 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
879 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
880 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
881 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
882 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
883 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
884 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
885 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
886 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
887 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
888 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
889 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
890 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
891 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
892 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
893 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
894 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
895 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
896 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
897 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
898 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
899 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
900 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
901 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
902 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
903 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
904 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
905 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
906 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
907 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
908 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
909 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
910 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
911 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
912 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
913 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
914 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
915 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
916 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
917 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
918 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
919 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
920 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
921 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
922 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
923 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
924 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
925 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
926 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
927 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
928 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
929 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
930 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
931 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
932 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
933 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
934 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
935 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
936 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
937 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
938 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
939 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
940 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
941 { .node_name = NULL },
955 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); in dra7xx_dt_clk_init()
960 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); in dra7xx_dt_clk_init()
965 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); in dra7xx_dt_clk_init()
970 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); in dra7xx_dt_clk_init()