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Lines Matching refs:bank

31 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \  argument
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
48 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
50 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
54 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ argument
55 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
57 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ argument
58 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
61 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
63 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
65 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
67 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
70 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
71 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
73 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ argument
74 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
77 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ argument
78 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \