570 	void __iomem			 *virtbase;  member
620 	return chan->base->virtbase + D40_DREG_PCBASE +  in chan_base()
1057 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_phy()
1059 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_phy()
1274 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_log()
1276 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_log()
1358 	writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);  in d40_config_write()
1363 	writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);  in d40_config_write()
1655 		regs[i] = readl(base->virtbase + il[i].src);  in d40_handle_interrupt()
1683 		writel(BIT(idx), base->virtbase + il[row].clr);  in d40_handle_interrupt()
2061 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in d40_is_paused()
2063 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in d40_is_paused()
2321 	writel(bit, d40c->base->virtbase + prioreg + group * 4);  in __d40_set_prio_rt()
2322 	writel(bit, d40c->base->virtbase + rtreg + group * 4);  in __d40_set_prio_rt()
2962 		addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;  in d40_save_restore_registers()
2972 	dma40_backup(base->virtbase, base->reg_val_backup,  in d40_save_restore_registers()
2978 		dma40_backup(base->virtbase, base->reg_val_backup_v4,  in d40_save_restore_registers()
2993 			       base->virtbase + D40_DREG_GCC);  in dma40_runtime_suspend()
3005 		       base->virtbase + D40_DREG_GCC);  in dma40_runtime_resume()
3027 	val[0] = readl(base->virtbase + D40_DREG_PRSME);  in d40_phy_res_init()
3028 	val[1] = readl(base->virtbase + D40_DREG_PRSMO);  in d40_phy_res_init()
3078 	val[0] = readl(base->virtbase + D40_DREG_PRTYP);  in d40_phy_res_init()
3097 	writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_phy_res_init()
3107 	void __iomem *virtbase;  in d40_hw_detect_init()  local
3140 	virtbase = ioremap(res->start, resource_size(res));  in d40_hw_detect_init()
3141 	if (!virtbase)  in d40_hw_detect_init()
3146 		pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)  in d40_hw_detect_init()
3149 		cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)  in d40_hw_detect_init()
3181 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;  in d40_hw_detect_init()
3209 	base->virtbase = virtbase;  in d40_hw_detect_init()
3305 	iounmap(virtbase);  in d40_hw_detect_init()
3330 		       base->virtbase + dma_init_reg[i].reg);  in d40_hw_init()
3355 	writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);  in d40_hw_init()
3356 	writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);  in d40_hw_init()
3357 	writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);  in d40_hw_init()
3358 	writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);  in d40_hw_init()
3361 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);  in d40_hw_init()
3364 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);  in d40_hw_init()
3447 	       base->virtbase + D40_DREG_LCLA);  in d40_lcla_allocate()
3556 	val = readl(base->virtbase + D40_DREG_LCPA);  in d40_probe()
3562 		writel(res->start, base->virtbase + D40_DREG_LCPA);  in d40_probe()
3587 		writel(res->start, base->virtbase + D40_DREG_LCLA);  in d40_probe()
3631 	writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_probe()
3663 	if (base->virtbase)  in d40_probe()
3664 		iounmap(base->virtbase);  in d40_probe()