Lines Matching refs:m
13 static void (*decode_dram_ecc)(int node_id, struct mce *m);
764 static void decode_mc0_mce(struct mce *m) in decode_mc0_mce() argument
766 u16 ec = EC(m->status); in decode_mc0_mce()
767 u8 xec = XEC(m->status, xec_mask); in decode_mc0_mce()
874 static void decode_mc1_mce(struct mce *m) in decode_mc1_mce() argument
876 u16 ec = EC(m->status); in decode_mc1_mce()
877 u8 xec = XEC(m->status, xec_mask); in decode_mc1_mce()
885 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); in decode_mc1_mce()
1020 static void decode_mc2_mce(struct mce *m) in decode_mc2_mce() argument
1022 u16 ec = EC(m->status); in decode_mc2_mce()
1023 u8 xec = XEC(m->status, xec_mask); in decode_mc2_mce()
1031 static void decode_mc3_mce(struct mce *m) in decode_mc3_mce() argument
1033 u16 ec = EC(m->status); in decode_mc3_mce()
1034 u8 xec = XEC(m->status, xec_mask); in decode_mc3_mce()
1060 static void decode_mc4_mce(struct mce *m) in decode_mc4_mce() argument
1062 unsigned int fam = x86_family(m->cpuid); in decode_mc4_mce()
1063 int node_id = topology_die_id(m->extcpu); in decode_mc4_mce()
1064 u16 ec = EC(m->status); in decode_mc4_mce()
1065 u8 xec = XEC(m->status, 0x1f); in decode_mc4_mce()
1082 decode_dram_ecc(node_id, m); in decode_mc4_mce()
1118 static void decode_mc5_mce(struct mce *m) in decode_mc5_mce() argument
1120 unsigned int fam = x86_family(m->cpuid); in decode_mc5_mce()
1121 u16 ec = EC(m->status); in decode_mc5_mce()
1122 u8 xec = XEC(m->status, xec_mask); in decode_mc5_mce()
1150 static void decode_mc6_mce(struct mce *m) in decode_mc6_mce() argument
1152 u8 xec = XEC(m->status, xec_mask); in decode_mc6_mce()
1167 static void decode_smca_error(struct mce *m) in decode_smca_error() argument
1169 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in decode_smca_error()
1171 u8 xec = XEC(m->status, xec_mask); in decode_smca_error()
1177 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); in decode_smca_error()
1190 decode_dram_ecc(topology_die_id(m->extcpu), m); in decode_smca_error()
1217 static const char *decode_error_status(struct mce *m) in decode_error_status() argument
1219 if (m->status & MCI_STATUS_UC) { in decode_error_status()
1220 if (m->status & MCI_STATUS_PCC) in decode_error_status()
1222 if (m->mcgstatus & MCG_STATUS_RIPV) in decode_error_status()
1227 if (m->status & MCI_STATUS_DEFERRED) in decode_error_status()
1236 struct mce *m = (struct mce *)data; in amd_decode_mce() local
1237 unsigned int fam = x86_family(m->cpuid); in amd_decode_mce()
1240 if (m->kflags & MCE_HANDLED_CEC) in amd_decode_mce()
1243 pr_emerg(HW_ERR "%s\n", decode_error_status(m)); in amd_decode_mce()
1246 m->extcpu, in amd_decode_mce()
1247 fam, x86_model(m->cpuid), x86_stepping(m->cpuid), in amd_decode_mce()
1248 m->bank, in amd_decode_mce()
1249 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), in amd_decode_mce()
1250 ((m->status & MCI_STATUS_UC) ? "UE" : in amd_decode_mce()
1251 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), in amd_decode_mce()
1252 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), in amd_decode_mce()
1253 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), in amd_decode_mce()
1254 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); in amd_decode_mce()
1258 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); in amd_decode_mce()
1262 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); in amd_decode_mce()
1264 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); in amd_decode_mce()
1268 ecc = (m->status >> 45) & 0x3; in amd_decode_mce()
1273 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); in amd_decode_mce()
1276 if (fam != 0x15 || m->bank != 4) in amd_decode_mce()
1277 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); in amd_decode_mce()
1281 pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); in amd_decode_mce()
1283 pr_cont("]: 0x%016llx\n", m->status); in amd_decode_mce()
1285 if (m->status & MCI_STATUS_ADDRV) in amd_decode_mce()
1286 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); in amd_decode_mce()
1288 if (m->ppin) in amd_decode_mce()
1289 pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin); in amd_decode_mce()
1292 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); in amd_decode_mce()
1294 if (m->status & MCI_STATUS_SYNDV) in amd_decode_mce()
1295 pr_cont(", Syndrome: 0x%016llx", m->synd); in amd_decode_mce()
1299 decode_smca_error(m); in amd_decode_mce()
1303 if (m->tsc) in amd_decode_mce()
1304 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); in amd_decode_mce()
1310 switch (m->bank) { in amd_decode_mce()
1312 decode_mc0_mce(m); in amd_decode_mce()
1316 decode_mc1_mce(m); in amd_decode_mce()
1320 decode_mc2_mce(m); in amd_decode_mce()
1324 decode_mc3_mce(m); in amd_decode_mce()
1328 decode_mc4_mce(m); in amd_decode_mce()
1332 decode_mc5_mce(m); in amd_decode_mce()
1336 decode_mc6_mce(m); in amd_decode_mce()
1344 amd_decode_err_code(m->status & 0xffff); in amd_decode_mce()
1346 m->kflags |= MCE_HANDLED_EDAC; in amd_decode_mce()