28 	const unsigned long bank = io_port / 3;  in i8255_get_port()  local
31 	return ioread8(&ppi[bank].port[ppi_port]) & mask;  in i8255_get_port()
61 	const unsigned long bank = io_port / 3;  in i8255_set_port()  local
66 	spin_lock_irqsave(&state[bank].lock, flags);  in i8255_set_port()
68 	out_state = ioread8(&ppi[bank].port[ppi_port]);  in i8255_set_port()
70 	iowrite8(out_state, &ppi[bank].port[ppi_port]);  in i8255_set_port()
72 	spin_unlock_irqrestore(&state[bank].lock, flags);  in i8255_set_port()
90 	const unsigned long bank = io_port / 3;  in i8255_direction_input()  local
93 	spin_lock_irqsave(&state[bank].lock, flags);  in i8255_direction_input()
95 	state[bank].control_state |= I8255_CONTROL_MODE_SET;  in i8255_direction_input()
96 	state[bank].control_state |= i8255_direction_mask(offset);  in i8255_direction_input()
98 	iowrite8(state[bank].control_state, &ppi[bank].control);  in i8255_direction_input()
100 	spin_unlock_irqrestore(&state[bank].lock, flags);  in i8255_direction_input()
122 	const unsigned long bank = io_port / 3;  in i8255_direction_output()  local
125 	spin_lock_irqsave(&state[bank].lock, flags);  in i8255_direction_output()
127 	state[bank].control_state |= I8255_CONTROL_MODE_SET;  in i8255_direction_output()
128 	state[bank].control_state &= ~i8255_direction_mask(offset);  in i8255_direction_output()
130 	iowrite8(state[bank].control_state, &ppi[bank].control);  in i8255_direction_output()
132 	spin_unlock_irqrestore(&state[bank].lock, flags);  in i8255_direction_output()
166 	const unsigned long bank = io_port / 3;  in i8255_get_direction()  local
168 	return !!(state[bank].control_state & i8255_direction_mask(offset));  in i8255_get_direction()
278 	unsigned long bank;  in i8255_state_init()  local
280 	for (bank = 0; bank < nbanks; bank++)  in i8255_state_init()
281 		spin_lock_init(&state[bank].lock);  in i8255_state_init()