Lines Matching refs:bank
76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
93 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
105 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
108 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
126 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl_bit()
129 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_readl_bit()
143 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_get_direction() local
146 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); in rockchip_gpio_get_direction()
156 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_set_direction() local
162 pinctrl_gpio_direction_input(bank->pin_base + offset); in rockchip_gpio_set_direction()
164 pinctrl_gpio_direction_output(bank->pin_base + offset); in rockchip_gpio_set_direction()
166 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_direction()
167 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); in rockchip_gpio_set_direction()
168 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_direction()
176 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set() local
179 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
180 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); in rockchip_gpio_set()
181 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
186 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_get() local
189 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
200 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set_debounce() local
201 const struct rockchip_gpio_regs *reg = bank->gpio_regs; in rockchip_gpio_set_debounce()
207 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { in rockchip_gpio_set_debounce()
209 freq = clk_get_rate(bank->db_clk); in rockchip_gpio_set_debounce()
220 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
226 cur_div_reg = readl(bank->reg_base + in rockchip_gpio_set_debounce()
229 writel(div_reg, bank->reg_base + in rockchip_gpio_set_debounce()
231 rockchip_gpio_writel_bit(bank, offset, 1, in rockchip_gpio_set_debounce()
235 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); in rockchip_gpio_set_debounce()
238 rockchip_gpio_writel_bit(bank, offset, 0, in rockchip_gpio_set_debounce()
241 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); in rockchip_gpio_set_debounce()
244 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
249 clk_prepare_enable(bank->db_clk); in rockchip_gpio_set_debounce()
251 clk_disable_unprepare(bank->db_clk); in rockchip_gpio_set_debounce()
307 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_to_irq() local
310 if (!bank->domain) in rockchip_gpio_to_irq()
313 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
334 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); in rockchip_irq_demux() local
338 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
342 pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); in rockchip_irq_demux()
344 dev_dbg(bank->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
350 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
354 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
355 bank->gpio_regs->ext_port); in rockchip_irq_demux()
357 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
359 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
360 bank->gpio_regs->int_polarity); in rockchip_irq_demux()
366 bank->reg_base + in rockchip_irq_demux()
367 bank->gpio_regs->int_polarity); in rockchip_irq_demux()
369 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
372 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
373 bank->gpio_regs->ext_port); in rockchip_irq_demux()
377 generic_handle_domain_irq(bank->domain, irq); in rockchip_irq_demux()
386 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type() local
394 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
396 rockchip_gpio_writel_bit(bank, d->hwirq, 0, in rockchip_irq_set_type()
397 bank->gpio_regs->port_ddr); in rockchip_irq_set_type()
399 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
406 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
408 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); in rockchip_irq_set_type()
409 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); in rockchip_irq_set_type()
412 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_irq_set_type()
413 rockchip_gpio_writel_bit(bank, d->hwirq, 1, in rockchip_irq_set_type()
414 bank->gpio_regs->int_bothedge); in rockchip_irq_set_type()
417 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
424 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_irq_set_type()
431 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_irq_set_type()
432 rockchip_gpio_writel_bit(bank, d->hwirq, 0, in rockchip_irq_set_type()
433 bank->gpio_regs->int_bothedge); in rockchip_irq_set_type()
435 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
460 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); in rockchip_irq_set_type()
461 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); in rockchip_irq_set_type()
463 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
471 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_reqres() local
473 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); in rockchip_irq_reqres()
479 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_relres() local
481 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); in rockchip_irq_relres()
487 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend() local
489 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); in rockchip_irq_suspend()
490 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); in rockchip_irq_suspend()
496 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume() local
498 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); in rockchip_irq_resume()
511 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) in rockchip_interrupts_register() argument
517 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
519 if (!bank->domain) { in rockchip_interrupts_register()
520 dev_warn(bank->dev, "could not init irq domain for bank %s\n", in rockchip_interrupts_register()
521 bank->name); in rockchip_interrupts_register()
525 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
530 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
531 bank->name); in rockchip_interrupts_register()
532 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
536 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
537 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_interrupts_register()
542 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
543 gc->private = bank; in rockchip_interrupts_register()
544 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; in rockchip_interrupts_register()
545 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; in rockchip_interrupts_register()
557 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
564 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); in rockchip_interrupts_register()
565 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); in rockchip_interrupts_register()
566 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); in rockchip_interrupts_register()
569 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
570 rockchip_irq_demux, bank); in rockchip_interrupts_register()
575 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) in rockchip_gpiolib_register() argument
580 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
582 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
583 gc->base = bank->pin_base; in rockchip_gpiolib_register()
584 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
585 gc->label = bank->name; in rockchip_gpiolib_register()
586 gc->parent = bank->dev; in rockchip_gpiolib_register()
588 ret = gpiochip_add_data(gc, bank); in rockchip_gpiolib_register()
590 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", in rockchip_gpiolib_register()
605 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { in rockchip_gpiolib_register()
606 struct device_node *pctlnp = of_get_parent(bank->of_node); in rockchip_gpiolib_register()
620 dev_err(bank->dev, "Failed to add pin range\n"); in rockchip_gpiolib_register()
625 ret = rockchip_interrupts_register(bank); in rockchip_gpiolib_register()
627 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); in rockchip_gpiolib_register()
634 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
639 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) in rockchip_get_bank_data() argument
644 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
645 dev_err(bank->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
649 bank->reg_base = devm_ioremap_resource(bank->dev, &res); in rockchip_get_bank_data()
650 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
651 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
653 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
654 if (!bank->irq) in rockchip_get_bank_data()
657 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
658 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
659 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
661 clk_prepare_enable(bank->clk); in rockchip_get_bank_data()
662 id = readl(bank->reg_base + gpio_regs_v2.version_id); in rockchip_get_bank_data()
666 bank->gpio_regs = &gpio_regs_v2; in rockchip_get_bank_data()
667 bank->gpio_type = GPIO_TYPE_V2; in rockchip_get_bank_data()
668 bank->db_clk = of_clk_get(bank->of_node, 1); in rockchip_get_bank_data()
669 if (IS_ERR(bank->db_clk)) { in rockchip_get_bank_data()
670 dev_err(bank->dev, "cannot find debounce clk\n"); in rockchip_get_bank_data()
671 clk_disable_unprepare(bank->clk); in rockchip_get_bank_data()
675 bank->gpio_regs = &gpio_regs_v1; in rockchip_get_bank_data()
676 bank->gpio_type = GPIO_TYPE_V1; in rockchip_get_bank_data()
686 struct rockchip_pin_bank *bank; in rockchip_gpio_find_bank() local
690 bank = info->ctrl->pin_banks; in rockchip_gpio_find_bank()
691 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { in rockchip_gpio_find_bank()
692 if (bank->bank_num == id) { in rockchip_gpio_find_bank()
698 return found ? bank : NULL; in rockchip_gpio_find_bank()
707 struct rockchip_pin_bank *bank = NULL; in rockchip_gpio_probe() local
723 bank = rockchip_gpio_find_bank(pctldev, id); in rockchip_gpio_probe()
724 if (!bank) in rockchip_gpio_probe()
727 bank->dev = dev; in rockchip_gpio_probe()
728 bank->of_node = np; in rockchip_gpio_probe()
730 raw_spin_lock_init(&bank->slock); in rockchip_gpio_probe()
732 ret = rockchip_get_bank_data(bank); in rockchip_gpio_probe()
740 mutex_lock(&bank->deferred_lock); in rockchip_gpio_probe()
742 ret = rockchip_gpiolib_register(bank); in rockchip_gpio_probe()
744 clk_disable_unprepare(bank->clk); in rockchip_gpio_probe()
745 mutex_unlock(&bank->deferred_lock); in rockchip_gpio_probe()
749 while (!list_empty(&bank->deferred_pins)) { in rockchip_gpio_probe()
750 cfg = list_first_entry(&bank->deferred_pins, in rockchip_gpio_probe()
756 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); in rockchip_gpio_probe()
762 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); in rockchip_gpio_probe()
773 mutex_unlock(&bank->deferred_lock); in rockchip_gpio_probe()
775 platform_set_drvdata(pdev, bank); in rockchip_gpio_probe()
783 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); in rockchip_gpio_remove() local
785 clk_disable_unprepare(bank->clk); in rockchip_gpio_remove()
786 gpiochip_remove(&bank->gpio_chip); in rockchip_gpio_remove()