Lines Matching refs:ih_regs
48 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_0_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_0_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI); in ih_v6_0_init_register_offset()
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; in ih_v6_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_0_init_register_offset()
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); in ih_v6_0_init_register_offset()
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1); in ih_v6_0_init_register_offset()
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v6_0_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v6_0_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v6_0_init_register_offset()
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1); in ih_v6_0_init_register_offset()
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; in ih_v6_0_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_toggle_ring_interrupts() local
134 ih_regs = &ih->ih_regs; in ih_v6_0_toggle_ring_interrupts()
136 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v6_0_toggle_ring_interrupts()
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) in ih_v6_0_toggle_ring_interrupts()
146 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
153 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_toggle_ring_interrupts()
154 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_toggle_ring_interrupts()
240 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_enable_ring() local
243 ih_regs = &ih->ih_regs; in ih_v6_0_enable_ring()
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in ih_v6_0_enable_ring()
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in ih_v6_0_enable_ring()
249 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v6_0_enable_ring()
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in ih_v6_0_enable_ring()
264 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_enable_ring()
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_enable_ring()
275 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_enable_ring()
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih)); in ih_v6_0_enable_ring()
394 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_get_wptr() local
397 ih_regs = &ih->ih_regs; in ih_v6_0_get_wptr()
402 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
417 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_0_get_wptr()
419 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_get_wptr()
435 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_irq_rearm() local
437 ih_regs = &ih->ih_regs; in ih_v6_0_irq_rearm()
441 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
459 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_set_rptr() local
469 ih_regs = &ih->ih_regs; in ih_v6_0_set_rptr()
470 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_0_set_rptr()