28 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
40 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
41 	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
43 					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
44 					0, ip##_HWIP) & \
46 			      0, ip##_HWIP)
48 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \  argument
49 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,  …
51 					adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
52 					0, ip##_HWIP) & \
54 			0, ip##_HWIP)
56 #define RREG32_SOC15(ip, inst, reg) \  argument
57 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
58 			 0, ip##_HWIP)
60 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)  argument
62 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)  argument
64 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
65 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
66 			 AMDGPU_REGS_NO_KIQ, ip##_HWIP)
68 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
69 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_H…
71 #define WREG32_SOC15(ip, inst, reg, value) \  argument
72 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
73 			  value, 0, ip##_HWIP)
75 #define WREG32_SOC15_IP(ip, reg, value) \  argument
76 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
78 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \  argument
79 	 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
81 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
82 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
83 			     value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
85 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
86 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
87 			  value, 0, ip##_HWIP)
89 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \  argument
93 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
102 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
143 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
144 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
156 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
158 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
174 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
175 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
177 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
179 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
180 		__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
183 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
189 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
190 	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
191 			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
192 						   AMDGPU_REGS_RLC, ip##_HWIP) & \
194 			     AMDGPU_REGS_RLC, ip##_HWIP)
196 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
197 …_WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMD…
199 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
200 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…