120 #define SRI(reg_name, block, id)\  argument
124 #define SRI2(reg_name, block, id)\  argument
128 #define SRIR(var_name, reg_name, block, id)\  argument
132 #define SRII(reg_name, block, id)\  argument
136 #define SRII2(reg_name_pre, reg_name_post, id)\  argument
141 #define SRII_MPC_RMU(reg_name, block, id)\  argument
145 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
149 #define DCCG_SRII(reg_name, block, id)\  argument
153 #define VUPDATE_SRII(reg_name, block, id)\  argument
215 #define abm_regs(id)\  argument
235 #define audio_regs(id)\  argument
263 #define vpg_regs(id)\  argument
283 #define afmt_regs(id)\  argument
303 #define stream_enc_regs(id)\  argument
324 #define aux_regs(id)\  argument
336 #define hpd_regs(id)\  argument
349 #define link_regs(id, phyid)\  argument
382 #define panel_cntl_regs(id)\  argument
400 #define dpp_regs(id)\  argument
420 #define opp_regs(id)\  argument
440 #define aux_engine_regs(id)\  argument
455 #define dwbc_regs_dcn3(id)\  argument
472 #define mcif_wb_regs_dcn3(id)\  argument
489 #define dsc_regsDCN20(id)\  argument
531 #define optc_regs(id)\  argument
550 #define hubp_regs(id)\  argument
605 #define vmid_regs(id)\  argument
778 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }  argument
1275 		enum clock_source_id id,  in dcn301_clock_source_create()