155 #define SRI(reg_name, block, id)\  argument
159 #define SRI2(reg_name, block, id)\  argument
163 #define SRIR(var_name, reg_name, block, id)\  argument
167 #define SRII(reg_name, block, id)\  argument
171 #define SRII_MPC_RMU(reg_name, block, id)\  argument
175 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
179 #define DCCG_SRII(reg_name, block, id)\  argument
183 #define VUPDATE_SRII(reg_name, block, id)\  argument
224 #define abm_regs(id)\  argument
244 #define audio_regs(id)\  argument
272 #define vpg_regs(id)\  argument
298 #define afmt_regs(id)\  argument
321 #define apg_regs(id)\  argument
342 #define stream_enc_regs(id)\  argument
364 #define aux_regs(id)\  argument
377 #define hpd_regs(id)\  argument
390 #define link_regs(id, phyid)\  argument
425 #define hpo_dp_stream_encoder_reg_list(id)\  argument
446 #define hpo_dp_link_encoder_reg_list(id)\  argument
470 #define dpp_regs(id)\  argument
490 #define opp_regs(id)\  argument
510 #define aux_engine_regs(id)\  argument
526 #define dwbc_regs_dcn3(id)\  argument
543 #define mcif_wb_regs_dcn3(id)\  argument
560 #define dsc_regsDCN20(id)\  argument
603 #define optc_regs(id)\  argument
621 #define hubp_regs(id)\  argument
666 #define SRII2(reg_name_pre, reg_name_post, id)\  argument
775 #define vmid_regs(id)\  argument
978 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }  argument
1615 		enum clock_source_id id,  in dcn31_clock_source_create()