290 #define cbus_writeb(sii9234, offset, value) \  macro
331 		cbus_writeb(ctx, 0xE0 + i, 0xF2);  in sii9234_cbus_reset()
336 		cbus_writeb(ctx, 0xF0 + i, 0xF2);  in sii9234_cbus_reset()
345 	cbus_writeb(ctx, 0x07, 0xF2);  in sii9234_cbus_init()
346 	cbus_writeb(ctx, 0x40, 0x03);  in sii9234_cbus_init()
347 	cbus_writeb(ctx, 0x42, 0x06);  in sii9234_cbus_init()
348 	cbus_writeb(ctx, 0x36, 0x0C);  in sii9234_cbus_init()
349 	cbus_writeb(ctx, 0x3D, 0xFD);  in sii9234_cbus_init()
350 	cbus_writeb(ctx, 0x1C, 0x01);  in sii9234_cbus_init()
351 	cbus_writeb(ctx, 0x1D, 0x0F);  in sii9234_cbus_init()
352 	cbus_writeb(ctx, 0x44, 0x02);  in sii9234_cbus_init()
354 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);  in sii9234_cbus_init()
355 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,  in sii9234_cbus_init()
357 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,  in sii9234_cbus_init()
359 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);  in sii9234_cbus_init()
360 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);  in sii9234_cbus_init()
361 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,  in sii9234_cbus_init()
363 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,  in sii9234_cbus_init()
365 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,  in sii9234_cbus_init()
367 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);  in sii9234_cbus_init()
368 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,  in sii9234_cbus_init()
371 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);  in sii9234_cbus_init()
372 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);  in sii9234_cbus_init()
373 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,  in sii9234_cbus_init()
375 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,  in sii9234_cbus_init()
377 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);  in sii9234_cbus_init()
379 	cbus_writeb(ctx, 0x30, 0x01);  in sii9234_cbus_init()
383 	cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0);  in sii9234_cbus_init()
384 	cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0);  in sii9234_cbus_init()
675 	cbus_writeb(ctx, 0x07, 0x32);  in sii9234_mhl_established()
792 	cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF);  in sii9234_irq_thread()
793 	cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF);  in sii9234_irq_thread()
794 	cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1);  in sii9234_irq_thread()
795 	cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);  in sii9234_irq_thread()