121 	writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);  in hibmc_plane_atomic_update()
128 	       priv->mmio + HIBMC_CRT_FB_WIDTH);  in hibmc_plane_atomic_update()
131 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_plane_atomic_update()
135 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_plane_atomic_update()
165 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_dpms()
171 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_dpms()
183 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_enable()
205 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_disable()
259 	val = readl(priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
261 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
264 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
266 	writel(pll, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
271 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
276 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
281 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
323 	writel(pll2, priv->mmio + CRT_PLL2_HS);  in display_ctrl_adjust()
334 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);  in display_ctrl_adjust()
338 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);  in display_ctrl_adjust()
355 	writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);  in display_ctrl_adjust()
369 	writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);  in hibmc_crtc_mode_set_nofb()
372 	       priv->mmio + HIBMC_CRT_HORZ_TOTAL);  in hibmc_crtc_mode_set_nofb()
376 	       priv->mmio + HIBMC_CRT_HORZ_SYNC);  in hibmc_crtc_mode_set_nofb()
380 	       priv->mmio + HIBMC_CRT_VERT_TOTAL);  in hibmc_crtc_mode_set_nofb()
384 	       priv->mmio + HIBMC_CRT_VERT_SYNC);  in hibmc_crtc_mode_set_nofb()
404 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_begin()
432 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);  in hibmc_crtc_enable_vblank()
442 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);  in hibmc_crtc_disable_vblank()
448 	void __iomem   *mmio = priv->mmio;  in hibmc_crtc_load_lut()  local
464 		writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);  in hibmc_crtc_load_lut()
467 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_load_lut()
469 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_load_lut()