Lines Matching refs:smc_state
2300 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_smc_sp() argument
2307 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in ni_populate_smc_sp()
2309 smc_state->levels[ps->performance_level_count - 1].bSP = in ni_populate_smc_sp()
2396 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_smc_t() argument
2411 smc_state->levels[0].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2415 smc_state->levels[0].aT = cpu_to_be32(0); in ni_populate_smc_t()
2440 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; in ni_populate_smc_t()
2442 smc_state->levels[i].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2448 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); in ni_populate_smc_t()
2456 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_power_containment_values() argument
2477 if (smc_state->levelCount != state->performance_level_count) in ni_populate_power_containment_values()
2499 smc_state->levels[0].dpm2.MaxPS = 0; in ni_populate_power_containment_values()
2500 smc_state->levels[0].dpm2.NearTDPDec = 0; in ni_populate_power_containment_values()
2501 smc_state->levels[0].dpm2.AboveSafeInc = 0; in ni_populate_power_containment_values()
2502 smc_state->levels[0].dpm2.BelowSafeInc = 0; in ni_populate_power_containment_values()
2503 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0; in ni_populate_power_containment_values()
2527 smc_state->levels[i].dpm2.MaxPS = in ni_populate_power_containment_values()
2529 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC; in ni_populate_power_containment_values()
2530 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC; in ni_populate_power_containment_values()
2531 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC; in ni_populate_power_containment_values()
2532 smc_state->levels[i].stateFlags |= in ni_populate_power_containment_values()
2542 NISLANDS_SMC_SWSTATE *smc_state) in ni_populate_sq_ramping_values() argument
2554 if (smc_state->levelCount != state->performance_level_count) in ni_populate_sq_ramping_values()
2591 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); in ni_populate_sq_ramping_values()
2592 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); in ni_populate_sq_ramping_values()
2630 NISLANDS_SMC_SWSTATE *smc_state) in ni_convert_power_state_to_smc() argument
2639 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in ni_convert_power_state_to_smc()
2641 smc_state->levelCount = 0; in ni_convert_power_state_to_smc()
2648 &smc_state->levels[i]); in ni_convert_power_state_to_smc()
2649 smc_state->levels[i].arbRefreshState = in ni_convert_power_state_to_smc()
2656 smc_state->levels[i].displayWatermark = in ni_convert_power_state_to_smc()
2660 smc_state->levels[i].displayWatermark = (i < 2) ? in ni_convert_power_state_to_smc()
2664 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; in ni_convert_power_state_to_smc()
2666 smc_state->levels[i].ACIndex = 0; in ni_convert_power_state_to_smc()
2668 smc_state->levelCount++; in ni_convert_power_state_to_smc()
2674 ni_populate_smc_sp(rdev, radeon_state, smc_state); in ni_convert_power_state_to_smc()
2676 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state); in ni_convert_power_state_to_smc()
2680 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state); in ni_convert_power_state_to_smc()
2684 return ni_populate_smc_t(rdev, radeon_state, smc_state); in ni_convert_power_state_to_smc()
2693 NISLANDS_SMC_SWSTATE *smc_state; in ni_upload_sw_state() local
2694 size_t state_size = struct_size(smc_state, levels, in ni_upload_sw_state()
2698 smc_state = kzalloc(state_size, GFP_KERNEL); in ni_upload_sw_state()
2699 if (smc_state == NULL) in ni_upload_sw_state()
2702 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); in ni_upload_sw_state()
2706 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end); in ni_upload_sw_state()
2709 kfree(smc_state); in ni_upload_sw_state()