25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_reset()
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);  in flite_hw_clear_pending_irq()
49 	u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);  in flite_hw_get_interrupt_source()
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);  in flite_hw_clear_last_capture_end()
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_interrupt_mask()
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_start()
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);  in flite_hw_capture_stop()
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_test_pattern()
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_source_format()
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);  in flite_hw_set_source_format()
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);  in flite_hw_set_window_offset()
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);  in flite_hw_set_window_offset()
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);  in flite_hw_set_camera_port()
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_camera_bus()
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_pack12()
237 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
244 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);  in flite_hw_set_out_order()
252 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
255 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);  in flite_hw_set_dma_window()
258 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
261 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);  in flite_hw_set_dma_window()
275 		writel(buf->addr, dev->regs + FLITE_REG_CIOSA);  in flite_hw_set_dma_buffer()
277 		writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));  in flite_hw_set_dma_buffer()
279 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
281 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_set_dma_buffer()
291 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
293 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);  in flite_hw_mask_dma_buffer()
300 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
304 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
309 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);  in flite_hw_set_output_dma()
342 		u32 cfg = readl(dev->regs + registers[i].offset);  in flite_hw_dump_regs()