Lines Matching refs:pad_mii_rx
423 struct sja1105_cfg_pad_mii pad_mii_rx = {0}; in sja1105_cfg_pad_rx_config() local
426 if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR) in sja1105_cfg_pad_rx_config()
430 pad_mii_rx.d32_ih = 0; /* RXD[3:2] input stage hysteresis: */ in sja1105_cfg_pad_rx_config()
432 pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
434 pad_mii_rx.d10_ih = 0; /* RXD[1:0] input stage hysteresis: */ in sja1105_cfg_pad_rx_config()
436 pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
438 pad_mii_rx.ctrl_ih = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ in sja1105_cfg_pad_rx_config()
441 pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ in sja1105_cfg_pad_rx_config()
444 pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */ in sja1105_cfg_pad_rx_config()
446 pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */ in sja1105_cfg_pad_rx_config()
448 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ in sja1105_cfg_pad_rx_config()
450 sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK); in sja1105_cfg_pad_rx_config()
452 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port], in sja1105_cfg_pad_rx_config()