Lines Matching refs:pad_mii_tx
394 struct sja1105_cfg_pad_mii pad_mii_tx = {0}; in sja1105_rgmii_cfg_pad_tx_config() local
397 if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) in sja1105_rgmii_cfg_pad_tx_config()
401 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
403 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
405 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
407 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
409 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ in sja1105_rgmii_cfg_pad_tx_config()
410 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
411 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
412 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
413 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
414 sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK); in sja1105_rgmii_cfg_pad_tx_config()
416 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port], in sja1105_rgmii_cfg_pad_tx_config()