Lines Matching refs:dst
20 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) in xgene_set_bits() argument
25 *dst &= ~mask; in xgene_set_bits()
26 *dst |= (val << start) & mask; in xgene_set_bits()
139 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) argument
157 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) argument
158 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) argument
160 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) argument
161 #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) argument
162 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) argument
163 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) argument
164 #define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4) argument
165 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) argument
166 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) argument
205 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) argument
206 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) argument
207 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) argument
208 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) argument