2352 	ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;  in nvme_disable_ctrl()
2353 	ctrl->ctrl_config &= ~NVME_CC_ENABLE;  in nvme_disable_ctrl()
2355 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_disable_ctrl()
2387 		ctrl->ctrl_config = NVME_CC_CSS_CSI;  in nvme_enable_ctrl()
2389 		ctrl->ctrl_config = NVME_CC_CSS_NVM;  in nvme_enable_ctrl()
2392 		ctrl->ctrl_config |= NVME_CC_CRIME;  in nvme_enable_ctrl()
2394 	ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;  in nvme_enable_ctrl()
2395 	ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;  in nvme_enable_ctrl()
2396 	ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;  in nvme_enable_ctrl()
2397 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_enable_ctrl()
2402 	ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);  in nvme_enable_ctrl()
2427 		if (ctrl->ctrl_config & NVME_CC_CRIME)  in nvme_enable_ctrl()
2439 	ctrl->ctrl_config |= NVME_CC_ENABLE;  in nvme_enable_ctrl()
2440 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_enable_ctrl()
2453 	ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;  in nvme_shutdown_ctrl()
2454 	ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;  in nvme_shutdown_ctrl()
2456 	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);  in nvme_shutdown_ctrl()
4819 	return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));  in nvme_ctrl_pp_status()