Lines Matching refs:cr0
29 u32 cr0; member
273 u32 cr0 = 0; in dw_spi_prepare_cr0() local
277 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI); in dw_spi_prepare_cr0()
285 cr0 |= DW_PSSI_CTRLR0_SCPOL; in dw_spi_prepare_cr0()
287 cr0 |= DW_PSSI_CTRLR0_SCPHA; in dw_spi_prepare_cr0()
291 cr0 |= DW_PSSI_CTRLR0_SRL; in dw_spi_prepare_cr0()
294 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI); in dw_spi_prepare_cr0()
302 cr0 |= DW_HSSI_CTRLR0_SCPOL; in dw_spi_prepare_cr0()
304 cr0 |= DW_HSSI_CTRLR0_SCPHA; in dw_spi_prepare_cr0()
308 cr0 |= DW_HSSI_CTRLR0_SRL; in dw_spi_prepare_cr0()
312 cr0 |= DW_HSSI_CTRLR0_MST; in dw_spi_prepare_cr0()
315 return cr0; in dw_spi_prepare_cr0()
322 u32 cr0 = chip->cr0; in dw_spi_update_config() local
327 cr0 |= (cfg->dfs - 1) << dws->dfs_offset; in dw_spi_update_config()
331 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
334 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); in dw_spi_update_config()
336 dw_writel(dws, DW_SPI_CTRLR0, cr0); in dw_spi_update_config()
812 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()
868 u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0); in dw_spi_hw_init() local
872 cr0 = dw_readl(dws, DW_SPI_CTRLR0); in dw_spi_hw_init()
876 if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) { in dw_spi_hw_init()