Lines Matching refs:qspi
127 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
130 return readl(qspi->base + reg); in ti_qspi_read()
133 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
136 writel(val, qspi->base + reg); in ti_qspi_write()
141 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
145 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
149 if (!qspi->master->max_speed_hz) { in ti_qspi_setup()
150 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
154 spi->max_speed_hz = min(spi->max_speed_hz, qspi->master->max_speed_hz); in ti_qspi_setup()
156 ret = pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup()
158 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
162 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup()
163 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
165 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
172 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz) in ti_qspi_setup_clk() argument
174 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup_clk()
178 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup_clk()
181 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); in ti_qspi_setup_clk()
183 pm_runtime_resume_and_get(qspi->dev); in ti_qspi_setup_clk()
187 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
192 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
195 ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup_clk()
199 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup_clk()
200 pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup_clk()
203 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) in ti_qspi_restore_ctx() argument
205 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
207 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
210 static inline u32 qspi_is_busy(struct ti_qspi *qspi) in qspi_is_busy() argument
215 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
218 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
225 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) in ti_qspi_poll_wc() argument
231 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
237 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
243 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_write_msg() argument
252 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
257 if (qspi_is_busy(qspi)) in qspi_write_msg()
262 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
263 cmd, qspi->dc, *txbuf); in qspi_write_msg()
268 writel(data, qspi->base + in qspi_write_msg()
271 writel(data, qspi->base + in qspi_write_msg()
274 writel(data, qspi->base + in qspi_write_msg()
277 writel(data, qspi->base + in qspi_write_msg()
282 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
283 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
289 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
290 cmd, qspi->dc, *txbuf); in qspi_write_msg()
291 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
294 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
295 cmd, qspi->dc, *txbuf); in qspi_write_msg()
296 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
300 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_write_msg()
301 if (ti_qspi_poll_wc(qspi)) { in qspi_write_msg()
302 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
312 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_read_msg() argument
322 cmd = qspi->cmd; in qspi_read_msg()
338 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
339 if (qspi_is_busy(qspi)) in qspi_read_msg()
362 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_read_msg()
363 if (ti_qspi_poll_wc(qspi)) { in qspi_read_msg()
364 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
376 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3); in qspi_read_msg()
378 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2); in qspi_read_msg()
380 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1); in qspi_read_msg()
382 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
386 rx = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
398 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
401 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
411 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_transfer_msg() argument
417 ret = qspi_write_msg(qspi, t, count); in qspi_transfer_msg()
419 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
425 ret = qspi_read_msg(qspi, t, count); in qspi_transfer_msg()
427 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
437 struct ti_qspi *qspi = param; in ti_qspi_dma_callback() local
439 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
442 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, in ti_qspi_dma_xfer() argument
445 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
454 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
459 tx->callback_param = qspi; in ti_qspi_dma_xfer()
461 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
465 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
470 time_left = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
474 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
481 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, in ti_qspi_dma_bounce_buffer() argument
484 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
495 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
499 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
508 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, in ti_qspi_dma_xfer_sg() argument
512 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
519 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); in ti_qspi_dma_xfer_sg()
530 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_enable_memory_map() local
532 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); in ti_qspi_enable_memory_map()
533 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
534 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
538 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
539 qspi->current_cs = spi->chip_select; in ti_qspi_enable_memory_map()
544 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_disable_memory_map() local
546 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); in ti_qspi_disable_memory_map()
547 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
548 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
550 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
551 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
558 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup_mmap_read() local
574 ti_qspi_write(qspi, memval, in ti_qspi_setup_mmap_read()
580 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master); in ti_qspi_adjust_op_size() local
584 if (op->addr.val < qspi->mmap_size) { in ti_qspi_adjust_op_size()
586 if (op->addr.val + op->data.nbytes > qspi->mmap_size) { in ti_qspi_adjust_op_size()
587 max_len = qspi->mmap_size - op->addr.val; in ti_qspi_adjust_op_size()
610 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master); in ti_qspi_exec_mem_op() local
621 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
624 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
626 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) { in ti_qspi_exec_mem_op()
627 ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); in ti_qspi_exec_mem_op()
633 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
639 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); in ti_qspi_exec_mem_op()
643 ret = ti_qspi_dma_bounce_buffer(qspi, from, in ti_qspi_exec_mem_op()
648 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
652 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
665 struct ti_qspi *qspi = spi_master_get_devdata(master); in ti_qspi_start_transfer_one() local
673 qspi->dc = 0; in ti_qspi_start_transfer_one()
676 qspi->dc |= QSPI_CKPHA(spi->chip_select); in ti_qspi_start_transfer_one()
678 qspi->dc |= QSPI_CKPOL(spi->chip_select); in ti_qspi_start_transfer_one()
680 qspi->dc |= QSPI_CSPOL(spi->chip_select); in ti_qspi_start_transfer_one()
688 qspi->cmd = 0; in ti_qspi_start_transfer_one()
689 qspi->cmd |= QSPI_EN_CS(spi->chip_select); in ti_qspi_start_transfer_one()
690 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
692 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
694 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
696 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
700 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
706 ti_qspi_setup_clk(qspi, t->speed_hz); in ti_qspi_start_transfer_one()
707 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); in ti_qspi_start_transfer_one()
709 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
710 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
720 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
722 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
731 struct ti_qspi *qspi; in ti_qspi_runtime_resume() local
733 qspi = dev_get_drvdata(dev); in ti_qspi_runtime_resume()
734 ti_qspi_restore_ctx(qspi); in ti_qspi_runtime_resume()
739 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi) in ti_qspi_dma_cleanup() argument
741 if (qspi->rx_bb_addr) in ti_qspi_dma_cleanup()
742 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_dma_cleanup()
743 qspi->rx_bb_addr, in ti_qspi_dma_cleanup()
744 qspi->rx_bb_dma_addr); in ti_qspi_dma_cleanup()
746 if (qspi->rx_chan) in ti_qspi_dma_cleanup()
747 dma_release_channel(qspi->rx_chan); in ti_qspi_dma_cleanup()
759 struct ti_qspi *qspi; in ti_qspi_probe() local
767 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
785 qspi = spi_master_get_devdata(master); in ti_qspi_probe()
786 qspi->master = master; in ti_qspi_probe()
787 qspi->dev = &pdev->dev; in ti_qspi_probe()
788 platform_set_drvdata(pdev, qspi); in ti_qspi_probe()
811 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
819 mutex_init(&qspi->list_lock); in ti_qspi_probe()
821 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
822 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
823 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
829 qspi->ctrl_base = in ti_qspi_probe()
832 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
833 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
838 1, &qspi->ctrl_reg); in ti_qspi_probe()
846 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
847 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
848 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
862 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
863 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
864 dev_err(qspi->dev, in ti_qspi_probe()
866 qspi->rx_chan = NULL; in ti_qspi_probe()
870 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
872 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
874 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
875 dev_err(qspi->dev, in ti_qspi_probe()
877 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
880 master->dma_rx = qspi->rx_chan; in ti_qspi_probe()
881 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
883 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
886 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
887 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
888 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
891 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
892 qspi->mmap_base = NULL; in ti_qspi_probe()
896 qspi->mmap_enabled = false; in ti_qspi_probe()
897 qspi->current_cs = -1; in ti_qspi_probe()
903 ti_qspi_dma_cleanup(qspi); in ti_qspi_probe()
913 struct ti_qspi *qspi = platform_get_drvdata(pdev); in ti_qspi_remove() local
916 rc = spi_master_suspend(qspi->master); in ti_qspi_remove()
923 ti_qspi_dma_cleanup(qspi); in ti_qspi_remove()