Lines Matching refs:cc
32 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, in chipco_write32_masked() argument
36 value |= chipco_read32(cc, offset) & ~mask; in chipco_write32_masked()
37 chipco_write32(cc, offset, value); in chipco_write32_masked()
42 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, in ssb_chipco_set_clockmode() argument
45 struct ssb_device *ccdev = cc->dev; in ssb_chipco_set_clockmode()
57 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) in ssb_chipco_set_clockmode()
69 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in ssb_chipco_set_clockmode()
74 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); in ssb_chipco_set_clockmode()
76 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); in ssb_chipco_set_clockmode()
81 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); in ssb_chipco_set_clockmode()
84 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); in ssb_chipco_set_clockmode()
86 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, in ssb_chipco_set_clockmode()
87 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) | in ssb_chipco_set_clockmode()
94 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); in ssb_chipco_set_clockmode()
101 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); in ssb_chipco_set_clockmode()
108 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, in ssb_chipco_set_clockmode()
109 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & in ssb_chipco_set_clockmode()
119 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) in chipco_pctl_get_slowclksrc() argument
121 struct ssb_bus *bus = cc->dev->bus; in chipco_pctl_get_slowclksrc()
124 if (cc->dev->id.revision < 6) { in chipco_pctl_get_slowclksrc()
135 if (cc->dev->id.revision < 10) { in chipco_pctl_get_slowclksrc()
136 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); in chipco_pctl_get_slowclksrc()
150 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) in chipco_pctl_clockfreqlimit() argument
157 clocksrc = chipco_pctl_get_slowclksrc(cc); in chipco_pctl_clockfreqlimit()
158 if (cc->dev->id.revision < 6) { in chipco_pctl_clockfreqlimit()
169 } else if (cc->dev->id.revision < 10) { in chipco_pctl_clockfreqlimit()
175 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); in chipco_pctl_clockfreqlimit()
181 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); in chipco_pctl_clockfreqlimit()
211 static void chipco_powercontrol_init(struct ssb_chipcommon *cc) in chipco_powercontrol_init() argument
213 struct ssb_bus *bus = cc->dev->bus; in chipco_powercontrol_init()
217 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); in chipco_powercontrol_init()
219 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); in chipco_powercontrol_init()
222 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in chipco_powercontrol_init()
225 if (cc->dev->id.revision >= 10) { in chipco_powercontrol_init()
227 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, in chipco_powercontrol_init()
228 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & in chipco_powercontrol_init()
233 maxfreq = chipco_pctl_clockfreqlimit(cc, 1); in chipco_powercontrol_init()
234 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, in chipco_powercontrol_init()
236 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, in chipco_powercontrol_init()
242 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc) in pmu_fast_powerup_delay() argument
244 struct ssb_bus *bus = cc->dev->bus; in pmu_fast_powerup_delay()
259 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) in calc_fast_powerup_delay() argument
261 struct ssb_bus *bus = cc->dev->bus; in calc_fast_powerup_delay()
269 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { in calc_fast_powerup_delay()
270 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc); in calc_fast_powerup_delay()
274 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in calc_fast_powerup_delay()
277 minfreq = chipco_pctl_clockfreqlimit(cc, 0); in calc_fast_powerup_delay()
278 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); in calc_fast_powerup_delay()
282 cc->fast_pwrup_delay = tmp; in calc_fast_powerup_delay()
285 static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc) in ssb_chipco_alp_clock() argument
287 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) in ssb_chipco_alp_clock()
288 return ssb_pmu_get_alp_clock(cc); in ssb_chipco_alp_clock()
293 static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc) in ssb_chipco_watchdog_get_max_timer() argument
297 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { in ssb_chipco_watchdog_get_max_timer()
298 if (cc->dev->id.revision < 26) in ssb_chipco_watchdog_get_max_timer()
301 nb = (cc->dev->id.revision >= 37) ? 32 : 24; in ssb_chipco_watchdog_get_max_timer()
313 struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt); in ssb_chipco_watchdog_timer_set_wdt() local
315 if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB) in ssb_chipco_watchdog_timer_set_wdt()
318 return ssb_chipco_watchdog_timer_set(cc, ticks); in ssb_chipco_watchdog_timer_set_wdt()
323 struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt); in ssb_chipco_watchdog_timer_set_ms() local
326 if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB) in ssb_chipco_watchdog_timer_set_ms()
329 ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); in ssb_chipco_watchdog_timer_set_ms()
330 return ticks / cc->ticks_per_ms; in ssb_chipco_watchdog_timer_set_ms()
333 static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc) in ssb_chipco_watchdog_ticks_per_ms() argument
335 struct ssb_bus *bus = cc->dev->bus; in ssb_chipco_watchdog_ticks_per_ms()
337 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { in ssb_chipco_watchdog_ticks_per_ms()
341 if (cc->dev->id.revision < 18) in ssb_chipco_watchdog_ticks_per_ms()
344 return ssb_chipco_alp_clock(cc) / 1000; in ssb_chipco_watchdog_ticks_per_ms()
348 void ssb_chipcommon_init(struct ssb_chipcommon *cc) in ssb_chipcommon_init() argument
350 if (!cc->dev) in ssb_chipcommon_init()
353 spin_lock_init(&cc->gpio_lock); in ssb_chipcommon_init()
355 if (cc->dev->id.revision >= 11) in ssb_chipcommon_init()
356 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); in ssb_chipcommon_init()
357 dev_dbg(cc->dev->dev, "chipcommon status is 0x%x\n", cc->status); in ssb_chipcommon_init()
359 if (cc->dev->id.revision >= 20) { in ssb_chipcommon_init()
360 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); in ssb_chipcommon_init()
361 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0); in ssb_chipcommon_init()
364 ssb_pmu_init(cc); in ssb_chipcommon_init()
365 chipco_powercontrol_init(cc); in ssb_chipcommon_init()
366 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); in ssb_chipcommon_init()
367 calc_fast_powerup_delay(cc); in ssb_chipcommon_init()
369 if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) { in ssb_chipcommon_init()
370 cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc); in ssb_chipcommon_init()
371 cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; in ssb_chipcommon_init()
375 void ssb_chipco_suspend(struct ssb_chipcommon *cc) in ssb_chipco_suspend() argument
377 if (!cc->dev) in ssb_chipco_suspend()
379 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); in ssb_chipco_suspend()
382 void ssb_chipco_resume(struct ssb_chipcommon *cc) in ssb_chipco_resume() argument
384 if (!cc->dev) in ssb_chipco_resume()
386 chipco_powercontrol_init(cc); in ssb_chipco_resume()
387 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); in ssb_chipco_resume()
391 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, in ssb_chipco_get_clockcpu() argument
394 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); in ssb_chipco_get_clockcpu()
395 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); in ssb_chipco_get_clockcpu()
401 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); in ssb_chipco_get_clockcpu()
405 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); in ssb_chipco_get_clockcpu()
408 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); in ssb_chipco_get_clockcpu()
414 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, in ssb_chipco_get_clockcontrol() argument
417 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); in ssb_chipco_get_clockcontrol()
418 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); in ssb_chipco_get_clockcontrol()
421 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); in ssb_chipco_get_clockcontrol()
424 if (cc->dev->bus->chip_id != 0x5365) { in ssb_chipco_get_clockcontrol()
425 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); in ssb_chipco_get_clockcontrol()
430 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); in ssb_chipco_get_clockcontrol()
434 void ssb_chipco_timing_init(struct ssb_chipcommon *cc, in ssb_chipco_timing_init() argument
437 struct ssb_device *dev = cc->dev; in ssb_chipco_timing_init()
442 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); in ssb_chipco_timing_init()
446 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ in ssb_chipco_timing_init()
454 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); in ssb_chipco_timing_init()
458 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); in ssb_chipco_timing_init()
466 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ in ssb_chipco_timing_init()
471 u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) in ssb_chipco_watchdog_timer_set() argument
476 maxt = ssb_chipco_watchdog_get_max_timer(cc); in ssb_chipco_watchdog_timer_set()
477 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { in ssb_chipco_watchdog_timer_set()
482 chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks); in ssb_chipco_watchdog_timer_set()
485 ssb_chipco_set_clockmode(cc, clkmode); in ssb_chipco_watchdog_timer_set()
489 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); in ssb_chipco_watchdog_timer_set()
494 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_irq_mask() argument
496 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value); in ssb_chipco_irq_mask()
499 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) in ssb_chipco_irq_status() argument
501 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask; in ssb_chipco_irq_status()
504 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) in ssb_chipco_gpio_in() argument
506 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; in ssb_chipco_gpio_in()
509 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_out() argument
514 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_out()
515 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); in ssb_chipco_gpio_out()
516 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_out()
521 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_outen() argument
526 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_outen()
527 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); in ssb_chipco_gpio_outen()
528 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_outen()
533 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_control() argument
538 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_control()
539 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); in ssb_chipco_gpio_control()
540 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_control()
546 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_intmask() argument
551 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_intmask()
552 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); in ssb_chipco_gpio_intmask()
553 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_intmask()
558 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_polarity() argument
563 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_polarity()
564 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); in ssb_chipco_gpio_polarity()
565 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_polarity()
570 u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_pullup() argument
575 if (cc->dev->id.revision < 20) in ssb_chipco_gpio_pullup()
578 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_pullup()
579 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value); in ssb_chipco_gpio_pullup()
580 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_pullup()
585 u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) in ssb_chipco_gpio_pulldown() argument
590 if (cc->dev->id.revision < 20) in ssb_chipco_gpio_pulldown()
593 spin_lock_irqsave(&cc->gpio_lock, flags); in ssb_chipco_gpio_pulldown()
594 res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value); in ssb_chipco_gpio_pulldown()
595 spin_unlock_irqrestore(&cc->gpio_lock, flags); in ssb_chipco_gpio_pulldown()
601 int ssb_chipco_serial_init(struct ssb_chipcommon *cc, in ssb_chipco_serial_init() argument
604 struct ssb_bus *bus = cc->dev->bus; in ssb_chipco_serial_init()
610 unsigned int ccrev = cc->dev->id.revision; in ssb_chipco_serial_init()
612 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); in ssb_chipco_serial_init()
613 irq = ssb_mips_irq(cc->dev); in ssb_chipco_serial_init()
618 chipco_read32(cc, SSB_CHIPCO_CLOCK_N), in ssb_chipco_serial_init()
619 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); in ssb_chipco_serial_init()
627 chipco_write32(cc, SSB_CHIPCO_CORECTL, in ssb_chipco_serial_init()
628 chipco_read32(cc, SSB_CHIPCO_CORECTL) in ssb_chipco_serial_init()
631 baud_base = ssb_chipco_alp_clock(cc); in ssb_chipco_serial_init()
635 chipco_write32(cc, SSB_CHIPCO_CORECTL, in ssb_chipco_serial_init()
636 chipco_read32(cc, SSB_CHIPCO_CORECTL) in ssb_chipco_serial_init()
640 chipco_write32(cc, SSB_CHIPCO_CORECTL, in ssb_chipco_serial_init()
641 chipco_read32(cc, SSB_CHIPCO_CORECTL) in ssb_chipco_serial_init()
645 chipco_write32(cc, SSB_CHIPCO_CORECTL, in ssb_chipco_serial_init()
646 chipco_read32(cc, SSB_CHIPCO_CORECTL) in ssb_chipco_serial_init()
652 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) in ssb_chipco_serial_init()
662 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { in ssb_chipco_serial_init()
663 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == in ssb_chipco_serial_init()
675 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); in ssb_chipco_serial_init()
680 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); in ssb_chipco_serial_init()