Lines Matching refs:tup
152 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
153 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
154 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
157 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
160 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
163 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
166 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
176 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
187 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
192 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
196 mcr = tup->mcr_shadow; in set_rts()
201 if (mcr != tup->mcr_shadow) { in set_rts()
202 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
203 tup->mcr_shadow = mcr; in set_rts()
207 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
211 mcr = tup->mcr_shadow; in set_dtr()
216 if (mcr != tup->mcr_shadow) { in set_dtr()
217 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
218 tup->mcr_shadow = mcr; in set_dtr()
222 static void set_loopbk(struct tegra_uart_port *tup, bool active) in set_loopbk() argument
224 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
231 if (mcr != tup->mcr_shadow) { in set_loopbk()
232 tegra_uart_write(tup, mcr, UART_MCR); in set_loopbk()
233 tup->mcr_shadow = mcr; in set_loopbk()
239 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
242 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
243 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
246 set_dtr(tup, enable); in tegra_uart_set_mctrl()
249 set_loopbk(tup, enable); in tegra_uart_set_mctrl()
254 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
257 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
262 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
263 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
275 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, in tegra_uart_wait_cycle_time() argument
278 if (tup->current_baud) in tegra_uart_wait_cycle_time()
279 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
283 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
286 if (tup->current_baud) in tegra_uart_wait_sym_time()
287 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
288 tup->current_baud)); in tegra_uart_wait_sym_time()
291 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) in tegra_uart_wait_fifo_mode_enabled() argument
297 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_wait_fifo_mode_enabled()
306 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
308 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
311 if (tup->rts_active) in tegra_uart_fifo_reset()
312 set_rts(tup, false); in tegra_uart_fifo_reset()
314 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
316 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
319 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
322 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
324 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
325 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
326 tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_fifo_reset()
330 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
337 tegra_uart_wait_cycle_time(tup, 32); in tegra_uart_fifo_reset()
340 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fifo_reset()
346 if (tup->rts_active) in tegra_uart_fifo_reset()
347 set_rts(tup, true); in tegra_uart_fifo_reset()
350 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, in tegra_get_tolerance_rate() argument
355 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
356 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
357 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
359 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
365 static int tegra_check_rate_in_range(struct tegra_uart_port *tup) in tegra_check_rate_in_range() argument
369 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
370 / tup->required_rate; in tegra_check_rate_in_range()
371 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
372 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
373 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
381 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
389 if (tup->current_baud == baud) in tegra_set_baudrate()
392 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
394 tup->required_rate = rate; in tegra_set_baudrate()
396 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
397 rate = tegra_get_tolerance_rate(tup, baud, rate); in tegra_set_baudrate()
399 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
401 dev_err(tup->uport.dev, in tegra_set_baudrate()
405 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
407 ret = tegra_check_rate_in_range(tup); in tegra_set_baudrate()
411 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
415 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_set_baudrate()
416 lcr = tup->lcr_shadow; in tegra_set_baudrate()
418 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
420 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
421 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
424 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
427 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
428 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_set_baudrate()
430 tup->current_baud = baud; in tegra_set_baudrate()
433 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
437 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
446 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
447 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
451 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
452 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
455 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
456 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
463 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
464 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
467 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
468 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
470 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
486 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
488 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
493 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
494 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
498 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
500 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
504 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
510 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
511 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
512 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
513 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
518 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
519 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
524 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
525 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
526 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
527 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
528 uart_xmit_advance(&tup->uport, count); in tegra_uart_tx_dma_complete()
529 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
531 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
532 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
533 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
536 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
539 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
542 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
543 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
545 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
546 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
548 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
549 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
551 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
552 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
556 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
557 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
558 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
559 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
560 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
561 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
565 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
569 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
571 if (!tup->current_baud) in tegra_uart_start_next_tx()
579 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
580 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
582 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
584 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
590 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
593 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
594 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
599 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
604 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
605 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
615 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
619 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
622 dmaengine_pause(tup->tx_dma_chan); in tegra_uart_stop_tx()
623 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
624 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
625 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
626 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
627 uart_xmit_advance(&tup->uport, count); in tegra_uart_stop_tx()
628 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
631 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
633 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
635 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
636 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
638 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
639 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
642 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
650 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
654 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
658 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
659 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
661 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
664 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
671 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
681 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
683 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
686 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
689 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
692 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
694 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
698 static void do_handle_rx_pio(struct tegra_uart_port *tup) in do_handle_rx_pio() argument
700 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
701 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
703 tegra_uart_handle_rx_pio(tup, port); in do_handle_rx_pio()
710 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, in tegra_uart_rx_buffer_push() argument
713 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
716 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
717 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
720 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_buffer_push()
722 do_handle_rx_pio(tup); in tegra_uart_rx_buffer_push()
727 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
728 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
735 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
738 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
743 if (tup->rts_active) in tegra_uart_rx_dma_complete()
744 set_rts(tup, false); in tegra_uart_rx_dma_complete()
746 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
747 tegra_uart_rx_buffer_push(tup, 0); in tegra_uart_rx_dma_complete()
748 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
751 if (tup->rts_active) in tegra_uart_rx_dma_complete()
752 set_rts(tup, true); in tegra_uart_rx_dma_complete()
758 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) in tegra_uart_terminate_rx_dma() argument
762 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
763 do_handle_rx_pio(tup); in tegra_uart_terminate_rx_dma()
767 dmaengine_pause(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
768 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
769 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
771 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_terminate_rx_dma()
772 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
775 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) in tegra_uart_handle_rx_dma() argument
778 if (tup->rts_active) in tegra_uart_handle_rx_dma()
779 set_rts(tup, false); in tegra_uart_handle_rx_dma()
781 tegra_uart_terminate_rx_dma(tup); in tegra_uart_handle_rx_dma()
783 if (tup->rts_active) in tegra_uart_handle_rx_dma()
784 set_rts(tup, true); in tegra_uart_handle_rx_dma()
787 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
791 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
794 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
795 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
797 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
798 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
802 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
803 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
804 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
805 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
806 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
807 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
813 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
816 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
821 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
823 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
826 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
829 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
834 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
835 struct uart_port *u = &tup->uport; in tegra_uart_isr()
844 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
846 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
847 tegra_uart_handle_rx_dma(tup); in tegra_uart_isr()
848 if (tup->rx_in_progress) { in tegra_uart_isr()
849 ier = tup->ier_shadow; in tegra_uart_isr()
852 tup->ier_shadow = ier; in tegra_uart_isr()
853 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
856 tegra_uart_start_rx_dma(tup); in tegra_uart_isr()
868 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
869 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
870 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
875 if (!tup->use_rx_pio) { in tegra_uart_isr()
876 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
878 ier = tup->ier_shadow; in tegra_uart_isr()
881 tup->ier_shadow = ier; in tegra_uart_isr()
882 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
887 if (!tup->use_rx_pio) { in tegra_uart_isr()
888 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
889 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
890 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
893 do_handle_rx_pio(tup); in tegra_uart_isr()
898 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
899 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
911 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
912 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
915 if (tup->rts_active) in tegra_uart_stop_rx()
916 set_rts(tup, false); in tegra_uart_stop_rx()
918 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
921 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */ in tegra_uart_stop_rx()
923 ier = tup->ier_shadow; in tegra_uart_stop_rx()
926 tup->ier_shadow = ier; in tegra_uart_stop_rx()
927 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
928 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
930 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
931 tegra_uart_terminate_rx_dma(tup); in tegra_uart_stop_rx()
933 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_stop_rx()
936 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
939 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
940 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
947 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
949 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
951 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
952 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
954 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
963 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
964 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
967 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
971 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
975 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
977 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
978 tup->current_baud = 0; in tegra_uart_hw_deinit()
979 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
981 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
982 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
984 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
985 tegra_uart_dma_channel_free(tup, true); in tegra_uart_hw_deinit()
986 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
987 tegra_uart_dma_channel_free(tup, false); in tegra_uart_hw_deinit()
989 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
992 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
996 tup->fcr_shadow = 0; in tegra_uart_hw_init()
997 tup->mcr_shadow = 0; in tegra_uart_hw_init()
998 tup->lcr_shadow = 0; in tegra_uart_hw_init()
999 tup->ier_shadow = 0; in tegra_uart_hw_init()
1000 tup->current_baud = 0; in tegra_uart_hw_init()
1002 ret = clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
1004 dev_err(tup->uport.dev, "could not enable clk\n"); in tegra_uart_hw_init()
1009 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1011 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1013 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1014 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1034 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1036 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1039 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1040 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1042 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1045 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1046 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1049 tegra_uart_read(tup, UART_SCR); in tegra_uart_hw_init()
1051 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1052 ret = tegra_uart_wait_fifo_mode_enabled(tup); in tegra_uart_hw_init()
1054 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1055 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1066 tegra_uart_wait_cycle_time(tup, 3); in tegra_uart_hw_init()
1074 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
1076 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1077 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1080 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1081 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1082 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1083 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1085 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1087 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1103 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1109 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1110 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1112 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1116 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
1120 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1121 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1122 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1123 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1124 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1125 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1126 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1128 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1129 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1130 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1132 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1133 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1134 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1138 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
1147 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1150 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1156 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1160 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1165 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1168 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1170 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1171 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1172 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1173 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1175 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1176 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
1178 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1179 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1183 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
1184 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1187 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1188 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1189 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1194 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1196 tegra_uart_dma_channel_free(tup, dma_to_memory); in tegra_uart_dma_channel_allocate()
1205 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
1208 if (!tup->use_tx_pio) { in tegra_uart_startup()
1209 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
1217 if (!tup->use_rx_pio) { in tegra_uart_startup()
1218 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1226 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1233 dev_name(u->dev), tup); in tegra_uart_startup()
1242 clk_disable_unprepare(tup->uart_clk); in tegra_uart_startup()
1244 if (!tup->use_rx_pio) in tegra_uart_startup()
1245 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1247 if (!tup->use_tx_pio) in tegra_uart_startup()
1248 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1258 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1260 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1261 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1262 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1267 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1269 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1270 free_irq(u->irq, tup); in tegra_uart_shutdown()
1275 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1277 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1278 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1279 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1287 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1292 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1294 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1301 if (tup->rts_active) in tegra_uart_set_termios()
1302 set_rts(tup, false); in tegra_uart_set_termios()
1305 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1306 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1307 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1308 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1311 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1339 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1340 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1341 tup->symb_bit = tty_get_frame_size(termios->c_cflag); in tegra_uart_set_termios()
1348 ret = tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1350 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1359 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1360 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1361 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1363 if (tup->rts_active) in tegra_uart_set_termios()
1364 set_rts(tup, true); in tegra_uart_set_termios()
1366 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1367 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1368 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1375 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1378 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1379 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1381 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1384 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1386 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1423 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1438 tup->uport.line = port; in tegra_uart_parse_dt()
1440 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1445 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1450 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1456 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1457 tup->baud_tolerance = in tegra_uart_parse_dt()
1458 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1459 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1460 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1469 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1476 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1483 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1487 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1557 struct tegra_uart_port *tup; in tegra_uart_probe() local
1569 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1570 if (!tup) { in tegra_uart_probe()
1575 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1579 u = &tup->uport; in tegra_uart_probe()
1584 tup->cdata = cdata; in tegra_uart_probe()
1586 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1598 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1599 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1601 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1604 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1605 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1607 return PTR_ERR(tup->rst); in tegra_uart_probe()
1626 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1627 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1636 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1637 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1644 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1645 struct uart_port *u = &tup->uport; in tegra_uart_resume()