25 #define UDC_EPCTL_ADDR		0x00	/* Endpoint control */  macro
622 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_set_stall()
623 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
625 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
636 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_clear_stall()
638 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_stall()
650 				UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);  in pch_udc_ep_set_trfr_type()
712 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);  in pch_udc_ep_set_pd()
721 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_set_rrdy()
730 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_clear_rrdy()
878 	return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);  in pch_udc_read_ep_control()
888 	return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);  in pch_udc_clear_ep_control()
919 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);  in pch_udc_ep_set_nak()
932 	if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))  in pch_udc_ep_clear_nak()
945 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_nak()
963 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_fifo_flush()
1013 		pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1015 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1019 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()