Lines Matching refs:minfo
37 static void DAC1064_calcclock(const struct matrox_fb_info *minfo, in DAC1064_calcclock() argument
49 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p); in DAC1064_calcclock()
88 static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout) in DAC1064_setpclk() argument
94 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setpclk()
95 minfo->hw.DACclk[0] = m; in DAC1064_setpclk()
96 minfo->hw.DACclk[1] = n; in DAC1064_setpclk()
97 minfo->hw.DACclk[2] = p; in DAC1064_setpclk()
100 static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo, in DAC1064_setmclk() argument
104 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_setmclk()
108 if (minfo->devflags.noinit) { in DAC1064_setmclk()
110 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in DAC1064_setmclk()
111 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in DAC1064_setmclk()
112 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in DAC1064_setmclk()
116 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
131 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
133 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
142 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setmclk()
143 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m); in DAC1064_setmclk()
144 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n); in DAC1064_setmclk()
145 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p); in DAC1064_setmclk()
147 if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40) in DAC1064_setmclk()
158 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
160 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
165 static void g450_set_plls(struct matrox_fb_info *minfo) in g450_set_plls() argument
169 struct matrox_hw_state *hw = &minfo->hw; in g450_set_plls()
176 pixelmnp = minfo->crtc1.mnp; in g450_set_plls()
177 videomnp = minfo->crtc2.mnp; in g450_set_plls()
181 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
196 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in g450_set_plls()
197 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL); in g450_set_plls()
204 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in g450_set_plls()
205 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C); in g450_set_plls()
212 pxc = minfo->crtc1.pixclock; in g450_set_plls()
213 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) { in g450_set_plls()
214 pxc = minfo->crtc2.pixclock; in g450_set_plls()
216 if (minfo->chip == MGA_G550) { in g450_set_plls()
257 void DAC1064_global_init(struct matrox_fb_info *minfo) in DAC1064_global_init() argument
259 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_init()
265 if (minfo->devflags.g450dac) { in DAC1064_global_init()
269 switch (minfo->outputs[0].src) { in DAC1064_global_init()
278 switch (minfo->outputs[1].src) { in DAC1064_global_init()
283 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) { in DAC1064_global_init()
293 switch (minfo->outputs[2].src) { in DAC1064_global_init()
312 g450_set_plls(minfo); in DAC1064_global_init()
316 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) { in DAC1064_global_init()
319 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) { in DAC1064_global_init()
321 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) in DAC1064_global_init()
326 if (minfo->outputs[0].src != MATROXFB_SRC_NONE) in DAC1064_global_init()
331 void DAC1064_global_restore(struct matrox_fb_info *minfo) in DAC1064_global_restore() argument
333 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_restore()
335 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in DAC1064_global_restore()
336 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); in DAC1064_global_restore()
337 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in DAC1064_global_restore()
338 outDAC1064(minfo, 0x20, 0x04); in DAC1064_global_restore()
339 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type); in DAC1064_global_restore()
340 if (minfo->devflags.g450dac) { in DAC1064_global_restore()
341 outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC); in DAC1064_global_restore()
342 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in DAC1064_global_restore()
343 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); in DAC1064_global_restore()
344 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]); in DAC1064_global_restore()
349 static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m) in DAC1064_init_1() argument
351 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_1()
356 switch (minfo->fbcon.var.bits_per_pixel) { in DAC1064_init_1()
362 if (minfo->fbcon.var.green.length == 5) in DAC1064_init_1()
376 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl; in DAC1064_init_1()
382 DAC1064_global_init(minfo); in DAC1064_init_1()
386 static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m) in DAC1064_init_2() argument
388 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_2()
392 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */ in DAC1064_init_2()
400 } else if (minfo->fbcon.var.bits_per_pixel > 8) { in DAC1064_init_2()
401 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */ in DAC1064_init_2()
429 static void DAC1064_restore_1(struct matrox_fb_info *minfo) in DAC1064_restore_1() argument
431 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_restore_1()
439 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) || in DAC1064_restore_1()
440 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) || in DAC1064_restore_1()
441 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) { in DAC1064_restore_1()
442 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]); in DAC1064_restore_1()
443 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]); in DAC1064_restore_1()
444 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]); in DAC1064_restore_1()
451 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]); in DAC1064_restore_1()
455 DAC1064_global_restore(minfo); in DAC1064_restore_1()
460 static void DAC1064_restore_2(struct matrox_fb_info *minfo) in DAC1064_restore_2() argument
471 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]); in DAC1064_restore_2()
476 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]); in DAC1064_restore_2()
482 #define minfo ((struct matrox_fb_info*)out) in m1064_compute() macro
488 DAC1064_setpclk(minfo, m->pixclock); in m1064_compute()
493 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]); in m1064_compute()
495 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) in m1064_compute()
505 #undef minfo in m1064_compute()
516 #define minfo ((struct matrox_fb_info*)out) in g450_compute() macro
518 …m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C … in g450_compute()
520 m->pixclock = g450_mnp2f(minfo, m->mnp); in g450_compute()
523 #undef minfo in g450_compute()
536 static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m) in MGA1064_init() argument
538 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_init()
542 if (DAC1064_init_1(minfo, m)) return 1; in MGA1064_init()
543 if (matroxfb_vgaHWinit(minfo, m)) return 1; in MGA1064_init()
553 if (DAC1064_init_2(minfo, m)) return 1; in MGA1064_init()
559 static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m) in MGAG100_init() argument
561 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_init()
565 if (DAC1064_init_1(minfo, m)) return 1; in MGAG100_init()
567 if (matroxfb_vgaHWinit(minfo, m)) return 1; in MGAG100_init()
577 if (DAC1064_init_2(minfo, m)) return 1; in MGAG100_init()
583 static void MGA1064_ramdac_init(struct matrox_fb_info *minfo) in MGA1064_ramdac_init() argument
589 minfo->features.pll.vco_freq_min = 62000; in MGA1064_ramdac_init()
590 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
591 minfo->features.pll.feed_div_min = 100; in MGA1064_ramdac_init()
592 minfo->features.pll.feed_div_max = 127; in MGA1064_ramdac_init()
593 minfo->features.pll.in_div_min = 1; in MGA1064_ramdac_init()
594 minfo->features.pll.in_div_max = 31; in MGA1064_ramdac_init()
595 minfo->features.pll.post_shift_max = 3; in MGA1064_ramdac_init()
596 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL; in MGA1064_ramdac_init()
598 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333); in MGA1064_ramdac_init()
610 static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags, in MGAG100_progPixClock() argument
619 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS | in MGAG100_progPixClock()
626 outDAC1064(minfo, reg++, m); in MGAG100_progPixClock()
627 outDAC1064(minfo, reg++, n); in MGAG100_progPixClock()
628 outDAC1064(minfo, reg, p); in MGAG100_progPixClock()
640 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) in MGAG100_progPixClock()
646 selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK; in MGAG100_progPixClock()
652 outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk); in MGAG100_progPixClock()
653 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS); in MGAG100_progPixClock()
656 static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags, in MGAG100_setPixClock() argument
663 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p); in MGAG100_setPixClock()
664 MGAG100_progPixClock(minfo, flags, m, n, p); in MGAG100_setPixClock()
669 static int MGA1064_preinit(struct matrox_fb_info *minfo) in MGA1064_preinit() argument
674 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_preinit()
679 minfo->capable.text = 1; in MGA1064_preinit()
680 minfo->capable.vxres = vxres_mystique; in MGA1064_preinit()
682 minfo->outputs[0].output = &m1064; in MGA1064_preinit()
683 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGA1064_preinit()
684 minfo->outputs[0].data = minfo; in MGA1064_preinit()
685 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGA1064_preinit()
687 if (minfo->devflags.noinit) in MGA1064_preinit()
691 if (minfo->devflags.novga) in MGA1064_preinit()
693 if (minfo->devflags.nobios) in MGA1064_preinit()
695 if (minfo->devflags.nopciretry) in MGA1064_preinit()
697 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_preinit()
707 static void MGA1064_reset(struct matrox_fb_info *minfo) in MGA1064_reset() argument
712 MGA1064_ramdac_init(minfo); in MGA1064_reset()
717 static void g450_mclk_init(struct matrox_fb_info *minfo) in g450_mclk_init() argument
720 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03); in g450_mclk_init()
722 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
724 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) || in g450_mclk_init()
725 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) || in g450_mclk_init()
726 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) { in g450_mclk_init()
727 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); in g450_mclk_init()
733 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02; in g450_mclk_init()
734 outDAC1064(minfo, M1064_XPWRCTRL, pwr); in g450_mclk_init()
737 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); in g450_mclk_init()
740 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); in g450_mclk_init()
742 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
746 static void g450_memory_init(struct matrox_fb_info *minfo) in g450_memory_init() argument
749 minfo->hw.MXoptionReg &= ~0x001F8000; in g450_memory_init()
750 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
753 minfo->hw.MXoptionReg &= ~0x00207E00; in g450_memory_init()
754 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; in g450_memory_init()
755 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
756 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); in g450_memory_init()
758 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in g450_memory_init()
761 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); in g450_memory_init()
762 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in g450_memory_init()
763 mga_outl(M_MACCESS, minfo->values.reg.maccess); in g450_memory_init()
765 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); in g450_memory_init()
769 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { in g450_memory_init()
770 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); in g450_memory_init()
772 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); in g450_memory_init()
776 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; in g450_memory_init()
777 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
783 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { in g450_memory_init()
784 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); in g450_memory_init()
789 static void g450_preinit(struct matrox_fb_info *minfo) in g450_preinit() argument
796 minfo->hw.MXoptionReg &= 0xC0000100; in g450_preinit()
797 minfo->hw.MXoptionReg |= 0x00000020; in g450_preinit()
798 if (minfo->devflags.novga) in g450_preinit()
799 minfo->hw.MXoptionReg &= ~0x00000100; in g450_preinit()
800 if (minfo->devflags.nobios) in g450_preinit()
801 minfo->hw.MXoptionReg &= ~0x40000000; in g450_preinit()
802 if (minfo->devflags.nopciretry) in g450_preinit()
803 minfo->hw.MXoptionReg |= 0x20000000; in g450_preinit()
804 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; in g450_preinit()
805 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_preinit()
813 curctl = inDAC1064(minfo, M1064_XCURCTRL); in g450_preinit()
814 outDAC1064(minfo, M1064_XCURCTRL, 0); in g450_preinit()
819 g450_mclk_init(minfo); in g450_preinit()
820 g450_memory_init(minfo); in g450_preinit()
823 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A); in g450_preinit()
824 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B); in g450_preinit()
830 outDAC1064(minfo, M1064_XCURCTRL, curctl); in g450_preinit()
838 static int MGAG100_preinit(struct matrox_fb_info *minfo) in MGAG100_preinit() argument
843 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_preinit()
853 if (minfo->devflags.g450dac) { in MGAG100_preinit()
854 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */ in MGAG100_preinit()
856 minfo->features.pll.vco_freq_min = 62000; in MGAG100_preinit()
858 if (!minfo->features.pll.ref_freq) { in MGAG100_preinit()
859 minfo->features.pll.ref_freq = 27000; in MGAG100_preinit()
861 minfo->features.pll.feed_div_min = 7; in MGAG100_preinit()
862 minfo->features.pll.feed_div_max = 127; in MGAG100_preinit()
863 minfo->features.pll.in_div_min = 1; in MGAG100_preinit()
864 minfo->features.pll.in_div_max = 31; in MGAG100_preinit()
865 minfo->features.pll.post_shift_max = 3; in MGAG100_preinit()
866 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT; in MGAG100_preinit()
868 minfo->capable.text = 1; in MGAG100_preinit()
869 minfo->capable.vxres = vxres_g100; in MGAG100_preinit()
870 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100 in MGAG100_preinit()
871 ? minfo->devflags.sgram : 1; in MGAG100_preinit()
873 if (minfo->devflags.g450dac) { in MGAG100_preinit()
874 minfo->outputs[0].output = &g450out; in MGAG100_preinit()
876 minfo->outputs[0].output = &m1064; in MGAG100_preinit()
878 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGAG100_preinit()
879 minfo->outputs[0].data = minfo; in MGAG100_preinit()
880 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGAG100_preinit()
882 if (minfo->devflags.g450dac) { in MGAG100_preinit()
887 if (minfo->devflags.noinit) in MGAG100_preinit()
889 if (minfo->devflags.g450dac) { in MGAG100_preinit()
890 g450_preinit(minfo); in MGAG100_preinit()
895 if (minfo->devflags.novga) in MGAG100_preinit()
897 if (minfo->devflags.nobios) in MGAG100_preinit()
899 if (minfo->devflags.nopciretry) in MGAG100_preinit()
901 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
902 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333); in MGAG100_preinit()
904 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) { in MGAG100_preinit()
905 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
907 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
910 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
911 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
921 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
927 mga_writeb(minfo->video.vbase, 0x0000, 0xAA); in MGAG100_preinit()
928 mga_writeb(minfo->video.vbase, 0x0800, 0x55); in MGAG100_preinit()
929 mga_writeb(minfo->video.vbase, 0x4000, 0x55); in MGAG100_preinit()
931 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) { in MGAG100_preinit()
936 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) { in MGAG100_preinit()
937 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
939 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
941 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
942 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
944 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
945 if (minfo->devflags.sgram) in MGAG100_preinit()
947 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
948 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
953 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
956 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
959 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
961 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
962 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
964 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
965 if (minfo->devflags.sgram) in MGAG100_preinit()
967 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
968 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
973 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
976 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
980 static void MGAG100_reset(struct matrox_fb_info *minfo) in MGAG100_reset() argument
983 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_reset()
993 if (b == minfo->pcidev->bus->number) { in MGAG100_reset()
1000 if (!minfo->devflags.noinit) { in MGAG100_reset()
1003 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_reset()
1008 if (minfo->devflags.g450dac) { in MGAG100_reset()
1010 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in MGAG100_reset()
1011 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in MGAG100_reset()
1012 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in MGAG100_reset()
1014 …DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_… in MGAG100_reset()
1016 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in MGAG100_reset()
1017 if (minfo->devflags.dfp_type == -1) { in MGAG100_reset()
1018 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F); in MGAG100_reset()
1021 if (minfo->devflags.noinit) in MGAG100_reset()
1023 if (minfo->devflags.g450dac) { in MGAG100_reset()
1025 MGAG100_setPixClock(minfo, 4, 25175); in MGAG100_reset()
1026 MGAG100_setPixClock(minfo, 5, 28322); in MGAG100_reset()
1028 b = inDAC1064(minfo, M1064_XGENIODATA) & ~1; in MGAG100_reset()
1029 outDAC1064(minfo, M1064_XGENIODATA, b); in MGAG100_reset()
1030 b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1; in MGAG100_reset()
1031 outDAC1064(minfo, M1064_XGENIOCTRL, b); in MGAG100_reset()
1038 static void MGA1064_restore(struct matrox_fb_info *minfo) in MGA1064_restore() argument
1041 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_restore()
1049 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_restore()
1055 DAC1064_restore_1(minfo); in MGA1064_restore()
1056 matroxfb_vgaHWrestore(minfo); in MGA1064_restore()
1057 minfo->crtc1.panpos = -1; in MGA1064_restore()
1060 DAC1064_restore_2(minfo); in MGA1064_restore()
1065 static void MGAG100_restore(struct matrox_fb_info *minfo) in MGAG100_restore() argument
1068 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_restore()
1076 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_restore()
1079 DAC1064_restore_1(minfo); in MGAG100_restore()
1080 matroxfb_vgaHWrestore(minfo); in MGAG100_restore()
1081 if (minfo->devflags.support32MB) in MGAG100_restore()
1083 minfo->crtc1.panpos = -1; in MGAG100_restore()
1086 DAC1064_restore_2(minfo); in MGAG100_restore()