Lines Matching refs:u32
32 u32 sync_clk;
35 u32 cs_on; /* Assertion time */
36 u32 cs_rd_off; /* Read deassertion time */
37 u32 cs_wr_off; /* Write deassertion time */
40 u32 adv_on; /* Assertion time */
41 u32 adv_rd_off; /* Read deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
43 u32 adv_aad_mux_on; /* ADV assertion time for AAD */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
48 u32 we_on; /* WE assertion time */
49 u32 we_off; /* WE deassertion time */
52 u32 oe_on; /* OE assertion time */
53 u32 oe_off; /* OE deassertion time */
54 u32 oe_aad_mux_on; /* OE assertion time for AAD */
55 u32 oe_aad_mux_off; /* OE deassertion time for AAD */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
60 u32 rd_cycle; /* Total read cycle time */
61 u32 wr_cycle; /* Total write cycle time */
63 u32 bus_turnaround;
64 u32 cycle2cycle_delay;
66 u32 wait_monitoring;
67 u32 clk_activation;
70 u32 wr_access; /* WRACCESSTIME */
71 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
87 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
88 u32 t_avdp_w;
89 u32 t_aavdh; /* address hold time */
90 u32 t_oeasu; /* address setup to OE valid */
91 u32 t_aa; /* access time from ADV assertion */
92 u32 t_iaa; /* initial access time */
93 u32 t_oe; /* access time from OE assertion */
94 u32 t_ce; /* access time from CS asertion */
95 u32 t_rd_cycle; /* read cycle time */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
98 u32 t_oez; /* OE deassertion to high Z */
99 u32 t_weasu; /* address setup to WE valid */
100 u32 t_wpl; /* write assertion time */
101 u32 t_wph; /* write deassertion time */
102 u32 t_wr_cycle; /* write cycle time */
104 u32 clk;
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
108 u32 t_avdh; /* ADV hold time from clk */
109 u32 t_ach; /* address hold time from clk */
110 u32 t_rdyo; /* clk to ready valid */
112 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
113 u32 t_ce_avd; /* CS on to ADV on delay */
122 u32 cyc_iaa; /* initial access time in cycles */
148 u32 burst_len; /* page/burst length */
149 u32 device_width; /* device bus width (8 or 16 bit) */
150 u32 mux_add_data; /* multiplex address & data */
151 u32 wait_pin; /* wait-pin to be used */