41 	u32 mask = d->mask;  in irq_gc_mask_disable_reg()  local
44 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_reg()
45 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_reg()
61 	u32 mask = d->mask;  in irq_gc_mask_set_bit()  local
64 	*ct->mask_cache |= mask;  in irq_gc_mask_set_bit()
65 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_set_bit()
81 	u32 mask = d->mask;  in irq_gc_mask_clr_bit()  local
84 	*ct->mask_cache &= ~mask;  in irq_gc_mask_clr_bit()
85 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_clr_bit()
101 	u32 mask = d->mask;  in irq_gc_unmask_enable_reg()  local
104 	irq_reg_writel(gc, mask, ct->regs.enable);  in irq_gc_unmask_enable_reg()
105 	*ct->mask_cache |= mask;  in irq_gc_unmask_enable_reg()
118 	u32 mask = d->mask;  in irq_gc_ack_set_bit()  local
121 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_set_bit()
134 	u32 mask = ~d->mask;  in irq_gc_ack_clr_bit()  local
137 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_clr_bit()
157 	u32 mask = d->mask;  in irq_gc_mask_disable_and_ack_set()  local
160 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_and_ack_set()
161 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_and_ack_set()
162 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_mask_disable_and_ack_set()
174 	u32 mask = d->mask;  in irq_gc_eoi()  local
177 	irq_reg_writel(gc, mask, ct->regs.eoi);  in irq_gc_eoi()
193 	u32 mask = d->mask;  in irq_gc_set_wake()  local
195 	if (!(mask & gc->wake_enabled))  in irq_gc_set_wake()
200 		gc->wake_active |= mask;  in irq_gc_set_wake()
202 		gc->wake_active &= ~mask;  in irq_gc_set_wake()
260 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;  in irq_gc_init_mask_cache()
266 			mskreg = ct[i].regs.mask;  in irq_gc_init_mask_cache()
427 		data->mask = 1 << idx;  in irq_map_generic_chip()
501 				d->mask = 1 << (i - gc->irq_base);  in irq_setup_generic_chip()