36 	struct mt6797_afe_private *afe_priv = afe->platform_priv;  in mt6797_init_clock()  local
39 	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),  in mt6797_init_clock()
41 	if (!afe_priv->clk)  in mt6797_init_clock()
45 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt6797_init_clock()
46 		if (IS_ERR(afe_priv->clk[i])) {  in mt6797_init_clock()
49 				PTR_ERR(afe_priv->clk[i]));  in mt6797_init_clock()
50 			return PTR_ERR(afe_priv->clk[i]);  in mt6797_init_clock()
59 	struct mt6797_afe_private *afe_priv = afe->platform_priv;  in mt6797_afe_enable_clock()  local
62 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);  in mt6797_afe_enable_clock()
69 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);  in mt6797_afe_enable_clock()
76 	ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);  in mt6797_afe_enable_clock()
83 	ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],  in mt6797_afe_enable_clock()
84 			     afe_priv->clk[CLK_CLK26M]);  in mt6797_afe_enable_clock()
92 	ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);  in mt6797_afe_enable_clock()
102 	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);  in mt6797_afe_enable_clock()
104 	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);  in mt6797_afe_enable_clock()
106 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);  in mt6797_afe_enable_clock()
108 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);  in mt6797_afe_enable_clock()
115 	struct mt6797_afe_private *afe_priv = afe->platform_priv;  in mt6797_afe_disable_clock()  local
117 	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);  in mt6797_afe_disable_clock()
118 	clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);  in mt6797_afe_disable_clock()
119 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);  in mt6797_afe_disable_clock()
120 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);  in mt6797_afe_disable_clock()