1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 #include "i915_reg_defs.h"
31
32 enum drm_scaling_filter;
33 struct dpll;
34 struct drm_connector;
35 struct drm_device;
36 struct drm_display_mode;
37 struct drm_encoder;
38 struct drm_file;
39 struct drm_format_info;
40 struct drm_framebuffer;
41 struct drm_i915_gem_object;
42 struct drm_i915_private;
43 struct drm_mode_fb_cmd2;
44 struct drm_modeset_acquire_ctx;
45 struct drm_plane;
46 struct drm_plane_state;
47 struct i915_address_space;
48 struct i915_gtt_view;
49 struct intel_atomic_state;
50 struct intel_crtc;
51 struct intel_crtc_state;
52 struct intel_digital_port;
53 struct intel_dp;
54 struct intel_encoder;
55 struct intel_initial_plane_config;
56 struct intel_load_detect_pipe;
57 struct intel_plane;
58 struct intel_plane_state;
59 struct intel_power_domain_mask;
60 struct intel_remapped_info;
61 struct intel_rotation_info;
62 struct pci_dev;
63
64 enum i915_gpio {
65 GPIOA,
66 GPIOB,
67 GPIOC,
68 GPIOD,
69 GPIOE,
70 GPIOF,
71 GPIOG,
72 GPIOH,
73 __GPIOI_UNUSED,
74 GPIOJ,
75 GPIOK,
76 GPIOL,
77 GPIOM,
78 GPION,
79 GPIOO,
80 };
81
82 /*
83 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
84 * rest have consecutive values and match the enum values of transcoders
85 * with a 1:1 transcoder -> pipe mapping.
86 */
87 enum pipe {
88 INVALID_PIPE = -1,
89
90 PIPE_A = 0,
91 PIPE_B,
92 PIPE_C,
93 PIPE_D,
94 _PIPE_EDP,
95
96 I915_MAX_PIPES = _PIPE_EDP
97 };
98
99 #define pipe_name(p) ((p) + 'A')
100
101 enum transcoder {
102 INVALID_TRANSCODER = -1,
103 /*
104 * The following transcoders have a 1:1 transcoder -> pipe mapping,
105 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
106 * rest have consecutive values and match the enum values of the pipes
107 * they map to.
108 */
109 TRANSCODER_A = PIPE_A,
110 TRANSCODER_B = PIPE_B,
111 TRANSCODER_C = PIPE_C,
112 TRANSCODER_D = PIPE_D,
113
114 /*
115 * The following transcoders can map to any pipe, their enum value
116 * doesn't need to stay fixed.
117 */
118 TRANSCODER_EDP,
119 TRANSCODER_DSI_0,
120 TRANSCODER_DSI_1,
121 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
122 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
123
124 I915_MAX_TRANSCODERS
125 };
126
transcoder_name(enum transcoder transcoder)127 static inline const char *transcoder_name(enum transcoder transcoder)
128 {
129 switch (transcoder) {
130 case TRANSCODER_A:
131 return "A";
132 case TRANSCODER_B:
133 return "B";
134 case TRANSCODER_C:
135 return "C";
136 case TRANSCODER_D:
137 return "D";
138 case TRANSCODER_EDP:
139 return "EDP";
140 case TRANSCODER_DSI_A:
141 return "DSI A";
142 case TRANSCODER_DSI_C:
143 return "DSI C";
144 default:
145 return "<invalid>";
146 }
147 }
148
transcoder_is_dsi(enum transcoder transcoder)149 static inline bool transcoder_is_dsi(enum transcoder transcoder)
150 {
151 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
152 }
153
154 /*
155 * Global legacy plane identifier. Valid only for primary/sprite
156 * planes on pre-g4x, and only for primary planes on g4x-bdw.
157 */
158 enum i9xx_plane_id {
159 PLANE_A,
160 PLANE_B,
161 PLANE_C,
162 };
163
164 #define plane_name(p) ((p) + 'A')
165 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
166
167 /*
168 * Per-pipe plane identifier.
169 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
170 * number of planes per CRTC. Not all platforms really have this many planes,
171 * which means some arrays of size I915_MAX_PLANES may have unused entries
172 * between the topmost sprite plane and the cursor plane.
173 *
174 * This is expected to be passed to various register macros
175 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
176 */
177 enum plane_id {
178 PLANE_PRIMARY,
179 PLANE_SPRITE0,
180 PLANE_SPRITE1,
181 PLANE_SPRITE2,
182 PLANE_SPRITE3,
183 PLANE_SPRITE4,
184 PLANE_SPRITE5,
185 PLANE_CURSOR,
186
187 I915_MAX_PLANES,
188 };
189
190 #define for_each_plane_id_on_crtc(__crtc, __p) \
191 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
192 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
193
194 #define for_each_dbuf_slice(__dev_priv, __slice) \
195 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
196 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
197
198 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
199 for_each_dbuf_slice((__dev_priv), (__slice)) \
200 for_each_if((__mask) & BIT(__slice))
201
202 enum port {
203 PORT_NONE = -1,
204
205 PORT_A = 0,
206 PORT_B,
207 PORT_C,
208 PORT_D,
209 PORT_E,
210 PORT_F,
211 PORT_G,
212 PORT_H,
213 PORT_I,
214
215 /* tgl+ */
216 PORT_TC1 = PORT_D,
217 PORT_TC2,
218 PORT_TC3,
219 PORT_TC4,
220 PORT_TC5,
221 PORT_TC6,
222
223 /* XE_LPD repositions D/E offsets and bitfields */
224 PORT_D_XELPD = PORT_TC5,
225 PORT_E_XELPD,
226
227 I915_MAX_PORTS
228 };
229
230 #define port_name(p) ((p) + 'A')
231
232 /*
233 * Ports identifier referenced from other drivers.
234 * Expected to remain stable over time
235 */
port_identifier(enum port port)236 static inline const char *port_identifier(enum port port)
237 {
238 switch (port) {
239 case PORT_A:
240 return "Port A";
241 case PORT_B:
242 return "Port B";
243 case PORT_C:
244 return "Port C";
245 case PORT_D:
246 return "Port D";
247 case PORT_E:
248 return "Port E";
249 case PORT_F:
250 return "Port F";
251 case PORT_G:
252 return "Port G";
253 case PORT_H:
254 return "Port H";
255 case PORT_I:
256 return "Port I";
257 default:
258 return "<invalid>";
259 }
260 }
261
262 enum tc_port {
263 TC_PORT_NONE = -1,
264
265 TC_PORT_1 = 0,
266 TC_PORT_2,
267 TC_PORT_3,
268 TC_PORT_4,
269 TC_PORT_5,
270 TC_PORT_6,
271
272 I915_MAX_TC_PORTS
273 };
274
275 enum tc_port_mode {
276 TC_PORT_DISCONNECTED,
277 TC_PORT_TBT_ALT,
278 TC_PORT_DP_ALT,
279 TC_PORT_LEGACY,
280 };
281
282 enum dpio_channel {
283 DPIO_CH0,
284 DPIO_CH1
285 };
286
287 enum dpio_phy {
288 DPIO_PHY0,
289 DPIO_PHY1,
290 DPIO_PHY2,
291 };
292
293 enum aux_ch {
294 AUX_CH_A,
295 AUX_CH_B,
296 AUX_CH_C,
297 AUX_CH_D,
298 AUX_CH_E, /* ICL+ */
299 AUX_CH_F,
300 AUX_CH_G,
301 AUX_CH_H,
302 AUX_CH_I,
303
304 /* tgl+ */
305 AUX_CH_USBC1 = AUX_CH_D,
306 AUX_CH_USBC2,
307 AUX_CH_USBC3,
308 AUX_CH_USBC4,
309 AUX_CH_USBC5,
310 AUX_CH_USBC6,
311
312 /* XE_LPD repositions D/E offsets and bitfields */
313 AUX_CH_D_XELPD = AUX_CH_USBC5,
314 AUX_CH_E_XELPD,
315 };
316
317 #define aux_ch_name(a) ((a) + 'A')
318
319 /* Used by dp and fdi links */
320 struct intel_link_m_n {
321 u32 tu;
322 u32 data_m;
323 u32 data_n;
324 u32 link_m;
325 u32 link_n;
326 };
327
328 enum phy {
329 PHY_NONE = -1,
330
331 PHY_A = 0,
332 PHY_B,
333 PHY_C,
334 PHY_D,
335 PHY_E,
336 PHY_F,
337 PHY_G,
338 PHY_H,
339 PHY_I,
340
341 I915_MAX_PHYS
342 };
343
344 #define phy_name(a) ((a) + 'A')
345
346 enum phy_fia {
347 FIA1,
348 FIA2,
349 FIA3,
350 };
351
352 enum hpd_pin {
353 HPD_NONE = 0,
354 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
355 HPD_CRT,
356 HPD_SDVO_B,
357 HPD_SDVO_C,
358 HPD_PORT_A,
359 HPD_PORT_B,
360 HPD_PORT_C,
361 HPD_PORT_D,
362 HPD_PORT_E,
363 HPD_PORT_TC1,
364 HPD_PORT_TC2,
365 HPD_PORT_TC3,
366 HPD_PORT_TC4,
367 HPD_PORT_TC5,
368 HPD_PORT_TC6,
369
370 HPD_NUM_PINS
371 };
372
373 #define for_each_hpd_pin(__pin) \
374 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
375
376 #define for_each_pipe(__dev_priv, __p) \
377 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
378 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
379
380 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
381 for_each_pipe(__dev_priv, __p) \
382 for_each_if((__mask) & BIT(__p))
383
384 #define for_each_cpu_transcoder(__dev_priv, __t) \
385 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
386 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
387
388 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
389 for_each_cpu_transcoder(__dev_priv, __t) \
390 for_each_if ((__mask) & BIT(__t))
391
392 #define for_each_sprite(__dev_priv, __p, __s) \
393 for ((__s) = 0; \
394 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
395 (__s)++)
396
397 #define for_each_port(__port) \
398 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
399
400 #define for_each_port_masked(__port, __ports_mask) \
401 for_each_port(__port) \
402 for_each_if((__ports_mask) & BIT(__port))
403
404 #define for_each_phy_masked(__phy, __phys_mask) \
405 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
406 for_each_if((__phys_mask) & BIT(__phy))
407
408 #define for_each_crtc(dev, crtc) \
409 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
410
411 #define for_each_intel_plane(dev, intel_plane) \
412 list_for_each_entry(intel_plane, \
413 &(dev)->mode_config.plane_list, \
414 base.head)
415
416 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
417 list_for_each_entry(intel_plane, \
418 &(dev)->mode_config.plane_list, \
419 base.head) \
420 for_each_if((plane_mask) & \
421 drm_plane_mask(&intel_plane->base))
422
423 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
424 list_for_each_entry(intel_plane, \
425 &(dev)->mode_config.plane_list, \
426 base.head) \
427 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
428
429 #define for_each_intel_crtc(dev, intel_crtc) \
430 list_for_each_entry(intel_crtc, \
431 &(dev)->mode_config.crtc_list, \
432 base.head)
433
434 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
435 list_for_each_entry(intel_crtc, \
436 &(dev)->mode_config.crtc_list, \
437 base.head) \
438 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
439
440 #define for_each_intel_encoder(dev, intel_encoder) \
441 list_for_each_entry(intel_encoder, \
442 &(dev)->mode_config.encoder_list, \
443 base.head)
444
445 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
446 list_for_each_entry(intel_encoder, \
447 &(dev)->mode_config.encoder_list, \
448 base.head) \
449 for_each_if((encoder_mask) & \
450 drm_encoder_mask(&intel_encoder->base))
451
452 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
453 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
454 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
455 intel_encoder_can_psr(intel_encoder))
456
457 #define for_each_intel_dp(dev, intel_encoder) \
458 for_each_intel_encoder(dev, intel_encoder) \
459 for_each_if(intel_encoder_is_dp(intel_encoder))
460
461 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
462 for_each_intel_encoder((dev), (intel_encoder)) \
463 for_each_if(intel_encoder_can_psr(intel_encoder))
464
465 #define for_each_intel_connector_iter(intel_connector, iter) \
466 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
467
468 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
469 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
470 for_each_if((intel_encoder)->base.crtc == (__crtc))
471
472 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
473 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
474 for_each_if((intel_connector)->base.encoder == (__encoder))
475
476 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
477 for ((__i) = 0; \
478 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
479 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
480 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
481 (__i)++) \
482 for_each_if(plane)
483
484 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
485 for ((__i) = 0; \
486 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
487 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
488 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
489 (__i)++) \
490 for_each_if(plane)
491
492 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
493 for ((__i) = 0; \
494 (__i) < (__state)->base.dev->mode_config.num_crtc && \
495 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
496 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
497 (__i)++) \
498 for_each_if(crtc)
499
500 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
501 for ((__i) = 0; \
502 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
503 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
504 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
505 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
506 (__i)++) \
507 for_each_if(plane)
508
509 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
510 for ((__i) = 0; \
511 (__i) < (__state)->base.dev->mode_config.num_crtc && \
512 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
513 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
514 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
515 (__i)++) \
516 for_each_if(crtc)
517
518 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
519 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
520 (__i) >= 0 && \
521 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
522 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
523 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
524 (__i)--) \
525 for_each_if(crtc)
526
527 #define intel_atomic_crtc_state_for_each_plane_state( \
528 plane, plane_state, \
529 crtc_state) \
530 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
531 ((crtc_state)->uapi.plane_mask)) \
532 for_each_if ((plane_state = \
533 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
534
535 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
536 for ((__i) = 0; \
537 (__i) < (__state)->base.num_connector; \
538 (__i)++) \
539 for_each_if ((__state)->base.connectors[__i].ptr && \
540 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
541 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
542
543 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
544 struct intel_crtc *crtc);
545 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
546 u8 active_pipes);
547 void intel_link_compute_m_n(u16 bpp, int nlanes,
548 int pixel_clock, int link_clock,
549 struct intel_link_m_n *m_n,
550 bool fec_enable);
551 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
552 u32 pixel_format, u64 modifier);
553 enum drm_mode_status
554 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
555 const struct drm_display_mode *mode,
556 bool bigjoiner);
557 enum drm_mode_status
558 intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
559 const struct drm_display_mode *mode);
560 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
561 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
562 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
563 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
564 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
565 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
566 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
567 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
568 const struct intel_crtc_state *pipe_config,
569 bool fastset);
570 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
571
572 void intel_plane_destroy(struct drm_plane *plane);
573 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
574 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
575 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
576 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
577 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
578 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
579 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
580 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
581 const char *name, u32 reg, int ref_freq);
582 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
583 const char *name, u32 reg);
584 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
585 unsigned int intel_fb_xy_to_linear(int x, int y,
586 const struct intel_plane_state *state,
587 int plane);
588 void intel_add_fb_offsets(int *x, int *y,
589 const struct intel_plane_state *state, int plane);
590 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
591 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
592 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
593 int intel_display_suspend(struct drm_device *dev);
594 void intel_encoder_destroy(struct drm_encoder *encoder);
595 struct drm_display_mode *
596 intel_encoder_current_mode(struct intel_encoder *encoder);
597 void intel_encoder_get_config(struct intel_encoder *encoder,
598 struct intel_crtc_state *crtc_state);
599 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
600 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
601 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
602 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
603 enum port port);
604 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *file_priv);
606
607 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
608 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
609 struct intel_digital_port *dig_port,
610 unsigned int expected_mask);
611 int intel_get_load_detect_pipe(struct drm_connector *connector,
612 struct intel_load_detect_pipe *old,
613 struct drm_modeset_acquire_ctx *ctx);
614 void intel_release_load_detect_pipe(struct drm_connector *connector,
615 struct intel_load_detect_pipe *old,
616 struct drm_modeset_acquire_ctx *ctx);
617 struct drm_framebuffer *
618 intel_framebuffer_create(struct drm_i915_gem_object *obj,
619 struct drm_mode_fb_cmd2 *mode_cmd);
620
621 bool intel_fuzzy_clock_check(int clock1, int clock2);
622
623 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
624 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
625 void intel_zero_m_n(struct intel_link_m_n *m_n);
626 void intel_set_m_n(struct drm_i915_private *i915,
627 const struct intel_link_m_n *m_n,
628 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
629 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
630 void intel_get_m_n(struct drm_i915_private *i915,
631 struct intel_link_m_n *m_n,
632 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
633 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
634 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
635 enum transcoder transcoder);
636 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
637 enum transcoder cpu_transcoder,
638 const struct intel_link_m_n *m_n);
639 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
640 enum transcoder cpu_transcoder,
641 const struct intel_link_m_n *m_n);
642 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
643 enum transcoder cpu_transcoder,
644 struct intel_link_m_n *m_n);
645 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
646 enum transcoder cpu_transcoder,
647 struct intel_link_m_n *m_n);
648 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
649 struct intel_crtc_state *pipe_config);
650 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
651 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
652 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
653 enum intel_display_power_domain
654 intel_aux_power_domain(struct intel_digital_port *dig_port);
655 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
656 struct intel_crtc_state *crtc_state);
657 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
658
659 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
660 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
661
662 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
663
664 struct intel_encoder *
665 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
666 const struct intel_crtc_state *crtc_state);
667 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
668 struct intel_plane *plane);
669 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
670 struct intel_plane_state *plane_state,
671 bool visible);
672 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
673
674 void intel_display_driver_register(struct drm_i915_private *i915);
675 void intel_display_driver_unregister(struct drm_i915_private *i915);
676
677 void intel_update_watermarks(struct drm_i915_private *i915);
678
679 /* modesetting */
680 bool intel_modeset_probe_defer(struct pci_dev *pdev);
681 void intel_modeset_init_hw(struct drm_i915_private *i915);
682 int intel_modeset_init_noirq(struct drm_i915_private *i915);
683 int intel_modeset_init_nogem(struct drm_i915_private *i915);
684 int intel_modeset_init(struct drm_i915_private *i915);
685 void intel_modeset_driver_remove(struct drm_i915_private *i915);
686 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
687 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
688 void intel_display_resume(struct drm_device *dev);
689 int intel_modeset_all_pipes(struct intel_atomic_state *state);
690 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
691 struct intel_power_domain_mask *old_domains);
692 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
693 struct intel_power_domain_mask *domains);
694
695 /* modesetting asserts */
696 void assert_transcoder(struct drm_i915_private *dev_priv,
697 enum transcoder cpu_transcoder, bool state);
698 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
699 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
700
701 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
702 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
703 * which may not necessarily be a user visible problem. This will either
704 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
705 * enable distros and users to tailor their preferred amount of i915 abrt
706 * spam.
707 */
708 #define I915_STATE_WARN(condition, format...) ({ \
709 int __ret_warn_on = !!(condition); \
710 if (unlikely(__ret_warn_on)) \
711 if (!WARN(i915_modparams.verbose_state_checks, format)) \
712 DRM_ERROR(format); \
713 unlikely(__ret_warn_on); \
714 })
715
716 #define I915_STATE_WARN_ON(x) \
717 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
718
719 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
720
721 #endif
722