1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Trevor Wu <trevor.wu@mediatek.com> 7 */ 8 9 #ifndef _MT8195_AUDSYS_CLKID_H_ 10 #define _MT8195_AUDSYS_CLKID_H_ 11 12 enum{ 13 CLK_AUD_AFE, 14 CLK_AUD_LRCK_CNT, 15 CLK_AUD_SPDIFIN_TUNER_APLL, 16 CLK_AUD_SPDIFIN_TUNER_DBG, 17 CLK_AUD_UL_TML, 18 CLK_AUD_APLL1_TUNER, 19 CLK_AUD_APLL2_TUNER, 20 CLK_AUD_TOP0_SPDF, 21 CLK_AUD_APLL, 22 CLK_AUD_APLL2, 23 CLK_AUD_DAC, 24 CLK_AUD_DAC_PREDIS, 25 CLK_AUD_TML, 26 CLK_AUD_ADC, 27 CLK_AUD_DAC_HIRES, 28 CLK_AUD_A1SYS_HP, 29 CLK_AUD_AFE_DMIC1, 30 CLK_AUD_AFE_DMIC2, 31 CLK_AUD_AFE_DMIC3, 32 CLK_AUD_AFE_DMIC4, 33 CLK_AUD_AFE_26M_DMIC_TM, 34 CLK_AUD_UL_TML_HIRES, 35 CLK_AUD_ADC_HIRES, 36 CLK_AUD_ADDA6_ADC, 37 CLK_AUD_ADDA6_ADC_HIRES, 38 CLK_AUD_LINEIN_TUNER, 39 CLK_AUD_EARC_TUNER, 40 CLK_AUD_I2SIN, 41 CLK_AUD_TDM_IN, 42 CLK_AUD_I2S_OUT, 43 CLK_AUD_TDM_OUT, 44 CLK_AUD_HDMI_OUT, 45 CLK_AUD_ASRC11, 46 CLK_AUD_ASRC12, 47 CLK_AUD_MULTI_IN, 48 CLK_AUD_INTDIR, 49 CLK_AUD_A1SYS, 50 CLK_AUD_A2SYS, 51 CLK_AUD_PCMIF, 52 CLK_AUD_A3SYS, 53 CLK_AUD_A4SYS, 54 CLK_AUD_MEMIF_UL1, 55 CLK_AUD_MEMIF_UL2, 56 CLK_AUD_MEMIF_UL3, 57 CLK_AUD_MEMIF_UL4, 58 CLK_AUD_MEMIF_UL5, 59 CLK_AUD_MEMIF_UL6, 60 CLK_AUD_MEMIF_UL8, 61 CLK_AUD_MEMIF_UL9, 62 CLK_AUD_MEMIF_UL10, 63 CLK_AUD_MEMIF_DL2, 64 CLK_AUD_MEMIF_DL3, 65 CLK_AUD_MEMIF_DL6, 66 CLK_AUD_MEMIF_DL7, 67 CLK_AUD_MEMIF_DL8, 68 CLK_AUD_MEMIF_DL10, 69 CLK_AUD_MEMIF_DL11, 70 CLK_AUD_GASRC0, 71 CLK_AUD_GASRC1, 72 CLK_AUD_GASRC2, 73 CLK_AUD_GASRC3, 74 CLK_AUD_GASRC4, 75 CLK_AUD_GASRC5, 76 CLK_AUD_GASRC6, 77 CLK_AUD_GASRC7, 78 CLK_AUD_GASRC8, 79 CLK_AUD_GASRC9, 80 CLK_AUD_GASRC10, 81 CLK_AUD_GASRC11, 82 CLK_AUD_GASRC12, 83 CLK_AUD_GASRC13, 84 CLK_AUD_GASRC14, 85 CLK_AUD_GASRC15, 86 CLK_AUD_GASRC16, 87 CLK_AUD_GASRC17, 88 CLK_AUD_GASRC18, 89 CLK_AUD_GASRC19, 90 CLK_AUD_NR_CLK, 91 }; 92 93 #endif 94