1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Texas Instruments Ethernet Switch Driver
4 */
5
6 #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
7 #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
8
9 #include <uapi/linux/bpf.h>
10
11 #include "davinci_cpdma.h"
12
13 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
14 NETIF_MSG_DRV | NETIF_MSG_LINK | \
15 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
16 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
17 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
18 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
19 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
20 NETIF_MSG_RX_STATUS)
21
22 #define cpsw_info(priv, type, format, ...) \
23 do { \
24 if (netif_msg_##type(priv) && net_ratelimit()) \
25 dev_info(priv->dev, format, ## __VA_ARGS__); \
26 } while (0)
27
28 #define cpsw_err(priv, type, format, ...) \
29 do { \
30 if (netif_msg_##type(priv) && net_ratelimit()) \
31 dev_err(priv->dev, format, ## __VA_ARGS__); \
32 } while (0)
33
34 #define cpsw_dbg(priv, type, format, ...) \
35 do { \
36 if (netif_msg_##type(priv) && net_ratelimit()) \
37 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
38 } while (0)
39
40 #define cpsw_notice(priv, type, format, ...) \
41 do { \
42 if (netif_msg_##type(priv) && net_ratelimit()) \
43 dev_notice(priv->dev, format, ## __VA_ARGS__); \
44 } while (0)
45
46 #define ALE_ALL_PORTS 0x7
47
48 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
49 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
50 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
51
52 #define CPSW_VERSION_1 0x19010a
53 #define CPSW_VERSION_2 0x19010c
54 #define CPSW_VERSION_3 0x19010f
55 #define CPSW_VERSION_4 0x190112
56
57 #define HOST_PORT_NUM 0
58 #define CPSW_ALE_PORTS_NUM 3
59 #define CPSW_SLAVE_PORTS_NUM 2
60 #define SLIVER_SIZE 0x40
61
62 #define CPSW1_HOST_PORT_OFFSET 0x028
63 #define CPSW1_SLAVE_OFFSET 0x050
64 #define CPSW1_SLAVE_SIZE 0x040
65 #define CPSW1_CPDMA_OFFSET 0x100
66 #define CPSW1_STATERAM_OFFSET 0x200
67 #define CPSW1_HW_STATS 0x400
68 #define CPSW1_CPTS_OFFSET 0x500
69 #define CPSW1_ALE_OFFSET 0x600
70 #define CPSW1_SLIVER_OFFSET 0x700
71 #define CPSW1_WR_OFFSET 0x900
72
73 #define CPSW2_HOST_PORT_OFFSET 0x108
74 #define CPSW2_SLAVE_OFFSET 0x200
75 #define CPSW2_SLAVE_SIZE 0x100
76 #define CPSW2_CPDMA_OFFSET 0x800
77 #define CPSW2_HW_STATS 0x900
78 #define CPSW2_STATERAM_OFFSET 0xa00
79 #define CPSW2_CPTS_OFFSET 0xc00
80 #define CPSW2_ALE_OFFSET 0xd00
81 #define CPSW2_SLIVER_OFFSET 0xd80
82 #define CPSW2_BD_OFFSET 0x2000
83 #define CPSW2_WR_OFFSET 0x1200
84
85 #define CPDMA_RXTHRESH 0x0c0
86 #define CPDMA_RXFREE 0x0e0
87 #define CPDMA_TXHDP 0x00
88 #define CPDMA_RXHDP 0x20
89 #define CPDMA_TXCP 0x40
90 #define CPDMA_RXCP 0x60
91
92 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
93 #define CPSW_MIN_PACKET_SIZE_VLAN (VLAN_ETH_ZLEN)
94 #define CPSW_MIN_PACKET_SIZE (ETH_ZLEN)
95 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
96 ETH_FCS_LEN +\
97 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
98
99 #define RX_PRIORITY_MAPPING 0x76543210
100 #define TX_PRIORITY_MAPPING 0x33221100
101 #define CPDMA_TX_PRIORITY_MAP 0x76543210
102
103 #define CPSW_VLAN_AWARE BIT(1)
104 #define CPSW_RX_VLAN_ENCAP BIT(2)
105 #define CPSW_ALE_VLAN_AWARE 1
106
107 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
108 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
109 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
110
111 #define CPSW_INTPACEEN (0x3f << 16)
112 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
113 #define CPSW_CMINTMAX_CNT 63
114 #define CPSW_CMINTMIN_CNT 2
115 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
116 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
117
118 #define IRQ_NUM 2
119 #define CPSW_MAX_QUEUES 8
120 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
121 #define CPSW_ALE_AGEOUT_DEFAULT 10 /* sec */
122 #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
123 #define CPSW_FIFO_SHAPE_EN_SHIFT 16
124 #define CPSW_FIFO_RATE_EN_SHIFT 20
125 #define CPSW_TC_NUM 4
126 #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
127 #define CPSW_PCT_MASK 0x7f
128 #define CPSW_BD_RAM_SIZE 0x2000
129
130 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
131 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
132 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
133 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
134 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
135 enum {
136 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
137 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
138 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
139 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
140 };
141
142 struct cpsw_wr_regs {
143 u32 id_ver;
144 u32 soft_reset;
145 u32 control;
146 u32 int_control;
147 u32 rx_thresh_en;
148 u32 rx_en;
149 u32 tx_en;
150 u32 misc_en;
151 u32 mem_allign1[8];
152 u32 rx_thresh_stat;
153 u32 rx_stat;
154 u32 tx_stat;
155 u32 misc_stat;
156 u32 mem_allign2[8];
157 u32 rx_imax;
158 u32 tx_imax;
159
160 };
161
162 struct cpsw_ss_regs {
163 u32 id_ver;
164 u32 control;
165 u32 soft_reset;
166 u32 stat_port_en;
167 u32 ptype;
168 u32 soft_idle;
169 u32 thru_rate;
170 u32 gap_thresh;
171 u32 tx_start_wds;
172 u32 flow_control;
173 u32 vlan_ltype;
174 u32 ts_ltype;
175 u32 dlr_ltype;
176 };
177
178 /* CPSW_PORT_V1 */
179 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
180 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
181 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
182 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
183 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
184 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
185 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
186 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
187
188 /* CPSW_PORT_V2 */
189 #define CPSW2_CONTROL 0x00 /* Control Register */
190 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
191 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
192 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
193 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
194 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
195 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
196
197 /* CPSW_PORT_V1 and V2 */
198 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
199 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
200 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
201
202 /* CPSW_PORT_V2 only */
203 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
204 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
205 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
206 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
207 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
208 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
209 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
210 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
211
212 /* Bit definitions for the CPSW2_CONTROL register */
213 #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */
214 #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */
215 #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */
216 #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */
217 #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */
218 #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */
219 #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */
220 #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */
221 #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */
222 #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */
223 #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */
224 #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */
225 #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */
226 #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */
227 #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */
228 #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */
229 #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */
230 #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */
231
232 #define CTRL_V2_TS_BITS \
233 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
234 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
235
236 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
237 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
238 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
239
240
241 #define CTRL_V3_TS_BITS \
242 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
243 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
244 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
245
246 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
247 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
248 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
249
250 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
251 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
252 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
253 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
254 #define TS_MSG_TYPE_EN_MASK (0xffff)
255
256 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
257 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
258
259 /* Bit definitions for the CPSW1_TS_CTL register */
260 #define CPSW_V1_TS_RX_EN BIT(0)
261 #define CPSW_V1_TS_TX_EN BIT(4)
262 #define CPSW_V1_MSG_TYPE_OFS 16
263
264 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
265 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
266
267 #define CPSW_MAX_BLKS_TX 15
268 #define CPSW_MAX_BLKS_TX_SHIFT 4
269 #define CPSW_MAX_BLKS_RX 5
270
271 struct cpsw_host_regs {
272 u32 max_blks;
273 u32 blk_cnt;
274 u32 tx_in_ctl;
275 u32 port_vlan;
276 u32 tx_pri_map;
277 u32 cpdma_tx_pri_map;
278 u32 cpdma_rx_chan_map;
279 };
280
281 struct cpsw_slave_data {
282 struct device_node *slave_node;
283 struct device_node *phy_node;
284 char phy_id[MII_BUS_ID_SIZE];
285 phy_interface_t phy_if;
286 u8 mac_addr[ETH_ALEN];
287 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
288 struct phy *ifphy;
289 bool disabled;
290 };
291
292 struct cpsw_platform_data {
293 struct cpsw_slave_data *slave_data;
294 u32 ss_reg_ofs; /* Subsystem control register offset */
295 u32 channels; /* number of cpdma channels (symmetric) */
296 u32 slaves; /* number of slave cpgmac ports */
297 u32 active_slave;/* time stamping, ethtool and SIOCGMIIPHY slave */
298 u32 bd_ram_size; /*buffer descriptor ram size */
299 u32 mac_control; /* Mac control register */
300 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
301 bool dual_emac; /* Enable Dual EMAC mode */
302 };
303
304 struct cpsw_slave {
305 void __iomem *regs;
306 int slave_num;
307 u32 mac_control;
308 struct cpsw_slave_data *data;
309 struct phy_device *phy;
310 struct net_device *ndev;
311 u32 port_vlan;
312 struct cpsw_sl *mac_sl;
313 };
314
slave_read(struct cpsw_slave * slave,u32 offset)315 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
316 {
317 return readl_relaxed(slave->regs + offset);
318 }
319
slave_write(struct cpsw_slave * slave,u32 val,u32 offset)320 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
321 {
322 writel_relaxed(val, slave->regs + offset);
323 }
324
325 struct cpsw_vector {
326 struct cpdma_chan *ch;
327 int budget;
328 };
329
330 struct cpsw_common {
331 struct device *dev;
332 struct cpsw_platform_data data;
333 struct napi_struct napi_rx;
334 struct napi_struct napi_tx;
335 struct cpsw_ss_regs __iomem *regs;
336 struct cpsw_wr_regs __iomem *wr_regs;
337 u8 __iomem *hw_stats;
338 struct cpsw_host_regs __iomem *host_port_regs;
339 u32 version;
340 u32 coal_intvl;
341 u32 bus_freq_mhz;
342 int rx_packet_max;
343 int descs_pool_size;
344 struct cpsw_slave *slaves;
345 struct cpdma_ctlr *dma;
346 struct cpsw_vector txv[CPSW_MAX_QUEUES];
347 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
348 struct cpsw_ale *ale;
349 bool quirk_irq;
350 bool rx_irq_disabled;
351 bool tx_irq_disabled;
352 u32 irqs_table[IRQ_NUM];
353 int misc_irq;
354 struct cpts *cpts;
355 struct devlink *devlink;
356 int rx_ch_num, tx_ch_num;
357 int speed;
358 int usage_count;
359 struct page_pool *page_pool[CPSW_MAX_QUEUES];
360 u8 br_members;
361 struct net_device *hw_bridge_dev;
362 bool ale_bypass;
363 u8 base_mac[ETH_ALEN];
364 };
365
366 struct cpsw_ale_ratelimit {
367 unsigned long cookie;
368 u64 rate_packet_ps;
369 };
370
371 struct cpsw_priv {
372 struct net_device *ndev;
373 struct device *dev;
374 u32 msg_enable;
375 u8 mac_addr[ETH_ALEN];
376 bool rx_pause;
377 bool tx_pause;
378 bool mqprio_hw;
379 int fifo_bw[CPSW_TC_NUM];
380 int shp_cfg_speed;
381 int tx_ts_enabled;
382 int rx_ts_enabled;
383 struct bpf_prog *xdp_prog;
384 struct xdp_rxq_info xdp_rxq[CPSW_MAX_QUEUES];
385 struct xdp_attachment_info xdpi;
386
387 u32 emac_port;
388 struct cpsw_common *cpsw;
389 int offload_fwd_mark;
390 u32 tx_packet_min;
391 struct cpsw_ale_ratelimit ale_bc_ratelimit;
392 struct cpsw_ale_ratelimit ale_mc_ratelimit;
393 };
394
395 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
396 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
397
398 extern int (*cpsw_slave_index)(struct cpsw_common *cpsw,
399 struct cpsw_priv *priv);
400
401 struct addr_sync_ctx {
402 struct net_device *ndev;
403 const u8 *addr; /* address to be synched */
404 int consumed; /* number of address instances */
405 int flush; /* flush flag */
406 };
407
408 #define CPSW_XMETA_OFFSET ALIGN(sizeof(struct xdp_frame), sizeof(long))
409
410 #define CPSW_XDP_CONSUMED 1
411 #define CPSW_XDP_PASS 0
412
__aligned(sizeof (long))413 struct __aligned(sizeof(long)) cpsw_meta_xdp {
414 struct net_device *ndev;
415 int ch;
416 };
417
418 /* The buf includes headroom compatible with both skb and xdpf */
419 #define CPSW_HEADROOM_NA (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + NET_IP_ALIGN)
420
cpsw_is_xdpf_handle(void * handle)421 static inline int cpsw_is_xdpf_handle(void *handle)
422 {
423 return (unsigned long)handle & BIT(0);
424 }
425
cpsw_xdpf_to_handle(struct xdp_frame * xdpf)426 static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf)
427 {
428 return (void *)((unsigned long)xdpf | BIT(0));
429 }
430
cpsw_handle_to_xdpf(void * handle)431 static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle)
432 {
433 return (struct xdp_frame *)((unsigned long)handle & ~BIT(0));
434 }
435
436 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
437 int ale_ageout, phys_addr_t desc_mem_phys,
438 int descs_pool_size);
439 void cpsw_split_res(struct cpsw_common *cpsw);
440 int cpsw_fill_rx_channels(struct cpsw_priv *priv);
441 void cpsw_intr_enable(struct cpsw_common *cpsw);
442 void cpsw_intr_disable(struct cpsw_common *cpsw);
443 void cpsw_tx_handler(void *token, int len, int status);
444 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw);
445 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw);
446 int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
447 int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf,
448 struct page *page, int port);
449 int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp,
450 struct page *page, int port, int *len);
451 irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id);
452 irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id);
453 irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id);
454 int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget);
455 int cpsw_tx_poll(struct napi_struct *napi_tx, int budget);
456 int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget);
457 int cpsw_rx_poll(struct napi_struct *napi_rx, int budget);
458 void cpsw_rx_vlan_encap(struct sk_buff *skb);
459 void soft_reset(const char *module, void __iomem *reg);
460 void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv);
461 void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
462 int cpsw_need_resplit(struct cpsw_common *cpsw);
463 int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
464 int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate);
465 int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
466 void *type_data);
467 bool cpsw_shp_is_off(struct cpsw_priv *priv);
468 void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
469 void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
470 void cpsw_qos_clsflower_resume(struct cpsw_priv *priv);
471
472 /* ethtool */
473 u32 cpsw_get_msglevel(struct net_device *ndev);
474 void cpsw_set_msglevel(struct net_device *ndev, u32 value);
475 int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
476 struct kernel_ethtool_coalesce *kernel_coal,
477 struct netlink_ext_ack *extack);
478 int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
479 struct kernel_ethtool_coalesce *kernel_coal,
480 struct netlink_ext_ack *extack);
481 int cpsw_get_sset_count(struct net_device *ndev, int sset);
482 void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
483 void cpsw_get_ethtool_stats(struct net_device *ndev,
484 struct ethtool_stats *stats, u64 *data);
485 void cpsw_get_pauseparam(struct net_device *ndev,
486 struct ethtool_pauseparam *pause);
487 void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
488 int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
489 int cpsw_get_regs_len(struct net_device *ndev);
490 void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
491 int cpsw_ethtool_op_begin(struct net_device *ndev);
492 void cpsw_ethtool_op_complete(struct net_device *ndev);
493 void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
494 int cpsw_get_link_ksettings(struct net_device *ndev,
495 struct ethtool_link_ksettings *ecmd);
496 int cpsw_set_link_ksettings(struct net_device *ndev,
497 const struct ethtool_link_ksettings *ecmd);
498 int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata);
499 int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata);
500 int cpsw_nway_reset(struct net_device *ndev);
501 void cpsw_get_ringparam(struct net_device *ndev,
502 struct ethtool_ringparam *ering,
503 struct kernel_ethtool_ringparam *kernel_ering,
504 struct netlink_ext_ack *extack);
505 int cpsw_set_ringparam(struct net_device *ndev,
506 struct ethtool_ringparam *ering,
507 struct kernel_ethtool_ringparam *kernel_ering,
508 struct netlink_ext_ack *extack);
509 int cpsw_set_channels_common(struct net_device *ndev,
510 struct ethtool_channels *chs,
511 cpdma_handler_fn rx_handler);
512 int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info);
513
514 #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
515