1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCN32_CLK_MGR_SMU_MSG_H_ 27 #define __DCN32_CLK_MGR_SMU_MSG_H_ 28 29 #include "core_types.h" 30 #include "dcn30/dcn30_clk_mgr_smu_msg.h" 31 32 #define FCLK_PSTATE_NOTSUPPORTED 0x00 33 #define FCLK_PSTATE_SUPPORTED 0x01 34 35 /* TODO Remove this MSG ID define after it becomes available in dalsmc */ 36 #define DALSMC_MSG_SetCabForUclkPstate 0x12 37 #define DALSMC_Result_OK 0x1 38 39 void 40 dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); 41 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 42 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); 43 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); 44 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 45 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); 46 47 #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */ 48