1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* Linux PRO/1000 Ethernet Driver main header file */
5
6 #ifndef _E1000_H_
7 #define _E1000_H_
8
9 #include <linux/bitops.h>
10 #include <linux/types.h>
11 #include <linux/timer.h>
12 #include <linux/workqueue.h>
13 #include <linux/io.h>
14 #include <linux/netdevice.h>
15 #include <linux/pci.h>
16 #include <linux/crc32.h>
17 #include <linux/if_vlan.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/ptp_classify.h>
22 #include <linux/mii.h>
23 #include <linux/mdio.h>
24 #include <linux/mutex.h>
25 #include <linux/pm_qos.h>
26 #include "hw.h"
27
28 struct e1000_info;
29
30 #define e_dbg(format, arg...) \
31 netdev_dbg(hw->adapter->netdev, format, ## arg)
32 #define e_err(format, arg...) \
33 netdev_err(adapter->netdev, format, ## arg)
34 #define e_info(format, arg...) \
35 netdev_info(adapter->netdev, format, ## arg)
36 #define e_warn(format, arg...) \
37 netdev_warn(adapter->netdev, format, ## arg)
38 #define e_notice(format, arg...) \
39 netdev_notice(adapter->netdev, format, ## arg)
40
41 /* Interrupt modes, as used by the IntMode parameter */
42 #define E1000E_INT_MODE_LEGACY 0
43 #define E1000E_INT_MODE_MSI 1
44 #define E1000E_INT_MODE_MSIX 2
45
46 /* Tx/Rx descriptor defines */
47 #define E1000_DEFAULT_TXD 256
48 #define E1000_MAX_TXD 4096
49 #define E1000_MIN_TXD 64
50
51 #define E1000_DEFAULT_RXD 256
52 #define E1000_MAX_RXD 4096
53 #define E1000_MIN_RXD 64
54
55 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
56 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
57
58 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
59
60 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
61 /* How many Rx Buffers do we bundle into one write to the hardware ? */
62 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
63
64 #define AUTO_ALL_MODES 0
65 #define E1000_EEPROM_APME 0x0400
66
67 #define E1000_MNG_VLAN_NONE (-1)
68
69 #define DEFAULT_JUMBO 9234
70
71 /* Time to wait before putting the device into D3 if there's no link (in ms). */
72 #define LINK_TIMEOUT 100
73
74 /* Count for polling __E1000_RESET condition every 10-20msec.
75 * Experimentation has shown the reset can take approximately 210msec.
76 */
77 #define E1000_CHECK_RESET_COUNT 25
78
79 #define PCICFG_DESC_RING_STATUS 0xe4
80 #define FLUSH_DESC_REQUIRED 0x100
81
82 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
83 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
84 * WTHRESH=4, so a setting of 5 gives the most efficient bus
85 * utilization but to avoid possible Tx stalls, set it to 1
86 */
87 #define E1000_TXDCTL_DMA_BURST_ENABLE \
88 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
89 E1000_TXDCTL_COUNT_DESC | \
90 (1u << 16) | /* wthresh must be +1 more than desired */\
91 (1u << 8) | /* hthresh */ \
92 0x1f) /* pthresh */
93
94 #define E1000_RXDCTL_DMA_BURST_ENABLE \
95 (0x01000000 | /* set descriptor granularity */ \
96 (4u << 16) | /* set writeback threshold */ \
97 (4u << 8) | /* set prefetch threshold */ \
98 0x20) /* set hthresh */
99
100 #define E1000_TIDV_FPD BIT(31)
101 #define E1000_RDTR_FPD BIT(31)
102
103 enum e1000_boards {
104 board_82571,
105 board_82572,
106 board_82573,
107 board_82574,
108 board_82583,
109 board_80003es2lan,
110 board_ich8lan,
111 board_ich9lan,
112 board_ich10lan,
113 board_pchlan,
114 board_pch2lan,
115 board_pch_lpt,
116 board_pch_spt,
117 board_pch_cnp,
118 board_pch_tgp,
119 board_pch_adp
120 };
121
122 struct e1000_ps_page {
123 struct page *page;
124 u64 dma; /* must be u64 - written to hw */
125 };
126
127 /* wrappers around a pointer to a socket buffer,
128 * so a DMA handle can be stored along with the buffer
129 */
130 struct e1000_buffer {
131 dma_addr_t dma;
132 struct sk_buff *skb;
133 union {
134 /* Tx */
135 struct {
136 unsigned long time_stamp;
137 u16 length;
138 u16 next_to_watch;
139 unsigned int segs;
140 unsigned int bytecount;
141 u16 mapped_as_page;
142 };
143 /* Rx */
144 struct {
145 /* arrays of page information for packet split */
146 struct e1000_ps_page *ps_pages;
147 struct page *page;
148 };
149 };
150 };
151
152 struct e1000_ring {
153 struct e1000_adapter *adapter; /* back pointer to adapter */
154 void *desc; /* pointer to ring memory */
155 dma_addr_t dma; /* phys address of ring */
156 unsigned int size; /* length of ring in bytes */
157 unsigned int count; /* number of desc. in ring */
158
159 u16 next_to_use;
160 u16 next_to_clean;
161
162 void __iomem *head;
163 void __iomem *tail;
164
165 /* array of buffer information structs */
166 struct e1000_buffer *buffer_info;
167
168 char name[IFNAMSIZ + 5];
169 u32 ims_val;
170 u32 itr_val;
171 void __iomem *itr_register;
172 int set_itr;
173
174 struct sk_buff *rx_skb_top;
175 };
176
177 /* PHY register snapshot values */
178 struct e1000_phy_regs {
179 u16 bmcr; /* basic mode control register */
180 u16 bmsr; /* basic mode status register */
181 u16 advertise; /* auto-negotiation advertisement */
182 u16 lpa; /* link partner ability register */
183 u16 expansion; /* auto-negotiation expansion reg */
184 u16 ctrl1000; /* 1000BASE-T control register */
185 u16 stat1000; /* 1000BASE-T status register */
186 u16 estatus; /* extended status register */
187 };
188
189 /* board specific private data structure */
190 struct e1000_adapter {
191 struct timer_list watchdog_timer;
192 struct timer_list phy_info_timer;
193 struct timer_list blink_timer;
194
195 struct work_struct reset_task;
196 struct work_struct watchdog_task;
197
198 const struct e1000_info *ei;
199
200 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
201 u32 bd_number;
202 u32 rx_buffer_len;
203 u16 mng_vlan_id;
204 u16 link_speed;
205 u16 link_duplex;
206 u16 eeprom_vers;
207
208 /* track device up/down/testing state */
209 unsigned long state;
210
211 /* Interrupt Throttle Rate */
212 u32 itr;
213 u32 itr_setting;
214 u16 tx_itr;
215 u16 rx_itr;
216
217 /* Tx - one ring per active queue */
218 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
219 u32 tx_fifo_limit;
220
221 struct napi_struct napi;
222
223 unsigned int uncorr_errors; /* uncorrectable ECC errors */
224 unsigned int corr_errors; /* correctable ECC errors */
225 unsigned int restart_queue;
226 u32 txd_cmd;
227
228 bool detect_tx_hung;
229 bool tx_hang_recheck;
230 u8 tx_timeout_factor;
231
232 u32 tx_int_delay;
233 u32 tx_abs_int_delay;
234
235 unsigned int total_tx_bytes;
236 unsigned int total_tx_packets;
237 unsigned int total_rx_bytes;
238 unsigned int total_rx_packets;
239
240 /* Tx stats */
241 u64 tpt_old;
242 u64 colc_old;
243 u32 gotc;
244 u64 gotc_old;
245 u32 tx_timeout_count;
246 u32 tx_fifo_head;
247 u32 tx_head_addr;
248 u32 tx_fifo_size;
249 u32 tx_dma_failed;
250 u32 tx_hwtstamp_timeouts;
251 u32 tx_hwtstamp_skipped;
252
253 /* Rx */
254 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
255 int work_to_do) ____cacheline_aligned_in_smp;
256 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
257 gfp_t gfp);
258 struct e1000_ring *rx_ring;
259
260 u32 rx_int_delay;
261 u32 rx_abs_int_delay;
262
263 /* Rx stats */
264 u64 hw_csum_err;
265 u64 hw_csum_good;
266 u64 rx_hdr_split;
267 u32 gorc;
268 u64 gorc_old;
269 u32 alloc_rx_buff_failed;
270 u32 rx_dma_failed;
271 u32 rx_hwtstamp_cleared;
272
273 unsigned int rx_ps_pages;
274 u16 rx_ps_bsize0;
275 u32 max_frame_size;
276 u32 min_frame_size;
277
278 /* OS defined structs */
279 struct net_device *netdev;
280 struct pci_dev *pdev;
281
282 /* structs defined in e1000_hw.h */
283 struct e1000_hw hw;
284
285 spinlock_t stats64_lock; /* protects statistics counters */
286 struct e1000_hw_stats stats;
287 struct e1000_phy_info phy_info;
288 struct e1000_phy_stats phy_stats;
289
290 /* Snapshot of PHY registers */
291 struct e1000_phy_regs phy_regs;
292
293 struct e1000_ring test_tx_ring;
294 struct e1000_ring test_rx_ring;
295 u32 test_icr;
296
297 u32 msg_enable;
298 unsigned int num_vectors;
299 struct msix_entry *msix_entries;
300 int int_mode;
301 u32 eiac_mask;
302
303 u32 eeprom_wol;
304 u32 wol;
305 u32 pba;
306 u32 max_hw_frame_size;
307
308 bool fc_autoneg;
309
310 unsigned int flags;
311 unsigned int flags2;
312 struct work_struct downshift_task;
313 struct work_struct update_phy_task;
314 struct work_struct print_hang_task;
315
316 int phy_hang_count;
317
318 u16 tx_ring_count;
319 u16 rx_ring_count;
320
321 struct hwtstamp_config hwtstamp_config;
322 struct delayed_work systim_overflow_work;
323 struct sk_buff *tx_hwtstamp_skb;
324 unsigned long tx_hwtstamp_start;
325 struct work_struct tx_hwtstamp_work;
326 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
327 struct cyclecounter cc;
328 struct timecounter tc;
329 struct ptp_clock *ptp_clock;
330 struct ptp_clock_info ptp_clock_info;
331 struct pm_qos_request pm_qos_req;
332 long ptp_delta;
333
334 u16 eee_advert;
335 };
336
337 struct e1000_info {
338 enum e1000_mac_type mac;
339 unsigned int flags;
340 unsigned int flags2;
341 u32 pba;
342 u32 max_hw_frame_size;
343 s32 (*get_variants)(struct e1000_adapter *);
344 const struct e1000_mac_operations *mac_ops;
345 const struct e1000_phy_operations *phy_ops;
346 const struct e1000_nvm_operations *nvm_ops;
347 };
348
349 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
350
351 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
352 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
353 * its resolution) is based on the contents of the TIMINCA register - it
354 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
355 * For the best accuracy, the incperiod should be as small as possible. The
356 * incvalue is scaled by a factor as large as possible (while still fitting
357 * in bits 23:0) so that relatively small clock corrections can be made.
358 *
359 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
360 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
361 * bits to count nanoseconds leaving the rest for fractional nonseconds.
362 */
363 #define INCVALUE_96MHZ 125
364 #define INCVALUE_SHIFT_96MHZ 17
365 #define INCPERIOD_SHIFT_96MHZ 2
366 #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ)
367
368 #define INCVALUE_25MHZ 40
369 #define INCVALUE_SHIFT_25MHZ 18
370 #define INCPERIOD_25MHZ 1
371
372 #define INCVALUE_24MHZ 125
373 #define INCVALUE_SHIFT_24MHZ 14
374 #define INCPERIOD_24MHZ 3
375
376 #define INCVALUE_38400KHZ 26
377 #define INCVALUE_SHIFT_38400KHZ 19
378 #define INCPERIOD_38400KHZ 1
379
380 /* Another drawback of scaling the incvalue by a large factor is the
381 * 64-bit SYSTIM register overflows more quickly. This is dealt with
382 * by simply reading the clock before it overflows.
383 *
384 * Clock ns bits Overflows after
385 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
386 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
387 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
388 */
389 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
390 #define E1000_MAX_82574_SYSTIM_REREADS 50
391 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
392
393 /* hardware capability, feature, and workaround flags */
394 #define FLAG_HAS_AMT BIT(0)
395 #define FLAG_HAS_FLASH BIT(1)
396 #define FLAG_HAS_HW_VLAN_FILTER BIT(2)
397 #define FLAG_HAS_WOL BIT(3)
398 /* reserved BIT(4) */
399 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
400 #define FLAG_HAS_SWSM_ON_LOAD BIT(6)
401 #define FLAG_HAS_JUMBO_FRAMES BIT(7)
402 #define FLAG_READ_ONLY_NVM BIT(8)
403 #define FLAG_IS_ICH BIT(9)
404 #define FLAG_HAS_MSIX BIT(10)
405 #define FLAG_HAS_SMART_POWER_DOWN BIT(11)
406 #define FLAG_IS_QUAD_PORT_A BIT(12)
407 #define FLAG_IS_QUAD_PORT BIT(13)
408 #define FLAG_HAS_HW_TIMESTAMP BIT(14)
409 #define FLAG_APME_IN_WUC BIT(15)
410 #define FLAG_APME_IN_CTRL3 BIT(16)
411 #define FLAG_APME_CHECK_PORT_B BIT(17)
412 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
413 #define FLAG_NO_WAKE_UCAST BIT(19)
414 #define FLAG_MNG_PT_ENABLED BIT(20)
415 #define FLAG_RESET_OVERWRITES_LAA BIT(21)
416 #define FLAG_TARC_SPEED_MODE_BIT BIT(22)
417 #define FLAG_TARC_SET_BIT_ZERO BIT(23)
418 #define FLAG_RX_NEEDS_RESTART BIT(24)
419 #define FLAG_LSC_GIG_SPEED_DROP BIT(25)
420 #define FLAG_SMART_POWER_DOWN BIT(26)
421 #define FLAG_MSI_ENABLED BIT(27)
422 /* reserved BIT(28) */
423 #define FLAG_TSO_FORCE BIT(29)
424 #define FLAG_RESTART_NOW BIT(30)
425 #define FLAG_MSI_TEST_FAILED BIT(31)
426
427 #define FLAG2_CRC_STRIPPING BIT(0)
428 #define FLAG2_HAS_PHY_WAKEUP BIT(1)
429 #define FLAG2_IS_DISCARDING BIT(2)
430 #define FLAG2_DISABLE_ASPM_L1 BIT(3)
431 #define FLAG2_HAS_PHY_STATS BIT(4)
432 #define FLAG2_HAS_EEE BIT(5)
433 #define FLAG2_DMA_BURST BIT(6)
434 #define FLAG2_DISABLE_ASPM_L0S BIT(7)
435 #define FLAG2_DISABLE_AIM BIT(8)
436 #define FLAG2_CHECK_PHY_HANG BIT(9)
437 #define FLAG2_NO_DISABLE_RX BIT(10)
438 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
439 #define FLAG2_DFLT_CRC_STRIPPING BIT(12)
440 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
441 #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)
442 #define FLAG2_ENABLE_S0IX_FLOWS BIT(15)
443
444 #define E1000_RX_DESC_PS(R, i) \
445 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
446 #define E1000_RX_DESC_EXT(R, i) \
447 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
448 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
449 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
450 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
451
452 enum e1000_state_t {
453 __E1000_TESTING,
454 __E1000_RESETTING,
455 __E1000_ACCESS_SHARED_RESOURCE,
456 __E1000_DOWN
457 };
458
459 enum latency_range {
460 lowest_latency = 0,
461 low_latency = 1,
462 bulk_latency = 2,
463 latency_invalid = 255
464 };
465
466 extern char e1000e_driver_name[];
467
468 void e1000e_check_options(struct e1000_adapter *adapter);
469 void e1000e_set_ethtool_ops(struct net_device *netdev);
470
471 int e1000e_open(struct net_device *netdev);
472 int e1000e_close(struct net_device *netdev);
473 void e1000e_up(struct e1000_adapter *adapter);
474 void e1000e_down(struct e1000_adapter *adapter, bool reset);
475 void e1000e_reinit_locked(struct e1000_adapter *adapter);
476 void e1000e_reset(struct e1000_adapter *adapter);
477 void e1000e_power_up_phy(struct e1000_adapter *adapter);
478 int e1000e_setup_rx_resources(struct e1000_ring *ring);
479 int e1000e_setup_tx_resources(struct e1000_ring *ring);
480 void e1000e_free_rx_resources(struct e1000_ring *ring);
481 void e1000e_free_tx_resources(struct e1000_ring *ring);
482 void e1000e_get_stats64(struct net_device *netdev,
483 struct rtnl_link_stats64 *stats);
484 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
485 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
486 void e1000e_get_hw_control(struct e1000_adapter *adapter);
487 void e1000e_release_hw_control(struct e1000_adapter *adapter);
488 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
489
490 extern unsigned int copybreak;
491
492 extern const struct e1000_info e1000_82571_info;
493 extern const struct e1000_info e1000_82572_info;
494 extern const struct e1000_info e1000_82573_info;
495 extern const struct e1000_info e1000_82574_info;
496 extern const struct e1000_info e1000_82583_info;
497 extern const struct e1000_info e1000_ich8_info;
498 extern const struct e1000_info e1000_ich9_info;
499 extern const struct e1000_info e1000_ich10_info;
500 extern const struct e1000_info e1000_pch_info;
501 extern const struct e1000_info e1000_pch2_info;
502 extern const struct e1000_info e1000_pch_lpt_info;
503 extern const struct e1000_info e1000_pch_spt_info;
504 extern const struct e1000_info e1000_pch_cnp_info;
505 extern const struct e1000_info e1000_pch_tgp_info;
506 extern const struct e1000_info e1000_pch_adp_info;
507 extern const struct e1000_info e1000_es2_info;
508
509 void e1000e_ptp_init(struct e1000_adapter *adapter);
510 void e1000e_ptp_remove(struct e1000_adapter *adapter);
511
512 u64 e1000e_read_systim(struct e1000_adapter *adapter,
513 struct ptp_system_timestamp *sts);
514
e1000_phy_hw_reset(struct e1000_hw * hw)515 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
516 {
517 return hw->phy.ops.reset(hw);
518 }
519
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)520 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
521 {
522 return hw->phy.ops.read_reg(hw, offset, data);
523 }
524
e1e_rphy_locked(struct e1000_hw * hw,u32 offset,u16 * data)525 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
526 {
527 return hw->phy.ops.read_reg_locked(hw, offset, data);
528 }
529
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)530 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
531 {
532 return hw->phy.ops.write_reg(hw, offset, data);
533 }
534
e1e_wphy_locked(struct e1000_hw * hw,u32 offset,u16 data)535 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
536 {
537 return hw->phy.ops.write_reg_locked(hw, offset, data);
538 }
539
540 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
541
e1000e_read_mac_addr(struct e1000_hw * hw)542 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
543 {
544 if (hw->mac.ops.read_mac_addr)
545 return hw->mac.ops.read_mac_addr(hw);
546
547 return e1000_read_mac_addr_generic(hw);
548 }
549
e1000_validate_nvm_checksum(struct e1000_hw * hw)550 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
551 {
552 return hw->nvm.ops.validate(hw);
553 }
554
e1000e_update_nvm_checksum(struct e1000_hw * hw)555 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
556 {
557 return hw->nvm.ops.update(hw);
558 }
559
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)560 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
561 u16 *data)
562 {
563 return hw->nvm.ops.read(hw, offset, words, data);
564 }
565
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)566 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
567 u16 *data)
568 {
569 return hw->nvm.ops.write(hw, offset, words, data);
570 }
571
e1000_get_phy_info(struct e1000_hw * hw)572 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
573 {
574 return hw->phy.ops.get_info(hw);
575 }
576
__er32(struct e1000_hw * hw,unsigned long reg)577 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
578 {
579 return readl(hw->hw_addr + reg);
580 }
581
582 #define er32(reg) __er32(hw, E1000_##reg)
583
584 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
585
586 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
587
588 #define e1e_flush() er32(STATUS)
589
590 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
591 (__ew32((a), (reg + ((offset) << 2)), (value)))
592
593 #define E1000_READ_REG_ARRAY(a, reg, offset) \
594 (readl((a)->hw_addr + reg + ((offset) << 2)))
595
596 #endif /* _E1000_H_ */
597