1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 #include "core.h" 6 7 #ifndef ATH11K_HAL_DESC_H 8 #define ATH11K_HAL_DESC_H 9 10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 11 12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 15 16 struct ath11k_buffer_addr { 17 u32 info0; 18 u32 info1; 19 } __packed; 20 21 /* ath11k_buffer_addr 22 * 23 * info0 24 * Address (lower 32 bits) of the msdu buffer or msdu extension 25 * descriptor or Link descriptor 26 * 27 * addr 28 * Address (upper 8 bits) of the msdu buffer or msdu extension 29 * descriptor or Link descriptor 30 * 31 * return_buffer_manager (RBM) 32 * Consumer: WBM 33 * Producer: SW/FW 34 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 35 * descriptor or link descriptor that is being pointed to shall be 36 * returned after the frame has been processed. It is used by WBM 37 * for routing purposes. 38 * 39 * Values are defined in enum %HAL_RX_BUF_RBM_ 40 * 41 * sw_buffer_cookie 42 * Cookie field exclusively used by SW. HW ignores the contents, 43 * accept that it passes the programmed value on to other 44 * descriptors together with the physical address. 45 * 46 * Field can be used by SW to for example associate the buffers 47 * physical address with the virtual address. 48 */ 49 50 enum hal_tlv_tag { 51 HAL_MACTX_CBF_START = 0 /* 0x0 */, 52 HAL_PHYRX_DATA = 1 /* 0x1 */, 53 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 54 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 55 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 56 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 57 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 58 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 59 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 60 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 61 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 62 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 63 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 64 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 65 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 66 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 67 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 68 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 69 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 70 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 71 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 72 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 73 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 74 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 75 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 76 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 77 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 78 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 79 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 80 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 81 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 82 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 83 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 84 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 85 HAL_MACTX_PKT_END = 34 /* 0x22 */, 86 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 87 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 88 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 89 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 90 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 91 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 92 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 93 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 94 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 95 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 96 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 97 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 98 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 99 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 100 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 101 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 102 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 103 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 104 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 105 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 106 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 107 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 108 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 109 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 110 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 111 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 112 HAL_MACTX_SERVICE = 61 /* 0x3d */, 113 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 114 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 115 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 116 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 117 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 118 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 119 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 120 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 121 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 122 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 123 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 124 HAL_MACTX_DEBUG = 73 /* 0x49 */, 125 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 126 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 127 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 128 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 129 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 130 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 131 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 132 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 133 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 134 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 135 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 136 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 137 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 138 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 139 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 140 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 141 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 142 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 143 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 144 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 145 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 146 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 147 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 148 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 149 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 150 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 151 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 152 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 153 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 154 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 155 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 156 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 157 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 158 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 159 HAL_COEX_TX_REQ = 108 /* 0x6c */, 160 HAL_DUMMY = 109 /* 0x6d */, 161 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 162 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 163 HAL_MPDU_LIMIT = 112 /* 0x70 */, 164 HAL_NA_LENGTH_END = 113 /* 0x71 */, 165 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 166 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 167 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 168 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 169 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 170 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 171 HAL_PDG_RESPONSE = 120 /* 0x78 */, 172 HAL_PDG_TX_REQ = 121 /* 0x79 */, 173 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 174 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 175 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 176 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 177 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 178 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 179 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 180 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 181 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 182 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 183 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 184 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 185 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 186 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 187 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 188 HAL_TX_DATA = 137 /* 0x89 */, 189 HAL_TX_FES_SETUP = 138 /* 0x8a */, 190 HAL_RX_PACKET = 139 /* 0x8b */, 191 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 192 HAL_TX_MPDU_END = 141 /* 0x8d */, 193 HAL_TX_MPDU_START = 142 /* 0x8e */, 194 HAL_TX_MSDU_END = 143 /* 0x8f */, 195 HAL_TX_MSDU_START = 144 /* 0x90 */, 196 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 197 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 198 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 199 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 200 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 201 HAL_MPDU_INFO = 150 /* 0x96 */, 202 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 203 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 204 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 205 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 206 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 207 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 208 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 209 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 210 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 211 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 212 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 213 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 214 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 215 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 216 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 217 HAL_TX_FLUSH = 166 /* 0xa6 */, 218 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 219 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 220 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 221 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 222 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 223 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 224 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 225 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 226 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 227 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 228 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 229 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 230 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 231 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 232 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 233 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 234 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 235 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 236 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 237 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 238 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 239 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 240 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 241 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 242 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 243 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 244 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 245 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 246 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 247 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 248 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 249 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 250 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 251 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 252 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 253 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 254 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 255 HAL_RX_START_PARAM = 204 /* 0xcc */, 256 HAL_RX_PPDU_START = 205 /* 0xcd */, 257 HAL_RX_PPDU_END = 206 /* 0xce */, 258 HAL_RX_MPDU_START = 207 /* 0xcf */, 259 HAL_RX_MPDU_END = 208 /* 0xd0 */, 260 HAL_RX_MSDU_START = 209 /* 0xd1 */, 261 HAL_RX_MSDU_END = 210 /* 0xd2 */, 262 HAL_RX_ATTENTION = 211 /* 0xd3 */, 263 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 264 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 265 HAL_RX_HEADER = 214 /* 0xd6 */, 266 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 267 HAL_RX_FLUSH = 216 /* 0xd8 */, 268 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 269 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 270 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 271 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 272 HAL_TX_CBF_INFO = 221 /* 0xdd */, 273 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 274 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 275 HAL_RX_PM_INFO = 224 /* 0xe0 */, 276 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 277 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 278 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 279 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 280 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 281 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 282 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 283 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 284 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 285 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 286 HAL_COEX_TX_RESP = 235 /* 0xeb */, 287 HAL_COEX_TX_STATUS = 236 /* 0xec */, 288 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 289 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 290 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 291 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 292 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 293 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 294 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 295 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 296 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 297 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 298 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 299 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 300 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 301 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 302 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 303 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 304 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 305 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 306 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 307 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 308 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 309 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 310 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 311 HAL_WHO_COMMIT = 260 /* 0x104 */, 312 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 313 HAL_WHO_FLUSH = 262 /* 0x106 */, 314 HAL_WHO_L2_LLC = 263 /* 0x107 */, 315 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 316 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 317 HAL_WHO_L3_INFO = 266 /* 0x10a */, 318 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 319 HAL_WHO_L4_INFO = 268 /* 0x10c */, 320 HAL_WHO_MSDU = 269 /* 0x10d */, 321 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 322 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 323 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 324 HAL_WHO_PPDU_END = 273 /* 0x111 */, 325 HAL_WHO_PPDU_START = 274 /* 0x112 */, 326 HAL_WHO_TSO = 275 /* 0x113 */, 327 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 328 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 329 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 330 HAL_MPDU_INFO_END = 279 /* 0x117 */, 331 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 332 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 333 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 334 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 335 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 336 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 337 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 338 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 339 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 340 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 341 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 342 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 343 HAL_WHO_TERMINATE = 292 /* 0x124 */, 344 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 345 HAL_TX_CV_DATA = 294 /* 0x126 */, 346 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 347 HAL_PPDU_TX_END = 296 /* 0x128 */, 348 HAL_PROT_TX_END = 297 /* 0x129 */, 349 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 350 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 351 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 352 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 353 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 354 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 355 HAL_ACK_REPORT = 304 /* 0x130 */, 356 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 357 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 358 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 359 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 360 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 361 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 362 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 363 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 364 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 365 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 366 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 367 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 368 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 369 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 370 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 371 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 372 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 373 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 374 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 375 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 376 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 377 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 378 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 379 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 380 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 381 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 382 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 383 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 384 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 385 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 386 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 387 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 388 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 389 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 390 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 391 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 392 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 393 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 394 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 395 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 396 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 397 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 398 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 399 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 400 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 401 HAL_RX_RING_MASK = 350 /* 0x15e */, 402 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 403 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 404 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 405 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 406 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 407 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 408 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 409 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 410 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 411 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 412 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 413 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 414 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 415 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 416 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 417 HAL_HT_SIG_INFO = 366 /* 0x16e */, 418 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 419 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 420 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 421 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 422 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 423 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 424 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 425 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 426 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 427 HAL_SERVICE_INFO = 376 /* 0x178 */, 428 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 429 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 430 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 431 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 432 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 433 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 434 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 435 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 436 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 437 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 438 HAL_SCHEDULER_END = 387 /* 0x183 */, 439 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 440 HAL_SW_PEER_INFO = 389 /* 0x185 */, 441 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 442 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 443 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 444 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 445 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 446 HAL_CCE_RULE = 395 /* 0x18b */, 447 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 448 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 449 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 450 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 451 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 452 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 453 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 454 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 455 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 456 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 457 HAL_CE_SRC_DESC = 406 /* 0x196 */, 458 HAL_CE_STAT_DESC = 407 /* 0x197 */, 459 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 460 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 461 HAL_CMD_PART_0_END = 410 /* 0x19a */, 462 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 463 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 464 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 465 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 466 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 467 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 468 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 469 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 470 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 471 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 472 HAL_TLV_BASE = 511 /* 0x1ff */, 473 }; 474 475 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 476 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 477 #define HAL_TLV_USR_ID GENMASK(31, 26) 478 479 #define HAL_TLV_ALIGN 4 480 481 struct hal_tlv_hdr { 482 u32 tl; 483 u8 value[]; 484 } __packed; 485 486 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 487 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8) 488 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20) 489 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21) 490 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22) 491 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23) 492 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24) 493 #define RX_MPDU_DESC_INFO0_VALID_SA BIT(25) 494 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(26) 495 #define RX_MPDU_DESC_INFO0_VALID_DA BIT(27) 496 #define RX_MPDU_DESC_INFO0_DA_MCBC BIT(28) 497 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(29) 498 #define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(30) 499 500 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0) 501 502 struct rx_mpdu_desc { 503 u32 info0; /* %RX_MPDU_DESC_INFO */ 504 u32 meta_data; 505 } __packed; 506 507 /* rx_mpdu_desc 508 * Producer: RXDMA 509 * Consumer: REO/SW/FW 510 * 511 * msdu_count 512 * The number of MSDUs within the MPDU 513 * 514 * mpdu_sequence_number 515 * The field can have two different meanings based on the setting 516 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 517 * start sequence number from the BAR frame otherwise it means 518 * the MPDU sequence number of the received frame. 519 * 520 * fragment_flag 521 * When set, this MPDU is a fragment and REO should forward this 522 * fragment MPDU to the REO destination ring without any reorder 523 * checks, pn checks or bitmap update. This implies that REO is 524 * forwarding the pointer to the MSDU link descriptor. 525 * 526 * mpdu_retry_bit 527 * The retry bit setting from the MPDU header of the received frame 528 * 529 * ampdu_flag 530 * Indicates the MPDU was received as part of an A-MPDU. 531 * 532 * bar_frame 533 * Indicates the received frame is a BAR frame. After processing, 534 * this frame shall be pushed to SW or deleted. 535 * 536 * valid_pn 537 * When not set, REO will not perform a PN sequence number check. 538 * 539 * valid_sa 540 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 541 * 542 * sa_idx_timeout 543 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 544 * MAC source address search due to the expiration of search timer. 545 * 546 * valid_da 547 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 548 * 549 * da_mcbc 550 * Field Only valid if valid_da is set. Indicates at least one of 551 * the DA addresses is a Multicast or Broadcast address. 552 * 553 * da_idx_timeout 554 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 555 * MAC destination address search due to the expiration of search 556 * timer. 557 * 558 * raw_mpdu 559 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 560 * the contents in the MSDU buffer contains a 'RAW' MPDU. 561 */ 562 563 enum hal_rx_msdu_desc_reo_dest_ind { 564 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 565 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 566 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 567 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 568 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 569 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 570 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 571 }; 572 573 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 574 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 575 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 576 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 577 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 578 #define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(22) 579 #define RX_MSDU_DESC_INFO0_VALID_SA BIT(23) 580 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(24) 581 #define RX_MSDU_DESC_INFO0_VALID_DA BIT(25) 582 #define RX_MSDU_DESC_INFO0_DA_MCBC BIT(26) 583 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(27) 584 585 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 586 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 587 588 struct rx_msdu_desc { 589 u32 info0; 590 u32 rsvd0; 591 } __packed; 592 593 /* rx_msdu_desc 594 * 595 * first_msdu_in_mpdu 596 * Indicates first msdu in mpdu. 597 * 598 * last_msdu_in_mpdu 599 * Indicates last msdu in mpdu. This flag can be true only when 600 * 'Msdu_continuation' set to 0. This implies that when an msdu 601 * is spread out over multiple buffers and thus msdu_continuation 602 * is set, only for the very last buffer of the msdu, can the 603 * 'last_msdu_in_mpdu' be set. 604 * 605 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 606 * the MPDU that this MSDU belongs to only contains a single MSDU. 607 * 608 * msdu_continuation 609 * When set, this MSDU buffer was not able to hold the entire MSDU. 610 * The next buffer will therefore contain additional information 611 * related to this MSDU. 612 * 613 * msdu_length 614 * Field is only valid in combination with the 'first_msdu_in_mpdu' 615 * being set. Full MSDU length in bytes after decapsulation. This 616 * field is still valid for MPDU frames without A-MSDU. It still 617 * represents MSDU length after decapsulation Or in case of RAW 618 * MPDUs, it indicates the length of the entire MPDU (without FCS 619 * field). 620 * 621 * reo_destination_indication 622 * The id of the reo exit ring where the msdu frame shall push 623 * after (MPDU level) reordering has finished. Values are defined 624 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 625 * 626 * msdu_drop 627 * Indicates that REO shall drop this MSDU and not forward it to 628 * any other ring. 629 * 630 * valid_sa 631 * Indicates OLE found a valid SA entry for this MSDU. 632 * 633 * sa_idx_timeout 634 * Indicates, an unsuccessful MAC source address search due to 635 * the expiration of search timer for this MSDU. 636 * 637 * valid_da 638 * When set, OLE found a valid DA entry for this MSDU. 639 * 640 * da_mcbc 641 * Field Only valid if valid_da is set. Indicates the DA address 642 * is a Multicast or Broadcast address for this MSDU. 643 * 644 * da_idx_timeout 645 * Indicates, an unsuccessful MAC destination address search due 646 * to the expiration of search timer for this MSDU. 647 */ 648 649 enum hal_reo_dest_ring_buffer_type { 650 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 651 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 652 }; 653 654 enum hal_reo_dest_ring_push_reason { 655 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 656 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 657 }; 658 659 enum hal_reo_dest_ring_error_code { 660 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 661 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 662 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 663 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 664 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 665 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 666 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 667 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 668 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 669 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 670 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 671 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 672 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 673 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 674 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 675 HAL_REO_DEST_RING_ERROR_CODE_MAX, 676 }; 677 678 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 679 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(8) 680 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 681 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 682 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 683 684 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0) 685 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 686 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 687 688 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 689 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 690 691 struct hal_reo_dest_ring { 692 struct ath11k_buffer_addr buf_addr_info; 693 struct rx_mpdu_desc rx_mpdu_info; 694 struct rx_msdu_desc rx_msdu_info; 695 u32 queue_addr_lo; 696 u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 697 u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */ 698 u32 rsvd0; 699 u32 rsvd1; 700 u32 rsvd2; 701 u32 rsvd3; 702 u32 rsvd4; 703 u32 rsvd5; 704 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 705 } __packed; 706 707 /* hal_reo_dest_ring 708 * 709 * Producer: RXDMA 710 * Consumer: REO/SW/FW 711 * 712 * buf_addr_info 713 * Details of the physical address of a buffer or MSDU 714 * link descriptor. 715 * 716 * rx_mpdu_info 717 * General information related to the MPDU that is passed 718 * on from REO entrance ring to the REO destination ring. 719 * 720 * rx_msdu_info 721 * General information related to the MSDU that is passed 722 * on from RXDMA all the way to the REO destination ring. 723 * 724 * queue_addr_lo 725 * Address (lower 32 bits) of the REO queue descriptor. 726 * 727 * queue_addr_hi 728 * Address (upper 8 bits) of the REO queue descriptor. 729 * 730 * buffer_type 731 * Indicates the type of address provided in the buf_addr_info. 732 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 733 * 734 * push_reason 735 * Reason for pushing this frame to this exit ring. Values are 736 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 737 * 738 * error_code 739 * Valid only when 'push_reason' is set. All error codes are 740 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 741 * 742 * rx_queue_num 743 * Indicates the REO MPDU reorder queue id from which this frame 744 * originated. 745 * 746 * reorder_info_valid 747 * When set, REO has been instructed to not perform the actual 748 * re-ordering of frames for this queue, but just to insert 749 * the reorder opcodes. 750 * 751 * reorder_opcode 752 * Field is valid when 'reorder_info_valid' is set. This field is 753 * always valid for debug purpose as well. 754 * 755 * reorder_slot_idx 756 * Valid only when 'reorder_info_valid' is set. 757 * 758 * ring_id 759 * The buffer pointer ring id. 760 * 0 - Idle ring 761 * 1 - N refers to other rings. 762 * 763 * looping_count 764 * Indicates the number of times the producer of entries into 765 * this ring has looped around the ring. 766 */ 767 768 enum hal_reo_entr_rxdma_ecode { 769 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 770 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 771 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 772 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 773 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 774 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 775 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 776 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 777 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 778 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 779 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 780 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 781 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 782 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 783 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 784 }; 785 786 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 787 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 788 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 789 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 790 791 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 792 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 793 794 struct hal_reo_entrance_ring { 795 struct ath11k_buffer_addr buf_addr_info; 796 struct rx_mpdu_desc rx_mpdu_info; 797 u32 queue_addr_lo; 798 u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 799 u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 800 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 801 802 } __packed; 803 804 /* hal_reo_entrance_ring 805 * 806 * Producer: RXDMA 807 * Consumer: REO 808 * 809 * buf_addr_info 810 * Details of the physical address of a buffer or MSDU 811 * link descriptor. 812 * 813 * rx_mpdu_info 814 * General information related to the MPDU that is passed 815 * on from REO entrance ring to the REO destination ring. 816 * 817 * queue_addr_lo 818 * Address (lower 32 bits) of the REO queue descriptor. 819 * 820 * queue_addr_hi 821 * Address (upper 8 bits) of the REO queue descriptor. 822 * 823 * mpdu_byte_count 824 * An approximation of the number of bytes received in this MPDU. 825 * Used to keeps stats on the amount of data flowing 826 * through a queue. 827 * 828 * reo_destination_indication 829 * The id of the reo exit ring where the msdu frame shall push 830 * after (MPDU level) reordering has finished. Values are defined 831 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 832 * 833 * frameless_bar 834 * Indicates that this REO entrance ring struct contains BAR info 835 * from a multi TID BAR frame. The original multi TID BAR frame 836 * itself contained all the REO info for the first TID, but all 837 * the subsequent TID info and their linkage to the REO descriptors 838 * is passed down as 'frameless' BAR info. 839 * 840 * The only fields valid in this descriptor when this bit is set 841 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 842 * bar_frame and peer_meta_data. 843 * 844 * rxdma_push_reason 845 * Reason for pushing this frame to this exit ring. Values are 846 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 847 * 848 * rxdma_error_code 849 * Valid only when 'push_reason' is set. All error codes are 850 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 851 * 852 * ring_id 853 * The buffer pointer ring id. 854 * 0 - Idle ring 855 * 1 - N refers to other rings. 856 * 857 * looping_count 858 * Indicates the number of times the producer of entries into 859 * this ring has looped around the ring. 860 */ 861 862 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 863 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 864 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) 865 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) 866 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) 867 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) 868 869 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 870 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) 871 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 872 873 struct hal_sw_monitor_ring { 874 struct ath11k_buffer_addr buf_addr_info; 875 struct rx_mpdu_desc rx_mpdu_info; 876 struct ath11k_buffer_addr status_buf_addr_info; 877 u32 info0; 878 u32 info1; 879 } __packed; 880 881 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 882 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 883 884 struct hal_reo_cmd_hdr { 885 u32 info0; 886 } __packed; 887 888 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 889 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 890 891 struct hal_reo_get_queue_stats { 892 struct hal_reo_cmd_hdr cmd; 893 u32 queue_addr_lo; 894 u32 info0; 895 u32 rsvd0[6]; 896 } __packed; 897 898 /* hal_reo_get_queue_stats 899 * Producer: SW 900 * Consumer: REO 901 * 902 * cmd 903 * Details for command execution tracking purposes. 904 * 905 * queue_addr_lo 906 * Address (lower 32 bits) of the REO queue descriptor. 907 * 908 * queue_addr_hi 909 * Address (upper 8 bits) of the REO queue descriptor. 910 * 911 * clear_stats 912 * Clear stats settings. When set, Clear the stats after 913 * generating the status. 914 * 915 * Following stats will be cleared. 916 * Timeout_count 917 * Forward_due_to_bar_count 918 * Duplicate_count 919 * Frames_in_order_count 920 * BAR_received_count 921 * MPDU_Frames_processed_count 922 * MSDU_Frames_processed_count 923 * Total_processed_byte_count 924 * Late_receive_MPDU_count 925 * window_jump_2k 926 * Hole_count 927 */ 928 929 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 930 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 931 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 932 933 struct hal_reo_flush_queue { 934 struct hal_reo_cmd_hdr cmd; 935 u32 desc_addr_lo; 936 u32 info0; 937 u32 rsvd0[6]; 938 } __packed; 939 940 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 941 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 942 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 943 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 944 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 945 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 946 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 947 948 struct hal_reo_flush_cache { 949 struct hal_reo_cmd_hdr cmd; 950 u32 cache_addr_lo; 951 u32 info0; 952 u32 rsvd0[6]; 953 } __packed; 954 955 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 956 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 957 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 958 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 959 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 960 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 961 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 962 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 963 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 964 965 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 966 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 967 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 968 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 969 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 970 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 971 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 972 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 973 974 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 975 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 976 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 977 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 978 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 979 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 980 981 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 982 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 983 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 984 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) 985 986 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 987 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 988 989 enum hal_encrypt_type { 990 HAL_ENCRYPT_TYPE_WEP_40, 991 HAL_ENCRYPT_TYPE_WEP_104, 992 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 993 HAL_ENCRYPT_TYPE_WEP_128, 994 HAL_ENCRYPT_TYPE_TKIP_MIC, 995 HAL_ENCRYPT_TYPE_WAPI, 996 HAL_ENCRYPT_TYPE_CCMP_128, 997 HAL_ENCRYPT_TYPE_OPEN, 998 HAL_ENCRYPT_TYPE_CCMP_256, 999 HAL_ENCRYPT_TYPE_GCMP_128, 1000 HAL_ENCRYPT_TYPE_AES_GCMP_256, 1001 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 1002 }; 1003 1004 enum hal_tcl_encap_type { 1005 HAL_TCL_ENCAP_TYPE_RAW, 1006 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 1007 HAL_TCL_ENCAP_TYPE_ETHERNET, 1008 HAL_TCL_ENCAP_TYPE_802_3 = 3, 1009 }; 1010 1011 enum hal_tcl_desc_type { 1012 HAL_TCL_DESC_TYPE_BUFFER, 1013 HAL_TCL_DESC_TYPE_EXT_DESC, 1014 }; 1015 1016 enum hal_wbm_htt_tx_comp_status { 1017 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 1018 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 1019 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 1020 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 1021 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 1022 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 1023 }; 1024 1025 struct hal_tcl_data_cmd { 1026 struct ath11k_buffer_addr buf_addr_info; 1027 u32 info0; 1028 u32 info1; 1029 u32 info2; 1030 u32 info3; 1031 u32 info4; 1032 } __packed; 1033 1034 /* hal_tcl_data_cmd 1035 * 1036 * buf_addr_info 1037 * Details of the physical address of a buffer or MSDU 1038 * link descriptor. 1039 * 1040 * desc_type 1041 * Indicates the type of address provided in the buf_addr_info. 1042 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1043 * 1044 * epd 1045 * When this bit is set then input packet is an EPD type. 1046 * 1047 * encap_type 1048 * Indicates the encapsulation that HW will perform. Values are 1049 * defined in enum %HAL_TCL_ENCAP_TYPE_. 1050 * 1051 * encrypt_type 1052 * Field only valid for encap_type: RAW 1053 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 1054 * 1055 * src_buffer_swap 1056 * Treats source memory (packet buffer) organization as big-endian. 1057 * 1'b0: Source memory is little endian 1058 * 1'b1: Source memory is big endian 1059 * 1060 * link_meta_swap 1061 * Treats link descriptor and Metadata as big-endian. 1062 * 1'b0: memory is little endian 1063 * 1'b1: memory is big endian 1064 * 1065 * search_type 1066 * Search type select 1067 * 0 - Normal search, 1 - Index based address search, 1068 * 2 - Index based flow search 1069 * 1070 * addrx_en 1071 * addry_en 1072 * Address X/Y search enable in ASE correspondingly. 1073 * 1'b0: Search disable 1074 * 1'b1: Search Enable 1075 * 1076 * cmd_num 1077 * This number can be used to match against status. 1078 * 1079 * data_length 1080 * MSDU length in case of direct descriptor. Length of link 1081 * extension descriptor in case of Link extension descriptor. 1082 * 1083 * *_checksum_en 1084 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1085 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1086 * 1087 * to_fw 1088 * Forward packet to FW along with classification result. The 1089 * packet will not be forward to TQM when this bit is set. 1090 * 1'b0: Use classification result to forward the packet. 1091 * 1'b1: Override classification result & forward packet only to fw 1092 * 1093 * packet_offset 1094 * Packet offset from Metadata in case of direct buffer descriptor. 1095 * 1096 * buffer_timestamp 1097 * buffer_timestamp_valid 1098 * Frame system entrance timestamp. It shall be filled by first 1099 * module (SW, TCL or TQM) that sees the frames first. 1100 * 1101 * mesh_enable 1102 * For raw WiFi frames, this indicates transmission to a mesh STA, 1103 * enabling the interpretation of the 'Mesh Control Present' bit 1104 * (bit 8) of QoS Control. 1105 * For native WiFi frames, this indicates that a 'Mesh Control' 1106 * field is present between the header and the LLC. 1107 * 1108 * hlos_tid_overwrite 1109 * 1110 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1111 * fields and use HLOS_TID as the final TID. Otherwise TCL 1112 * shall consider the DSCP and PCP fields as well as HLOS_TID 1113 * and choose a final TID based on the configured priority 1114 * 1115 * hlos_tid 1116 * HLOS MSDU priority 1117 * Field is used when HLOS_TID_overwrite is set. 1118 * 1119 * lmac_id 1120 * TCL uses this LMAC_ID in address search, i.e, while 1121 * finding matching entry for the packet in AST corresponding 1122 * to given LMAC_ID 1123 * 1124 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 1125 * match for any MAC 1126 * 1127 * dscp_tid_table_num 1128 * DSCP to TID mapping table number that need to be used 1129 * for the MSDU. 1130 * 1131 * search_index 1132 * The index that will be used for index based address or 1133 * flow search. The field is valid when 'search_type' is 1 or 2. 1134 * 1135 * cache_set_num 1136 * 1137 * Cache set number that should be used to cache the index 1138 * based search results, for address and flow search. This 1139 * value should be equal to LSB four bits of the hash value of 1140 * match data, in case of search index points to an entry which 1141 * may be used in content based search also. The value can be 1142 * anything when the entry pointed by search index will not be 1143 * used for content based search. 1144 * 1145 * ring_id 1146 * The buffer pointer ring ID. 1147 * 0 refers to the IDLE ring 1148 * 1 - N refers to other rings 1149 * 1150 * looping_count 1151 * 1152 * A count value that indicates the number of times the 1153 * producer of entries into the Ring has looped around the 1154 * ring. 1155 * 1156 * At initialization time, this value is set to 0. On the 1157 * first loop, this value is set to 1. After the max value is 1158 * reached allowed by the number of bits for this field, the 1159 * count value continues with 0 again. 1160 * 1161 * In case SW is the consumer of the ring entries, it can 1162 * use this field to figure out up to where the producer of 1163 * entries has created new entries. This eliminates the need to 1164 * check where the head pointer' of the ring is located once 1165 * the SW starts processing an interrupt indicating that new 1166 * entries have been put into this ring... 1167 * 1168 * Also note that SW if it wants only needs to look at the 1169 * LSB bit of this count value. 1170 */ 1171 1172 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1173 1174 enum hal_tcl_gse_ctrl { 1175 HAL_TCL_GSE_CTRL_RD_STAT, 1176 HAL_TCL_GSE_CTRL_SRCH_DIS, 1177 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 1178 HAL_TCL_GSE_CTRL_WR_BK_ALL, 1179 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 1180 HAL_TCL_GSE_CTRL_INVAL_ALL, 1181 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 1182 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 1183 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 1184 }; 1185 1186 /* hal_tcl_gse_ctrl 1187 * 1188 * rd_stat 1189 * Report or Read statistics 1190 * srch_dis 1191 * Search disable. Report only Hash. 1192 * wr_bk_single 1193 * Write Back single entry 1194 * wr_bk_all 1195 * Write Back entire cache entry 1196 * inval_single 1197 * Invalidate single cache entry 1198 * inval_all 1199 * Invalidate entire cache 1200 * wr_bk_inval_single 1201 * Write back and invalidate single entry in cache 1202 * wr_bk_inval_all 1203 * Write back and invalidate entire cache 1204 * clr_stat_single 1205 * Clear statistics for single entry 1206 */ 1207 1208 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 1209 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 1210 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 1211 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 1212 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 1213 1214 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 1215 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 1216 1217 struct hal_tcl_gse_cmd { 1218 u32 ctrl_buf_addr_lo; 1219 u32 info0; 1220 u32 meta_data[2]; 1221 u32 rsvd0[2]; 1222 u32 info1; 1223 } __packed; 1224 1225 /* hal_tcl_gse_cmd 1226 * 1227 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1228 * Address of a control buffer containing additional info needed 1229 * for this command execution. 1230 * 1231 * gse_ctrl 1232 * GSE control operations. This includes cache operations and table 1233 * entry statistics read/clear operation. Values are defined in 1234 * enum %HAL_TCL_GSE_CTRL. 1235 * 1236 * gse_sel 1237 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1238 * 0: FSE select 1: ASE select 1239 * 1240 * status_destination_ring_id 1241 * TCL status ring to which the GSE status needs to be send. 1242 * 1243 * swap 1244 * Bit to enable byte swapping of contents of buffer. 1245 * 1246 * meta_data 1247 * Meta data to be returned in the status descriptor 1248 */ 1249 1250 enum hal_tcl_cache_op_res { 1251 HAL_TCL_CACHE_OP_RES_DONE, 1252 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1253 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1254 }; 1255 1256 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 1257 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 1258 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 1259 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 1260 1261 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 1262 1263 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 1264 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 1265 1266 struct hal_tcl_status_ring { 1267 u32 info0; 1268 u32 msdu_byte_count; 1269 u32 msdu_timestamp; 1270 u32 meta_data[2]; 1271 u32 info1; 1272 u32 rsvd0; 1273 u32 info2; 1274 } __packed; 1275 1276 /* hal_tcl_status_ring 1277 * 1278 * gse_ctrl 1279 * GSE control operations. This includes cache operations and table 1280 * entry statistics read/clear operation. Values are defined in 1281 * enum %HAL_TCL_GSE_CTRL. 1282 * 1283 * gse_sel 1284 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1285 * 0: FSE select 1: ASE select 1286 * 1287 * cache_op_res 1288 * Cache operation result. Values are defined in enum 1289 * %HAL_TCL_CACHE_OP_RES_. 1290 * 1291 * msdu_cnt 1292 * msdu_byte_count 1293 * MSDU count of Entry and MSDU byte count for entry 1. 1294 * 1295 * hash_indx 1296 * Hash value of the entry in case of search failed or disabled. 1297 */ 1298 1299 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1300 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1301 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1302 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1303 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1304 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1305 1306 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1307 1308 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1309 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1310 1311 struct hal_ce_srng_src_desc { 1312 u32 buffer_addr_low; 1313 u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1314 u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1315 u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1316 } __packed; 1317 1318 /* 1319 * hal_ce_srng_src_desc 1320 * 1321 * buffer_addr_lo 1322 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1323 * 1324 * buffer_addr_hi 1325 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1326 * 1327 * toeplitz_en 1328 * Enable generation of 32-bit Toeplitz-LFSR hash for 1329 * data transfer. In case of gather field in first source 1330 * ring entry of the gather copy cycle in taken into account. 1331 * 1332 * src_swap 1333 * Treats source memory organization as big-endian. For 1334 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1335 * and byte 1 is swapped with byte 2. 1336 * In case of gather field in first source ring entry of 1337 * the gather copy cycle in taken into account. 1338 * 1339 * dest_swap 1340 * Treats destination memory organization as big-endian. 1341 * For each dword write (4 bytes), the byte 0 is swapped with 1342 * byte 3 and byte 1 is swapped with byte 2. 1343 * In case of gather field in first source ring entry of 1344 * the gather copy cycle in taken into account. 1345 * 1346 * gather 1347 * Enables gather of multiple copy engine source 1348 * descriptors to one destination. 1349 * 1350 * ce_res_0 1351 * Reserved 1352 * 1353 * 1354 * length 1355 * Length of the buffer in units of octets of the current 1356 * descriptor 1357 * 1358 * fw_metadata 1359 * Meta data used by FW. 1360 * In case of gather field in first source ring entry of 1361 * the gather copy cycle in taken into account. 1362 * 1363 * ce_res_1 1364 * Reserved 1365 * 1366 * ce_res_2 1367 * Reserved 1368 * 1369 * ring_id 1370 * The buffer pointer ring ID. 1371 * 0 refers to the IDLE ring 1372 * 1 - N refers to other rings 1373 * Helps with debugging when dumping ring contents. 1374 * 1375 * looping_count 1376 * A count value that indicates the number of times the 1377 * producer of entries into the Ring has looped around the 1378 * ring. 1379 * 1380 * At initialization time, this value is set to 0. On the 1381 * first loop, this value is set to 1. After the max value is 1382 * reached allowed by the number of bits for this field, the 1383 * count value continues with 0 again. 1384 * 1385 * In case SW is the consumer of the ring entries, it can 1386 * use this field to figure out up to where the producer of 1387 * entries has created new entries. This eliminates the need to 1388 * check where the head pointer' of the ring is located once 1389 * the SW starts processing an interrupt indicating that new 1390 * entries have been put into this ring... 1391 * 1392 * Also note that SW if it wants only needs to look at the 1393 * LSB bit of this count value. 1394 */ 1395 1396 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1397 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1398 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1399 1400 struct hal_ce_srng_dest_desc { 1401 u32 buffer_addr_low; 1402 u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1403 } __packed; 1404 1405 /* hal_ce_srng_dest_desc 1406 * 1407 * dst_buffer_low 1408 * LSB 32 bits of the 40 Bit Pointer to the Destination 1409 * buffer 1410 * 1411 * dst_buffer_high 1412 * MSB 8 bits of the 40 Bit Pointer to the Destination 1413 * buffer 1414 * 1415 * ce_res_4 1416 * Reserved 1417 * 1418 * ring_id 1419 * The buffer pointer ring ID. 1420 * 0 refers to the IDLE ring 1421 * 1 - N refers to other rings 1422 * Helps with debugging when dumping ring contents. 1423 * 1424 * looping_count 1425 * A count value that indicates the number of times the 1426 * producer of entries into the Ring has looped around the 1427 * ring. 1428 * 1429 * At initialization time, this value is set to 0. On the 1430 * first loop, this value is set to 1. After the max value is 1431 * reached allowed by the number of bits for this field, the 1432 * count value continues with 0 again. 1433 * 1434 * In case SW is the consumer of the ring entries, it can 1435 * use this field to figure out up to where the producer of 1436 * entries has created new entries. This eliminates the need to 1437 * check where the head pointer' of the ring is located once 1438 * the SW starts processing an interrupt indicating that new 1439 * entries have been put into this ring... 1440 * 1441 * Also note that SW if it wants only needs to look at the 1442 * LSB bit of this count value. 1443 */ 1444 1445 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1446 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1447 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1448 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1449 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1450 1451 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 1452 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1453 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1454 1455 struct hal_ce_srng_dst_status_desc { 1456 u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1457 u32 toeplitz_hash0; 1458 u32 toeplitz_hash1; 1459 u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1460 } __packed; 1461 1462 /* hal_ce_srng_dst_status_desc 1463 * 1464 * ce_res_5 1465 * Reserved 1466 * 1467 * toeplitz_en 1468 * 1469 * src_swap 1470 * Source memory buffer swapped 1471 * 1472 * dest_swap 1473 * Destination memory buffer swapped 1474 * 1475 * gather 1476 * Gather of multiple copy engine source descriptors to one 1477 * destination enabled 1478 * 1479 * ce_res_6 1480 * Reserved 1481 * 1482 * length 1483 * Sum of all the Lengths of the source descriptor in the 1484 * gather chain 1485 * 1486 * toeplitz_hash_0 1487 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1488 * 1489 * toeplitz_hash_1 1490 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1491 * 1492 * fw_metadata 1493 * Meta data used by FW 1494 * In case of gather field in first source ring entry of 1495 * the gather copy cycle in taken into account. 1496 * 1497 * ce_res_7 1498 * Reserved 1499 * 1500 * ring_id 1501 * The buffer pointer ring ID. 1502 * 0 refers to the IDLE ring 1503 * 1 - N refers to other rings 1504 * Helps with debugging when dumping ring contents. 1505 * 1506 * looping_count 1507 * A count value that indicates the number of times the 1508 * producer of entries into the Ring has looped around the 1509 * ring. 1510 * 1511 * At initialization time, this value is set to 0. On the 1512 * first loop, this value is set to 1. After the max value is 1513 * reached allowed by the number of bits for this field, the 1514 * count value continues with 0 again. 1515 * 1516 * In case SW is the consumer of the ring entries, it can 1517 * use this field to figure out up to where the producer of 1518 * entries has created new entries. This eliminates the need to 1519 * check where the head pointer' of the ring is located once 1520 * the SW starts processing an interrupt indicating that new 1521 * entries have been put into this ring... 1522 * 1523 * Also note that SW if it wants only needs to look at the 1524 * LSB bit of this count value. 1525 */ 1526 1527 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1528 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 1529 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 1530 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 1531 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 1532 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 1533 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 1534 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 1535 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 1536 1537 enum hal_tx_rate_stats_bw { 1538 HAL_TX_RATE_STATS_BW_20, 1539 HAL_TX_RATE_STATS_BW_40, 1540 HAL_TX_RATE_STATS_BW_80, 1541 HAL_TX_RATE_STATS_BW_160, 1542 }; 1543 1544 enum hal_tx_rate_stats_pkt_type { 1545 HAL_TX_RATE_STATS_PKT_TYPE_11A, 1546 HAL_TX_RATE_STATS_PKT_TYPE_11B, 1547 HAL_TX_RATE_STATS_PKT_TYPE_11N, 1548 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 1549 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 1550 }; 1551 1552 enum hal_tx_rate_stats_sgi { 1553 HAL_TX_RATE_STATS_SGI_08US, 1554 HAL_TX_RATE_STATS_SGI_04US, 1555 HAL_TX_RATE_STATS_SGI_16US, 1556 HAL_TX_RATE_STATS_SGI_32US, 1557 }; 1558 1559 struct hal_tx_rate_stats { 1560 u32 info0; 1561 u32 tsf; 1562 } __packed; 1563 1564 struct hal_wbm_link_desc { 1565 struct ath11k_buffer_addr buf_addr_info; 1566 } __packed; 1567 1568 /* hal_wbm_link_desc 1569 * 1570 * Producer: WBM 1571 * Consumer: WBM 1572 * 1573 * buf_addr_info 1574 * Details of the physical address of a buffer or MSDU 1575 * link descriptor. 1576 */ 1577 1578 enum hal_wbm_rel_src_module { 1579 HAL_WBM_REL_SRC_MODULE_TQM, 1580 HAL_WBM_REL_SRC_MODULE_RXDMA, 1581 HAL_WBM_REL_SRC_MODULE_REO, 1582 HAL_WBM_REL_SRC_MODULE_FW, 1583 HAL_WBM_REL_SRC_MODULE_SW, 1584 }; 1585 1586 enum hal_wbm_rel_desc_type { 1587 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1588 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1589 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1590 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1591 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1592 }; 1593 1594 /* hal_wbm_rel_desc_type 1595 * 1596 * msdu_buffer 1597 * The address points to an MSDU buffer 1598 * 1599 * msdu_link_descriptor 1600 * The address points to an Tx MSDU link descriptor 1601 * 1602 * mpdu_link_descriptor 1603 * The address points to an MPDU link descriptor 1604 * 1605 * msdu_ext_descriptor 1606 * The address points to an MSDU extension descriptor 1607 * 1608 * queue_ext_descriptor 1609 * The address points to an TQM queue extension descriptor. WBM should 1610 * treat this is the same way as a link descriptor. 1611 */ 1612 1613 enum hal_wbm_rel_bm_act { 1614 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1615 HAL_WBM_REL_BM_ACT_REL_MSDU, 1616 }; 1617 1618 /* hal_wbm_rel_bm_act 1619 * 1620 * put_in_idle_list 1621 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1622 * MDPU link descriptor, BM does not need to check to release any 1623 * individual MSDU buffers. 1624 * 1625 * release_msdu_list 1626 * This BM action can only be used in combination with desc_type being 1627 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1628 * pointer in the MSDU link descriptor is the first of an MPDU that is 1629 * released. BM shall release all the MSDU buffers linked to this first 1630 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1631 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1632 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1633 * descriptor itself shall also be released. 1634 */ 1635 1636 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1637 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1638 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1639 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1640 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1641 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1642 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1643 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1644 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1645 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 1646 1647 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1648 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1649 1650 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1651 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 1652 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 1653 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 1654 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 1655 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 1656 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1657 1658 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 1659 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 1660 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 1661 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 1662 1663 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 1664 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 1665 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 1666 1667 struct hal_wbm_release_ring { 1668 struct ath11k_buffer_addr buf_addr_info; 1669 u32 info0; 1670 u32 info1; 1671 u32 info2; 1672 struct hal_tx_rate_stats rate_stats; 1673 u32 info3; 1674 } __packed; 1675 1676 /* hal_wbm_release_ring 1677 * 1678 * Producer: SW/TQM/RXDMA/REO/SWITCH 1679 * Consumer: WBM/SW/FW 1680 * 1681 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 1682 * for software based completions. 1683 * 1684 * buf_addr_info 1685 * Details of the physical address of the buffer or link descriptor. 1686 * 1687 * release_source_module 1688 * Indicates which module initiated the release of this buffer/descriptor. 1689 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 1690 * 1691 * bm_action 1692 * Field only valid when the field return_buffer_manager in 1693 * Released_buff_or_desc_addr_info indicates: 1694 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 1695 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 1696 * 1697 * buffer_or_desc_type 1698 * Field only valid when WBM is marked as the return_buffer_manager in 1699 * the Released_Buffer_address_info. Indicates that type of buffer or 1700 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 1701 * 1702 * first_msdu_index 1703 * Field only valid for the bm_action release_msdu_list. The index of the 1704 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 1705 * 1706 * tqm_release_reason 1707 * Field only valid when Release_source_module is set to release_source_TQM 1708 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 1709 * 1710 * rxdma_push_reason 1711 * reo_push_reason 1712 * Indicates why rxdma/reo pushed the frame to this ring and values are 1713 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 1714 * 1715 * rxdma_error_code 1716 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 1717 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 1718 * 1719 * reo_error_code 1720 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 1721 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 1722 * 1723 * wbm_internal_error 1724 * Is set when WBM got a buffer pointer but the action was to push it to 1725 * the idle link descriptor ring or do link related activity OR 1726 * Is set when WBM got a link buffer pointer but the action was to push it 1727 * to the buffer descriptor ring. 1728 * 1729 * tqm_status_number 1730 * The value in this field is equal to tqm_cmd_number in TQM command. It is 1731 * used to correlate the statu with TQM commands. Only valid when 1732 * release_source_module is TQM. 1733 * 1734 * transmit_count 1735 * The number of times the frame has been transmitted, valid only when 1736 * release source in TQM. 1737 * 1738 * ack_frame_rssi 1739 * This field is only valid when the source is TQM. If this frame is 1740 * removed as the result of the reception of an ACK or BA, this field 1741 * indicates the RSSI of the received ACK or BA frame. 1742 * 1743 * sw_release_details_valid 1744 * This is set when WMB got a 'release_msdu_list' command from TQM and 1745 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 1746 * and pass them one at a time on to the 'buffer owner'. 1747 * 1748 * first_msdu 1749 * Field only valid when SW_release_details_valid is set. 1750 * When set, this MSDU is the first MSDU pointed to in the 1751 * 'release_msdu_list' command. 1752 * 1753 * last_msdu 1754 * Field only valid when SW_release_details_valid is set. 1755 * When set, this MSDU is the last MSDU pointed to in the 1756 * 'release_msdu_list' command. 1757 * 1758 * msdu_part_of_amsdu 1759 * Field only valid when SW_release_details_valid is set. 1760 * When set, this MSDU was part of an A-MSDU in MPDU 1761 * 1762 * fw_tx_notify_frame 1763 * Field only valid when SW_release_details_valid is set. 1764 * 1765 * buffer_timestamp 1766 * Field only valid when SW_release_details_valid is set. 1767 * This is the Buffer_timestamp field from the 1768 * Timestamp in units of 1024 us 1769 * 1770 * struct hal_tx_rate_stats rate_stats 1771 * Details for command execution tracking purposes. 1772 * 1773 * sw_peer_id 1774 * tid 1775 * Field only valid when Release_source_module is set to 1776 * release_source_TQM 1777 * 1778 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 1779 * not fetched and hence sw_peer_id and tid = 0 1780 * 1781 * buffer_or_desc_type = e_num 0 1782 * MSDU_rel_buffertqm_release_reason = e_num 1 1783 * tqm_rr_rem_cmd_rem 1784 * 1785 * 2) Release of msdu buffer due to Flow is not fetched and 1786 * hence sw_peer_id and tid = 0 1787 * 1788 * buffer_or_desc_type = e_num 0 1789 * MSDU_rel_buffertqm_release_reason = e_num 1 1790 * tqm_rr_rem_cmd_rem 1791 * 1792 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 1793 * command. 1794 * 1795 * buffer_or_desc_type = e_num1 1796 * msdu_link_descriptortqm_release_reason can be:e_num 1 1797 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 1798 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 1799 * 1800 * This field represents the TID from the TX_MSDU_FLOW 1801 * descriptor or TX_MPDU_QUEUE descriptor 1802 * 1803 * rind_id 1804 * For debugging. 1805 * This field is filled in by the SRNG module. 1806 * It help to identify the ring that is being looked 1807 * 1808 * looping_count 1809 * A count value that indicates the number of times the 1810 * producer of entries into the Buffer Manager Ring has looped 1811 * around the ring. 1812 * 1813 * At initialization time, this value is set to 0. On the 1814 * first loop, this value is set to 1. After the max value is 1815 * reached allowed by the number of bits for this field, the 1816 * count value continues with 0 again. 1817 * 1818 * In case SW is the consumer of the ring entries, it can 1819 * use this field to figure out up to where the producer of 1820 * entries has created new entries. This eliminates the need to 1821 * check where the head pointer' of the ring is located once 1822 * the SW starts processing an interrupt indicating that new 1823 * entries have been put into this ring... 1824 * 1825 * Also note that SW if it wants only needs to look at the 1826 * LSB bit of this count value. 1827 */ 1828 1829 /** 1830 * enum hal_wbm_tqm_rel_reason - TQM release reason code 1831 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 1832 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 1833 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 1834 * initiated by sw. 1835 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 1836 * initiated by sw. 1837 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 1838 * mpdus. 1839 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 1840 * fw with fw_reason1. 1841 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 1842 * fw with fw_reason2. 1843 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 1844 * fw with fw_reason3. 1845 */ 1846 enum hal_wbm_tqm_rel_reason { 1847 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 1848 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 1849 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 1850 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 1851 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 1852 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 1853 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 1854 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 1855 }; 1856 1857 struct hal_wbm_buffer_ring { 1858 struct ath11k_buffer_addr buf_addr_info; 1859 }; 1860 1861 enum hal_desc_owner { 1862 HAL_DESC_OWNER_WBM, 1863 HAL_DESC_OWNER_SW, 1864 HAL_DESC_OWNER_TQM, 1865 HAL_DESC_OWNER_RXDMA, 1866 HAL_DESC_OWNER_REO, 1867 HAL_DESC_OWNER_SWITCH, 1868 }; 1869 1870 enum hal_desc_buf_type { 1871 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 1872 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 1873 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 1874 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 1875 HAL_DESC_BUF_TYPE_TX_FLOW, 1876 HAL_DESC_BUF_TYPE_TX_BUFFER, 1877 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 1878 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 1879 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 1880 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 1881 HAL_DESC_BUF_TYPE_RX_BUFFER, 1882 HAL_DESC_BUF_TYPE_IDLE_LINK, 1883 }; 1884 1885 #define HAL_DESC_REO_OWNED 4 1886 #define HAL_DESC_REO_QUEUE_DESC 8 1887 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 1888 #define HAL_DESC_REO_NON_QOS_TID 16 1889 1890 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 1891 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 1892 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 1893 1894 struct hal_desc_header { 1895 u32 info0; 1896 } __packed; 1897 1898 struct hal_rx_mpdu_link_ptr { 1899 struct ath11k_buffer_addr addr_info; 1900 } __packed; 1901 1902 struct hal_rx_msdu_details { 1903 struct ath11k_buffer_addr buf_addr_info; 1904 struct rx_msdu_desc rx_msdu_info; 1905 } __packed; 1906 1907 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 1908 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 1909 1910 struct hal_rx_msdu_link { 1911 struct hal_desc_header desc_hdr; 1912 struct ath11k_buffer_addr buf_addr_info; 1913 u32 info0; 1914 u32 pn[4]; 1915 struct hal_rx_msdu_details msdu_link[6]; 1916 } __packed; 1917 1918 struct hal_rx_reo_queue_ext { 1919 struct hal_desc_header desc_hdr; 1920 u32 rsvd; 1921 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 1922 } __packed; 1923 1924 /* hal_rx_reo_queue_ext 1925 * Consumer: REO 1926 * Producer: REO 1927 * 1928 * descriptor_header 1929 * Details about which module owns this struct. 1930 * 1931 * mpdu_link 1932 * Pointer to the next MPDU_link descriptor in the MPDU queue. 1933 */ 1934 1935 enum hal_rx_reo_queue_pn_size { 1936 HAL_RX_REO_QUEUE_PN_SIZE_24, 1937 HAL_RX_REO_QUEUE_PN_SIZE_48, 1938 HAL_RX_REO_QUEUE_PN_SIZE_128, 1939 }; 1940 1941 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 1942 1943 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 1944 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 1945 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 1946 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 1947 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 1948 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 1949 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 1950 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 1951 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 1952 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 1953 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 1954 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 1955 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 1956 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 1957 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 1958 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 1959 1960 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 1961 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 1962 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 1963 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 1964 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 1965 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 1966 1967 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 1968 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 1969 1970 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 1971 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 1972 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 1973 1974 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 1975 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 1976 1977 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 1978 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 1979 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 1980 1981 struct hal_rx_reo_queue { 1982 struct hal_desc_header desc_hdr; 1983 u32 rx_queue_num; 1984 u32 info0; 1985 u32 info1; 1986 u32 pn[4]; 1987 u32 last_rx_enqueue_timestamp; 1988 u32 last_rx_dequeue_timestamp; 1989 u32 next_aging_queue[2]; 1990 u32 prev_aging_queue[2]; 1991 u32 rx_bitmap[8]; 1992 u32 info2; 1993 u32 info3; 1994 u32 info4; 1995 u32 processed_mpdus; 1996 u32 processed_msdus; 1997 u32 processed_total_bytes; 1998 u32 info5; 1999 u32 rsvd[3]; 2000 struct hal_rx_reo_queue_ext ext_desc[]; 2001 } __packed; 2002 2003 /* hal_rx_reo_queue 2004 * 2005 * descriptor_header 2006 * Details about which module owns this struct. Note that sub field 2007 * Buffer_type shall be set to receive_reo_queue_descriptor. 2008 * 2009 * receive_queue_number 2010 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 2011 * 2012 * vld 2013 * Valid bit indicating a session is established and the queue descriptor 2014 * is valid. 2015 * associated_link_descriptor_counter 2016 * Indicates which of the 3 link descriptor counters shall be incremented 2017 * or decremented when link descriptors are added or removed from this 2018 * flow queue. 2019 * disable_duplicate_detection 2020 * When set, do not perform any duplicate detection. 2021 * soft_reorder_enable 2022 * When set, REO has been instructed to not perform the actual re-ordering 2023 * of frames for this queue, but just to insert the reorder opcodes. 2024 * ac 2025 * Indicates the access category of the queue descriptor. 2026 * bar 2027 * Indicates if BAR has been received. 2028 * retry 2029 * Retry bit is checked if this bit is set. 2030 * chk_2k_mode 2031 * Indicates what type of operation is expected from Reo when the received 2032 * frame SN falls within the 2K window. 2033 * oor_mode 2034 * Indicates what type of operation is expected when the received frame 2035 * falls within the OOR window. 2036 * ba_window_size 2037 * Indicates the negotiated (window size + 1). Max of 256 bits. 2038 * 2039 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2040 * session, with window size of 0). The 3 values here are the main values 2041 * validated, but other values should work as well. 2042 * 2043 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2044 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2045 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2046 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2047 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2048 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2049 * pn_size 2050 * REO shall perform the PN increment check, even number check, uneven 2051 * number check, PN error check and size of the PN field check. 2052 * ignore_ampdu_flag 2053 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2054 * 2055 * svld 2056 * Sequence number in next field is valid one. 2057 * ssn 2058 * Starting Sequence number of the session. 2059 * current_index 2060 * Points to last forwarded packet 2061 * seq_2k_error_detected_flag 2062 * REO has detected a 2k error jump in the sequence number and from that 2063 * moment forward, all new frames are forwarded directly to FW, without 2064 * duplicate detect, reordering, etc. 2065 * pn_error_detected_flag 2066 * REO has detected a PN error. 2067 */ 2068 2069 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2070 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2071 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2072 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2073 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2074 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2075 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2076 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2077 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2078 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2079 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2080 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2081 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2082 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2083 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2084 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2085 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2086 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2087 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2088 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2089 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2090 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2091 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2092 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2093 2094 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2095 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2096 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2097 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2098 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2099 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2100 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2101 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2102 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2103 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2104 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2105 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2106 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2107 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2108 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2109 2110 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 2111 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 2112 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 2113 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 2114 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 2115 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 2116 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 2117 2118 struct hal_reo_update_rx_queue { 2119 struct hal_reo_cmd_hdr cmd; 2120 u32 queue_addr_lo; 2121 u32 info0; 2122 u32 info1; 2123 u32 info2; 2124 u32 pn[4]; 2125 } __packed; 2126 2127 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2128 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2129 2130 struct hal_reo_unblock_cache { 2131 struct hal_reo_cmd_hdr cmd; 2132 u32 info0; 2133 u32 rsvd[7]; 2134 } __packed; 2135 2136 enum hal_reo_exec_status { 2137 HAL_REO_EXEC_STATUS_SUCCESS, 2138 HAL_REO_EXEC_STATUS_BLOCKED, 2139 HAL_REO_EXEC_STATUS_FAILED, 2140 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2141 }; 2142 2143 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2144 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2145 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2146 2147 struct hal_reo_status_hdr { 2148 u32 info0; 2149 u32 timestamp; 2150 } __packed; 2151 2152 /* hal_reo_status_hdr 2153 * Producer: REO 2154 * Consumer: SW 2155 * 2156 * status_num 2157 * The value in this field is equal to value of the reo command 2158 * number. This field helps to correlate the statuses with the REO 2159 * commands. 2160 * 2161 * execution_time (in us) 2162 * The amount of time REO took to execute the command. Note that 2163 * this time does not include the duration of the command waiting 2164 * in the command ring, before the execution started. 2165 * 2166 * execution_status 2167 * Execution status of the command. Values are defined in 2168 * enum %HAL_REO_EXEC_STATUS_. 2169 */ 2170 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2171 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 2172 2173 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2174 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2175 2176 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2177 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2178 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2179 2180 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2181 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2182 2183 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2184 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 2185 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 2186 2187 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2188 2189 struct hal_reo_get_queue_stats_status { 2190 struct hal_reo_status_hdr hdr; 2191 u32 info0; 2192 u32 pn[4]; 2193 u32 last_rx_enqueue_timestamp; 2194 u32 last_rx_dequeue_timestamp; 2195 u32 rx_bitmap[8]; 2196 u32 info1; 2197 u32 info2; 2198 u32 info3; 2199 u32 num_mpdu_frames; 2200 u32 num_msdu_frames; 2201 u32 total_bytes; 2202 u32 info4; 2203 u32 info5; 2204 } __packed; 2205 2206 /* hal_reo_get_queue_stats_status 2207 * Producer: REO 2208 * Consumer: SW 2209 * 2210 * status_hdr 2211 * Details that can link this status with the original command. It 2212 * also contains info on how long REO took to execute this command. 2213 * 2214 * ssn 2215 * Starting Sequence number of the session, this changes whenever 2216 * window moves (can be filled by SW then maintained by REO). 2217 * 2218 * current_index 2219 * Points to last forwarded packet. 2220 * 2221 * pn 2222 * Bits of the PN number. 2223 * 2224 * last_rx_enqueue_timestamp 2225 * last_rx_dequeue_timestamp 2226 * Timestamp of arrival of the last MPDU for this queue and 2227 * Timestamp of forwarding an MPDU accordingly. 2228 * 2229 * rx_bitmap 2230 * When a bit is set, the corresponding frame is currently held 2231 * in the re-order queue. The bitmap is Fully managed by HW. 2232 * 2233 * current_mpdu_count 2234 * current_msdu_count 2235 * The number of MPDUs and MSDUs in the queue. 2236 * 2237 * timeout_count 2238 * The number of times REO started forwarding frames even though 2239 * there is a hole in the bitmap. Forwarding reason is timeout. 2240 * 2241 * forward_due_to_bar_count 2242 * The number of times REO started forwarding frames even though 2243 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2244 * 2245 * duplicate_count 2246 * The number of duplicate frames that have been detected. 2247 * 2248 * frames_in_order_count 2249 * The number of frames that have been received in order (without 2250 * a hole that prevented them from being forwarded immediately). 2251 * 2252 * bar_received_count 2253 * The number of times a BAR frame is received. 2254 * 2255 * mpdu_frames_processed_count 2256 * msdu_frames_processed_count 2257 * The total number of MPDU/MSDU frames that have been processed. 2258 * 2259 * total_bytes 2260 * An approximation of the number of bytes received for this queue. 2261 * 2262 * late_receive_mpdu_count 2263 * The number of MPDUs received after the window had already moved 2264 * on. The 'late' sequence window is defined as 2265 * (Window SSN - 256) - (Window SSN - 1). 2266 * 2267 * window_jump_2k 2268 * The number of times the window moved more than 2K 2269 * 2270 * hole_count 2271 * The number of times a hole was created in the receive bitmap. 2272 * 2273 * looping_count 2274 * A count value that indicates the number of times the producer of 2275 * entries into this Ring has looped around the ring. 2276 */ 2277 2278 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2279 2280 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2281 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2282 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2283 2284 struct hal_reo_flush_queue_status { 2285 struct hal_reo_status_hdr hdr; 2286 u32 info0; 2287 u32 rsvd0[21]; 2288 u32 info1; 2289 } __packed; 2290 2291 /* hal_reo_flush_queue_status 2292 * Producer: REO 2293 * Consumer: SW 2294 * 2295 * status_hdr 2296 * Details that can link this status with the original command. It 2297 * also contains info on how long REO took to execute this command. 2298 * 2299 * error_detected 2300 * Status of blocking resource 2301 * 2302 * 0 - No error has been detected while executing this command 2303 * 1 - Error detected. The resource to be used for blocking was 2304 * already in use. 2305 * 2306 * looping_count 2307 * A count value that indicates the number of times the producer of 2308 * entries into this Ring has looped around the ring. 2309 */ 2310 2311 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2312 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2313 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2314 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2315 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2316 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2317 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2318 2319 struct hal_reo_flush_cache_status { 2320 struct hal_reo_status_hdr hdr; 2321 u32 info0; 2322 u32 rsvd0[21]; 2323 u32 info1; 2324 } __packed; 2325 2326 /* hal_reo_flush_cache_status 2327 * Producer: REO 2328 * Consumer: SW 2329 * 2330 * status_hdr 2331 * Details that can link this status with the original command. It 2332 * also contains info on how long REO took to execute this command. 2333 * 2334 * error_detected 2335 * Status for blocking resource handling 2336 * 2337 * 0 - No error has been detected while executing this command 2338 * 1 - An error in the blocking resource management was detected 2339 * 2340 * block_error_details 2341 * only valid when error_detected is set 2342 * 2343 * 0 - No blocking related errors found 2344 * 1 - Blocking resource is already in use 2345 * 2 - Resource requested to be unblocked, was not blocked 2346 * 2347 * cache_controller_flush_status_hit 2348 * The status that the cache controller returned on executing the 2349 * flush command. 2350 * 2351 * 0 - miss; 1 - hit 2352 * 2353 * cache_controller_flush_status_desc_type 2354 * Flush descriptor type 2355 * 2356 * cache_controller_flush_status_client_id 2357 * Module who made the flush request 2358 * 2359 * In REO, this is always 0 2360 * 2361 * cache_controller_flush_status_error 2362 * Error condition 2363 * 2364 * 0 - No error found 2365 * 1 - HW interface is still busy 2366 * 2 - Line currently locked. Used for one line flush command 2367 * 3 - At least one line is still locked. 2368 * Used for cache flush command. 2369 * 2370 * cache_controller_flush_count 2371 * The number of lines that were actually flushed out 2372 * 2373 * looping_count 2374 * A count value that indicates the number of times the producer of 2375 * entries into this Ring has looped around the ring. 2376 */ 2377 2378 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2379 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2380 2381 struct hal_reo_unblock_cache_status { 2382 struct hal_reo_status_hdr hdr; 2383 u32 info0; 2384 u32 rsvd0[21]; 2385 u32 info1; 2386 } __packed; 2387 2388 /* hal_reo_unblock_cache_status 2389 * Producer: REO 2390 * Consumer: SW 2391 * 2392 * status_hdr 2393 * Details that can link this status with the original command. It 2394 * also contains info on how long REO took to execute this command. 2395 * 2396 * error_detected 2397 * 0 - No error has been detected while executing this command 2398 * 1 - The blocking resource was not in use, and therefore it could 2399 * not be unblocked. 2400 * 2401 * unblock_type 2402 * Reference to the type of unblock command 2403 * 0 - Unblock a blocking resource 2404 * 1 - The entire cache usage is unblock 2405 * 2406 * looping_count 2407 * A count value that indicates the number of times the producer of 2408 * entries into this Ring has looped around the ring. 2409 */ 2410 2411 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2412 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2413 2414 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2415 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2416 2417 struct hal_reo_flush_timeout_list_status { 2418 struct hal_reo_status_hdr hdr; 2419 u32 info0; 2420 u32 info1; 2421 u32 rsvd0[20]; 2422 u32 info2; 2423 } __packed; 2424 2425 /* hal_reo_flush_timeout_list_status 2426 * Producer: REO 2427 * Consumer: SW 2428 * 2429 * status_hdr 2430 * Details that can link this status with the original command. It 2431 * also contains info on how long REO took to execute this command. 2432 * 2433 * error_detected 2434 * 0 - No error has been detected while executing this command 2435 * 1 - Command not properly executed and returned with error 2436 * 2437 * timeout_list_empty 2438 * When set, REO has depleted the timeout list and all entries are 2439 * gone. 2440 * 2441 * release_desc_count 2442 * Producer: SW; Consumer: REO 2443 * The number of link descriptor released 2444 * 2445 * forward_buf_count 2446 * Producer: SW; Consumer: REO 2447 * The number of buffers forwarded to the REO destination rings 2448 * 2449 * looping_count 2450 * A count value that indicates the number of times the producer of 2451 * entries into this Ring has looped around the ring. 2452 */ 2453 2454 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2455 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2456 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2457 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2458 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 2459 2460 struct hal_reo_desc_thresh_reached_status { 2461 struct hal_reo_status_hdr hdr; 2462 u32 info0; 2463 u32 info1; 2464 u32 info2; 2465 u32 info3; 2466 u32 info4; 2467 u32 rsvd0[17]; 2468 u32 info5; 2469 } __packed; 2470 2471 /* hal_reo_desc_thresh_reached_status 2472 * Producer: REO 2473 * Consumer: SW 2474 * 2475 * status_hdr 2476 * Details that can link this status with the original command. It 2477 * also contains info on how long REO took to execute this command. 2478 * 2479 * threshold_index 2480 * The index of the threshold register whose value got reached 2481 * 2482 * link_descriptor_counter0 2483 * link_descriptor_counter1 2484 * link_descriptor_counter2 2485 * link_descriptor_counter_sum 2486 * Value of the respective counters at generation of this message 2487 * 2488 * looping_count 2489 * A count value that indicates the number of times the producer of 2490 * entries into this Ring has looped around the ring. 2491 */ 2492 2493 #endif /* ATH11K_HAL_DESC_H */ 2494