| /drivers/gpu/drm/kmb/ |
| D | kmb_regs.h | 400 #define HS_OFFSET(M) (((M) + 1) * 0x400) argument
403 #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) argument
417 #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ argument
435 #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ argument
448 #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ argument
452 #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ argument
457 #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ argument
461 #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ argument
465 #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ argument
469 #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ argument
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| /drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 37 unsigned int M, N, OD, POD; in get_mxclk_freq() local
319 int N, M, X, d; in sm750_calc_pll_value() local
391 unsigned int M = p_PLL->M; in sm750_format_pll_reg() local
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| D | ddk750_chip.h | 47 unsigned long M; member
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv50.c | 58 int P, N, M, id; in read_pll_src() local
326 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) in calc_pll()
381 int N, M, P1, P2; in nv50_clk_calc() local
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| D | mcp77.c | 163 u32 clock, int *N, int *M, int *P) in calc_pll()
208 int N, M, P1, P2 = 0; in mcp77_clk_calc() local
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| D | pllgt215.c | 34 int M, lM, hM, N, fN; in gt215_pll_calc() local
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| D | gt215.c | 112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
241 int P, N, M, diff; in gt215_pll_info() local
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| D | gf100.c | 66 u32 M = (coef & 0x000000ff) >> 0; in read_pll() local
255 int N, M, P, ret; in calc_pll() local
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| D | gk104.c | 67 u32 M = (coef & 0x000000ff) >> 0; in read_pll() local
268 int N, M, P, ret; in calc_pll() local
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| D | nv40.c | 46 int M = (ctrl & 0x000000ff) >> 0; in read_pll_1() local
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| D | pllnv04.c | 49 int M, N, thisP, P; in getMNP_single() local
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| /drivers/video/fbdev/nvidia/ |
| D | nv_hw.c | 144 unsigned int pll, N, M, MB, NB, P; in nvGetClocks() local
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; in nForceUpdateArbitrationSettings() local
772 unsigned M, N, P; in CalcVClock() local
818 unsigned M, N, P; in CalcVClock2Stage() local
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | ga100.c | 35 int N, fN, M, P; in ga100_devinit_pll_set() local
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| D | gv100.c | 35 int N, fN, M, P; in gv100_devinit_pll_set() local
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| D | tu102.c | 35 int N, fN, M, P; in tu102_devinit_pll_set() local
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| D | gf100.c | 37 int N, fN, M, P; in gf100_devinit_pll_set() local
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| D | gt215.c | 37 int N, fN, M, P; in gt215_devinit_pll_set() local
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| /drivers/comedi/drivers/ni_routing/tools/ |
| D | convert_c_to_py.c | 58 const char *M; in family_write() local
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| /drivers/video/fbdev/riva/ |
| D | riva_hw.c | 618 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1097 unsigned int M, N, P, pll, MClk, NVClk; in nForceUpdateArbitrationSettings() local
1163 unsigned M, N, P; in CalcVClock() local
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 73 struct bit_entry M; in nv40_ram_prog() local
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mbox.c | 406 #define M(_name, _id, _1, _2, _3) case _id: return # _name; in otx2_mbox_id2name() macro
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| /drivers/media/platform/qcom/camss/ |
| D | camss-vfe-gen1.c | 706 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) argument
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| /drivers/phy/freescale/ |
| D | phy-fsl-imx8qm-lvds-phy.c | 23 #define M(n) FIELD_PREP(M_MASK, (n)) macro
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| /drivers/clk/pxa/ |
| D | clk-pxa25x.c | 34 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L) argument
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| /drivers/media/dvb-frontends/ |
| D | mb86a16.c | 457 int M; in rf_val_set() local
640 int R, M, fOSC, fOSC_OFS; in freqerr_chk() local
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