1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_execbuf_util.h>
59
60 #include <drm/amdgpu_drm.h>
61 #include <drm/drm_gem.h>
62 #include <drm/drm_ioctl.h>
63
64 #include <kgd_kfd_interface.h>
65 #include "dm_pp_interface.h"
66 #include "kgd_pp_interface.h"
67
68 #include "amd_shared.h"
69 #include "amdgpu_mode.h"
70 #include "amdgpu_ih.h"
71 #include "amdgpu_irq.h"
72 #include "amdgpu_ucode.h"
73 #include "amdgpu_ttm.h"
74 #include "amdgpu_psp.h"
75 #include "amdgpu_gds.h"
76 #include "amdgpu_sync.h"
77 #include "amdgpu_ring.h"
78 #include "amdgpu_vm.h"
79 #include "amdgpu_dpm.h"
80 #include "amdgpu_acp.h"
81 #include "amdgpu_uvd.h"
82 #include "amdgpu_vce.h"
83 #include "amdgpu_vcn.h"
84 #include "amdgpu_jpeg.h"
85 #include "amdgpu_mn.h"
86 #include "amdgpu_gmc.h"
87 #include "amdgpu_gfx.h"
88 #include "amdgpu_sdma.h"
89 #include "amdgpu_lsdma.h"
90 #include "amdgpu_nbio.h"
91 #include "amdgpu_hdp.h"
92 #include "amdgpu_dm.h"
93 #include "amdgpu_virt.h"
94 #include "amdgpu_csa.h"
95 #include "amdgpu_mes_ctx.h"
96 #include "amdgpu_gart.h"
97 #include "amdgpu_debugfs.h"
98 #include "amdgpu_job.h"
99 #include "amdgpu_bo_list.h"
100 #include "amdgpu_gem.h"
101 #include "amdgpu_doorbell.h"
102 #include "amdgpu_amdkfd.h"
103 #include "amdgpu_discovery.h"
104 #include "amdgpu_mes.h"
105 #include "amdgpu_umc.h"
106 #include "amdgpu_mmhub.h"
107 #include "amdgpu_gfxhub.h"
108 #include "amdgpu_df.h"
109 #include "amdgpu_smuio.h"
110 #include "amdgpu_fdinfo.h"
111 #include "amdgpu_mca.h"
112 #include "amdgpu_ras.h"
113
114 #define MAX_GPU_INSTANCE 16
115
116 struct amdgpu_gpu_instance
117 {
118 struct amdgpu_device *adev;
119 int mgpu_fan_enabled;
120 };
121
122 struct amdgpu_mgpu_info
123 {
124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
125 struct mutex mutex;
126 uint32_t num_gpu;
127 uint32_t num_dgpu;
128 uint32_t num_apu;
129
130 /* delayed reset_func for XGMI configuration if necessary */
131 struct delayed_work delayed_reset_work;
132 bool pending_reset;
133 };
134
135 enum amdgpu_ss {
136 AMDGPU_SS_DRV_LOAD,
137 AMDGPU_SS_DEV_D0,
138 AMDGPU_SS_DEV_D3,
139 AMDGPU_SS_DRV_UNLOAD
140 };
141
142 struct amdgpu_watchdog_timer
143 {
144 bool timeout_fatal_disable;
145 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
146 };
147
148 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
149
150 /*
151 * Modules parameters.
152 */
153 extern int amdgpu_modeset;
154 extern int amdgpu_vram_limit;
155 extern int amdgpu_vis_vram_limit;
156 extern int amdgpu_gart_size;
157 extern int amdgpu_gtt_size;
158 extern int amdgpu_moverate;
159 extern int amdgpu_audio;
160 extern int amdgpu_disp_priority;
161 extern int amdgpu_hw_i2c;
162 extern int amdgpu_pcie_gen2;
163 extern int amdgpu_msi;
164 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
165 extern int amdgpu_dpm;
166 extern int amdgpu_fw_load_type;
167 extern int amdgpu_aspm;
168 extern int amdgpu_runtime_pm;
169 extern uint amdgpu_ip_block_mask;
170 extern int amdgpu_bapm;
171 extern int amdgpu_deep_color;
172 extern int amdgpu_vm_size;
173 extern int amdgpu_vm_block_size;
174 extern int amdgpu_vm_fragment_size;
175 extern int amdgpu_vm_fault_stop;
176 extern int amdgpu_vm_debug;
177 extern int amdgpu_vm_update_mode;
178 extern int amdgpu_exp_hw_support;
179 extern int amdgpu_dc;
180 extern int amdgpu_sched_jobs;
181 extern int amdgpu_sched_hw_submission;
182 extern uint amdgpu_pcie_gen_cap;
183 extern uint amdgpu_pcie_lane_cap;
184 extern u64 amdgpu_cg_mask;
185 extern uint amdgpu_pg_mask;
186 extern uint amdgpu_sdma_phase_quantum;
187 extern char *amdgpu_disable_cu;
188 extern char *amdgpu_virtual_display;
189 extern uint amdgpu_pp_feature_mask;
190 extern uint amdgpu_force_long_training;
191 extern int amdgpu_job_hang_limit;
192 extern int amdgpu_lbpw;
193 extern int amdgpu_compute_multipipe;
194 extern int amdgpu_gpu_recovery;
195 extern int amdgpu_emu_mode;
196 extern uint amdgpu_smu_memory_pool_size;
197 extern int amdgpu_smu_pptable_id;
198 extern uint amdgpu_dc_feature_mask;
199 extern uint amdgpu_freesync_vid_mode;
200 extern uint amdgpu_dc_debug_mask;
201 extern uint amdgpu_dc_visual_confirm;
202 extern uint amdgpu_dm_abm_level;
203 extern int amdgpu_backlight;
204 extern struct amdgpu_mgpu_info mgpu_info;
205 extern int amdgpu_ras_enable;
206 extern uint amdgpu_ras_mask;
207 extern int amdgpu_bad_page_threshold;
208 extern bool amdgpu_ignore_bad_page_threshold;
209 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
210 extern int amdgpu_async_gfx_ring;
211 extern int amdgpu_mcbp;
212 extern int amdgpu_discovery;
213 extern int amdgpu_mes;
214 extern int amdgpu_mes_kiq;
215 extern int amdgpu_noretry;
216 extern int amdgpu_force_asic_type;
217 extern int amdgpu_smartshift_bias;
218 extern int amdgpu_use_xgmi_p2p;
219 #ifdef CONFIG_HSA_AMD
220 extern int sched_policy;
221 extern bool debug_evictions;
222 extern bool no_system_mem_limit;
223 #else
224 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
225 static const bool __maybe_unused debug_evictions; /* = false */
226 static const bool __maybe_unused no_system_mem_limit;
227 #endif
228 #ifdef CONFIG_HSA_AMD_P2P
229 extern bool pcie_p2p;
230 #endif
231
232 extern int amdgpu_tmz;
233 extern int amdgpu_reset_method;
234
235 #ifdef CONFIG_DRM_AMDGPU_SI
236 extern int amdgpu_si_support;
237 #endif
238 #ifdef CONFIG_DRM_AMDGPU_CIK
239 extern int amdgpu_cik_support;
240 #endif
241 extern int amdgpu_num_kcq;
242
243 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
244 extern int amdgpu_vcnfw_log;
245 extern int amdgpu_sg_display;
246
247 #define AMDGPU_VM_MAX_NUM_CTX 4096
248 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
249 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
250 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
251 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
252 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
253 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
254 #define AMDGPUFB_CONN_LIMIT 4
255 #define AMDGPU_BIOS_NUM_SCRATCH 16
256
257 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
258
259 /* hard reset data */
260 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
261
262 /* reset flags */
263 #define AMDGPU_RESET_GFX (1 << 0)
264 #define AMDGPU_RESET_COMPUTE (1 << 1)
265 #define AMDGPU_RESET_DMA (1 << 2)
266 #define AMDGPU_RESET_CP (1 << 3)
267 #define AMDGPU_RESET_GRBM (1 << 4)
268 #define AMDGPU_RESET_DMA1 (1 << 5)
269 #define AMDGPU_RESET_RLC (1 << 6)
270 #define AMDGPU_RESET_SEM (1 << 7)
271 #define AMDGPU_RESET_IH (1 << 8)
272 #define AMDGPU_RESET_VMC (1 << 9)
273 #define AMDGPU_RESET_MC (1 << 10)
274 #define AMDGPU_RESET_DISPLAY (1 << 11)
275 #define AMDGPU_RESET_UVD (1 << 12)
276 #define AMDGPU_RESET_VCE (1 << 13)
277 #define AMDGPU_RESET_VCE1 (1 << 14)
278
279 /* max cursor sizes (in pixels) */
280 #define CIK_CURSOR_WIDTH 128
281 #define CIK_CURSOR_HEIGHT 128
282
283 /* smart shift bias level limits */
284 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
285 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
286
287 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
288 #define AMDGPU_SWCTF_EXTRA_DELAY 50
289
290 struct amdgpu_device;
291 struct amdgpu_irq_src;
292 struct amdgpu_fpriv;
293 struct amdgpu_bo_va_mapping;
294 struct kfd_vm_fault_info;
295 struct amdgpu_hive_info;
296 struct amdgpu_reset_context;
297 struct amdgpu_reset_control;
298
299 enum amdgpu_cp_irq {
300 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
301 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
305 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
309 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
310
311 AMDGPU_CP_IRQ_LAST
312 };
313
314 enum amdgpu_thermal_irq {
315 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
316 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
317
318 AMDGPU_THERMAL_IRQ_LAST
319 };
320
321 enum amdgpu_kiq_irq {
322 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
323 AMDGPU_CP_KIQ_IRQ_LAST
324 };
325 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
326 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
327 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
328 #define MAX_KIQ_REG_TRY 1000
329
330 int amdgpu_device_ip_set_clockgating_state(void *dev,
331 enum amd_ip_block_type block_type,
332 enum amd_clockgating_state state);
333 int amdgpu_device_ip_set_powergating_state(void *dev,
334 enum amd_ip_block_type block_type,
335 enum amd_powergating_state state);
336 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
337 u64 *flags);
338 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
339 enum amd_ip_block_type block_type);
340 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
341 enum amd_ip_block_type block_type);
342
343 #define AMDGPU_MAX_IP_NUM 16
344
345 struct amdgpu_ip_block_status {
346 bool valid;
347 bool sw;
348 bool hw;
349 bool late_initialized;
350 bool hang;
351 };
352
353 struct amdgpu_ip_block_version {
354 const enum amd_ip_block_type type;
355 const u32 major;
356 const u32 minor;
357 const u32 rev;
358 const struct amd_ip_funcs *funcs;
359 };
360
361 #define HW_REV(_Major, _Minor, _Rev) \
362 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
363
364 struct amdgpu_ip_block {
365 struct amdgpu_ip_block_status status;
366 const struct amdgpu_ip_block_version *version;
367 };
368
369 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
370 enum amd_ip_block_type type,
371 u32 major, u32 minor);
372
373 struct amdgpu_ip_block *
374 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
375 enum amd_ip_block_type type);
376
377 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
378 const struct amdgpu_ip_block_version *ip_block_version);
379
380 /*
381 * BIOS.
382 */
383 bool amdgpu_get_bios(struct amdgpu_device *adev);
384 bool amdgpu_read_bios(struct amdgpu_device *adev);
385 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
386 u8 *bios, u32 length_bytes);
387 /*
388 * Clocks
389 */
390
391 #define AMDGPU_MAX_PPLL 3
392
393 struct amdgpu_clock {
394 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
395 struct amdgpu_pll spll;
396 struct amdgpu_pll mpll;
397 /* 10 Khz units */
398 uint32_t default_mclk;
399 uint32_t default_sclk;
400 uint32_t default_dispclk;
401 uint32_t current_dispclk;
402 uint32_t dp_extclk;
403 uint32_t max_pixel_clock;
404 };
405
406 /* sub-allocation manager, it has to be protected by another lock.
407 * By conception this is an helper for other part of the driver
408 * like the indirect buffer or semaphore, which both have their
409 * locking.
410 *
411 * Principe is simple, we keep a list of sub allocation in offset
412 * order (first entry has offset == 0, last entry has the highest
413 * offset).
414 *
415 * When allocating new object we first check if there is room at
416 * the end total_size - (last_object_offset + last_object_size) >=
417 * alloc_size. If so we allocate new object there.
418 *
419 * When there is not enough room at the end, we start waiting for
420 * each sub object until we reach object_offset+object_size >=
421 * alloc_size, this object then become the sub object we return.
422 *
423 * Alignment can't be bigger than page size.
424 *
425 * Hole are not considered for allocation to keep things simple.
426 * Assumption is that there won't be hole (all object on same
427 * alignment).
428 */
429
430 #define AMDGPU_SA_NUM_FENCE_LISTS 32
431
432 struct amdgpu_sa_manager {
433 wait_queue_head_t wq;
434 struct amdgpu_bo *bo;
435 struct list_head *hole;
436 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
437 struct list_head olist;
438 unsigned size;
439 uint64_t gpu_addr;
440 void *cpu_ptr;
441 uint32_t domain;
442 uint32_t align;
443 };
444
445 /* sub-allocation buffer */
446 struct amdgpu_sa_bo {
447 struct list_head olist;
448 struct list_head flist;
449 struct amdgpu_sa_manager *manager;
450 unsigned soffset;
451 unsigned eoffset;
452 struct dma_fence *fence;
453 };
454
455 int amdgpu_fence_slab_init(void);
456 void amdgpu_fence_slab_fini(void);
457
458 /*
459 * IRQS.
460 */
461
462 struct amdgpu_flip_work {
463 struct delayed_work flip_work;
464 struct work_struct unpin_work;
465 struct amdgpu_device *adev;
466 int crtc_id;
467 u32 target_vblank;
468 uint64_t base;
469 struct drm_pending_vblank_event *event;
470 struct amdgpu_bo *old_abo;
471 unsigned shared_count;
472 struct dma_fence **shared;
473 struct dma_fence_cb cb;
474 bool async;
475 };
476
477
478 /*
479 * file private structure
480 */
481
482 struct amdgpu_fpriv {
483 struct amdgpu_vm vm;
484 struct amdgpu_bo_va *prt_va;
485 struct amdgpu_bo_va *csa_va;
486 struct mutex bo_list_lock;
487 struct idr bo_list_handles;
488 struct amdgpu_ctx_mgr ctx_mgr;
489 };
490
491 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
492
493 /*
494 * Writeback
495 */
496 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
497
498 struct amdgpu_wb {
499 struct amdgpu_bo *wb_obj;
500 volatile uint32_t *wb;
501 uint64_t gpu_addr;
502 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
503 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
504 };
505
506 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
507 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
508
509 /*
510 * Benchmarking
511 */
512 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
513
514 /*
515 * ASIC specific register table accessible by UMD
516 */
517 struct amdgpu_allowed_register_entry {
518 uint32_t reg_offset;
519 bool grbm_indexed;
520 };
521
522 enum amd_reset_method {
523 AMD_RESET_METHOD_NONE = -1,
524 AMD_RESET_METHOD_LEGACY = 0,
525 AMD_RESET_METHOD_MODE0,
526 AMD_RESET_METHOD_MODE1,
527 AMD_RESET_METHOD_MODE2,
528 AMD_RESET_METHOD_BACO,
529 AMD_RESET_METHOD_PCI,
530 };
531
532 struct amdgpu_video_codec_info {
533 u32 codec_type;
534 u32 max_width;
535 u32 max_height;
536 u32 max_pixels_per_frame;
537 u32 max_level;
538 };
539
540 #define codec_info_build(type, width, height, level) \
541 .codec_type = type,\
542 .max_width = width,\
543 .max_height = height,\
544 .max_pixels_per_frame = height * width,\
545 .max_level = level,
546
547 struct amdgpu_video_codecs {
548 const u32 codec_count;
549 const struct amdgpu_video_codec_info *codec_array;
550 };
551
552 /*
553 * ASIC specific functions.
554 */
555 struct amdgpu_asic_funcs {
556 bool (*read_disabled_bios)(struct amdgpu_device *adev);
557 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
558 u8 *bios, u32 length_bytes);
559 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
560 u32 sh_num, u32 reg_offset, u32 *value);
561 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
562 int (*reset)(struct amdgpu_device *adev);
563 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
564 /* get the reference clock */
565 u32 (*get_xclk)(struct amdgpu_device *adev);
566 /* MM block clocks */
567 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
568 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
569 /* static power management */
570 int (*get_pcie_lanes)(struct amdgpu_device *adev);
571 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
572 /* get config memsize register */
573 u32 (*get_config_memsize)(struct amdgpu_device *adev);
574 /* flush hdp write queue */
575 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
576 /* invalidate hdp read cache */
577 void (*invalidate_hdp)(struct amdgpu_device *adev,
578 struct amdgpu_ring *ring);
579 /* check if the asic needs a full reset of if soft reset will work */
580 bool (*need_full_reset)(struct amdgpu_device *adev);
581 /* initialize doorbell layout for specific asic*/
582 void (*init_doorbell_index)(struct amdgpu_device *adev);
583 /* PCIe bandwidth usage */
584 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
585 uint64_t *count1);
586 /* do we need to reset the asic at init time (e.g., kexec) */
587 bool (*need_reset_on_init)(struct amdgpu_device *adev);
588 /* PCIe replay counter */
589 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
590 /* device supports BACO */
591 bool (*supports_baco)(struct amdgpu_device *adev);
592 /* pre asic_init quirks */
593 void (*pre_asic_init)(struct amdgpu_device *adev);
594 /* enter/exit umd stable pstate */
595 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
596 /* query video codecs */
597 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
598 const struct amdgpu_video_codecs **codecs);
599 };
600
601 /*
602 * IOCTL.
603 */
604 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *filp);
606
607 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
608 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *filp);
610 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
611 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
612 struct drm_file *filp);
613
614 /* VRAM scratch page for HDP bug, default vram page */
615 struct amdgpu_vram_scratch {
616 struct amdgpu_bo *robj;
617 volatile uint32_t *ptr;
618 u64 gpu_addr;
619 };
620
621 /*
622 * CGS
623 */
624 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
625 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
626
627 /*
628 * Core structure, functions and helpers.
629 */
630 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
631 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
632
633 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
634 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
635
636 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
637 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
638
639 struct amdgpu_mmio_remap {
640 u32 reg_offset;
641 resource_size_t bus_addr;
642 };
643
644 /* Define the HW IP blocks will be used in driver , add more if necessary */
645 enum amd_hw_ip_block_type {
646 GC_HWIP = 1,
647 HDP_HWIP,
648 SDMA0_HWIP,
649 SDMA1_HWIP,
650 SDMA2_HWIP,
651 SDMA3_HWIP,
652 SDMA4_HWIP,
653 SDMA5_HWIP,
654 SDMA6_HWIP,
655 SDMA7_HWIP,
656 LSDMA_HWIP,
657 MMHUB_HWIP,
658 ATHUB_HWIP,
659 NBIO_HWIP,
660 MP0_HWIP,
661 MP1_HWIP,
662 UVD_HWIP,
663 VCN_HWIP = UVD_HWIP,
664 JPEG_HWIP = VCN_HWIP,
665 VCN1_HWIP,
666 VCE_HWIP,
667 DF_HWIP,
668 DCE_HWIP,
669 OSSSYS_HWIP,
670 SMUIO_HWIP,
671 PWR_HWIP,
672 NBIF_HWIP,
673 THM_HWIP,
674 CLK_HWIP,
675 UMC_HWIP,
676 RSMU_HWIP,
677 XGMI_HWIP,
678 DCI_HWIP,
679 PCIE_HWIP,
680 MAX_HWIP
681 };
682
683 #define HWIP_MAX_INSTANCE 11
684
685 #define HW_ID_MAX 300
686 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
687 #define IP_VERSION_MAJ(ver) ((ver) >> 16)
688 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
689 #define IP_VERSION_REV(ver) ((ver) & 0xFF)
690
691 struct amd_powerplay {
692 void *pp_handle;
693 const struct amd_pm_funcs *pp_funcs;
694 };
695
696 struct ip_discovery_top;
697
698 /* polaris10 kickers */
699 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
700 ((rid == 0xE3) || \
701 (rid == 0xE4) || \
702 (rid == 0xE5) || \
703 (rid == 0xE7) || \
704 (rid == 0xEF))) || \
705 ((did == 0x6FDF) && \
706 ((rid == 0xE7) || \
707 (rid == 0xEF) || \
708 (rid == 0xFF))))
709
710 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
711 ((rid == 0xE1) || \
712 (rid == 0xF7)))
713
714 /* polaris11 kickers */
715 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
716 ((rid == 0xE0) || \
717 (rid == 0xE5))) || \
718 ((did == 0x67FF) && \
719 ((rid == 0xCF) || \
720 (rid == 0xEF) || \
721 (rid == 0xFF))))
722
723 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
724 ((rid == 0xE2)))
725
726 /* polaris12 kickers */
727 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
728 ((rid == 0xC0) || \
729 (rid == 0xC1) || \
730 (rid == 0xC3) || \
731 (rid == 0xC7))) || \
732 ((did == 0x6981) && \
733 ((rid == 0x00) || \
734 (rid == 0x01) || \
735 (rid == 0x10))))
736
737 struct amdgpu_mqd_prop {
738 uint64_t mqd_gpu_addr;
739 uint64_t hqd_base_gpu_addr;
740 uint64_t rptr_gpu_addr;
741 uint64_t wptr_gpu_addr;
742 uint32_t queue_size;
743 bool use_doorbell;
744 uint32_t doorbell_index;
745 uint64_t eop_gpu_addr;
746 uint32_t hqd_pipe_priority;
747 uint32_t hqd_queue_priority;
748 bool hqd_active;
749 };
750
751 struct amdgpu_mqd {
752 unsigned mqd_size;
753 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
754 struct amdgpu_mqd_prop *p);
755 };
756
757 #define AMDGPU_RESET_MAGIC_NUM 64
758 #define AMDGPU_MAX_DF_PERFMONS 4
759 #define AMDGPU_PRODUCT_NAME_LEN 64
760 struct amdgpu_reset_domain;
761
762 struct amdgpu_device {
763 struct device *dev;
764 struct pci_dev *pdev;
765 struct drm_device ddev;
766
767 #ifdef CONFIG_DRM_AMD_ACP
768 struct amdgpu_acp acp;
769 #endif
770 struct amdgpu_hive_info *hive;
771 /* ASIC */
772 enum amd_asic_type asic_type;
773 uint32_t family;
774 uint32_t rev_id;
775 uint32_t external_rev_id;
776 unsigned long flags;
777 unsigned long apu_flags;
778 int usec_timeout;
779 const struct amdgpu_asic_funcs *asic_funcs;
780 bool shutdown;
781 bool need_swiotlb;
782 bool accel_working;
783 struct notifier_block acpi_nb;
784 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
785 struct debugfs_blob_wrapper debugfs_vbios_blob;
786 struct debugfs_blob_wrapper debugfs_discovery_blob;
787 struct mutex srbm_mutex;
788 /* GRBM index mutex. Protects concurrent access to GRBM index */
789 struct mutex grbm_idx_mutex;
790 struct dev_pm_domain vga_pm_domain;
791 bool have_disp_power_ref;
792 bool have_atomics_support;
793
794 /* BIOS */
795 bool is_atom_fw;
796 uint8_t *bios;
797 uint32_t bios_size;
798 uint32_t bios_scratch_reg_offset;
799 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
800
801 /* Register/doorbell mmio */
802 resource_size_t rmmio_base;
803 resource_size_t rmmio_size;
804 void __iomem *rmmio;
805 /* protects concurrent MM_INDEX/DATA based register access */
806 spinlock_t mmio_idx_lock;
807 struct amdgpu_mmio_remap rmmio_remap;
808 /* protects concurrent SMC based register access */
809 spinlock_t smc_idx_lock;
810 amdgpu_rreg_t smc_rreg;
811 amdgpu_wreg_t smc_wreg;
812 /* protects concurrent PCIE register access */
813 spinlock_t pcie_idx_lock;
814 amdgpu_rreg_t pcie_rreg;
815 amdgpu_wreg_t pcie_wreg;
816 amdgpu_rreg_t pciep_rreg;
817 amdgpu_wreg_t pciep_wreg;
818 amdgpu_rreg64_t pcie_rreg64;
819 amdgpu_wreg64_t pcie_wreg64;
820 /* protects concurrent UVD register access */
821 spinlock_t uvd_ctx_idx_lock;
822 amdgpu_rreg_t uvd_ctx_rreg;
823 amdgpu_wreg_t uvd_ctx_wreg;
824 /* protects concurrent DIDT register access */
825 spinlock_t didt_idx_lock;
826 amdgpu_rreg_t didt_rreg;
827 amdgpu_wreg_t didt_wreg;
828 /* protects concurrent gc_cac register access */
829 spinlock_t gc_cac_idx_lock;
830 amdgpu_rreg_t gc_cac_rreg;
831 amdgpu_wreg_t gc_cac_wreg;
832 /* protects concurrent se_cac register access */
833 spinlock_t se_cac_idx_lock;
834 amdgpu_rreg_t se_cac_rreg;
835 amdgpu_wreg_t se_cac_wreg;
836 /* protects concurrent ENDPOINT (audio) register access */
837 spinlock_t audio_endpt_idx_lock;
838 amdgpu_block_rreg_t audio_endpt_rreg;
839 amdgpu_block_wreg_t audio_endpt_wreg;
840 struct amdgpu_doorbell doorbell;
841
842 /* clock/pll info */
843 struct amdgpu_clock clock;
844
845 /* MC */
846 struct amdgpu_gmc gmc;
847 struct amdgpu_gart gart;
848 dma_addr_t dummy_page_addr;
849 struct amdgpu_vm_manager vm_manager;
850 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
851 unsigned num_vmhubs;
852
853 /* memory management */
854 struct amdgpu_mman mman;
855 struct amdgpu_vram_scratch vram_scratch;
856 struct amdgpu_wb wb;
857 atomic64_t num_bytes_moved;
858 atomic64_t num_evictions;
859 atomic64_t num_vram_cpu_page_faults;
860 atomic_t gpu_reset_counter;
861 atomic_t vram_lost_counter;
862
863 /* data for buffer migration throttling */
864 struct {
865 spinlock_t lock;
866 s64 last_update_us;
867 s64 accum_us; /* accumulated microseconds */
868 s64 accum_us_vis; /* for visible VRAM */
869 u32 log2_max_MBps;
870 } mm_stats;
871
872 /* display */
873 bool enable_virtual_display;
874 struct amdgpu_vkms_output *amdgpu_vkms_output;
875 struct amdgpu_mode_info mode_info;
876 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
877 struct work_struct hotplug_work;
878 struct amdgpu_irq_src crtc_irq;
879 struct amdgpu_irq_src vline0_irq;
880 struct amdgpu_irq_src vupdate_irq;
881 struct amdgpu_irq_src pageflip_irq;
882 struct amdgpu_irq_src hpd_irq;
883 struct amdgpu_irq_src dmub_trace_irq;
884 struct amdgpu_irq_src dmub_outbox_irq;
885
886 /* rings */
887 u64 fence_context;
888 unsigned num_rings;
889 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
890 struct dma_fence __rcu *gang_submit;
891 bool ib_pool_ready;
892 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
893 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
894
895 /* interrupts */
896 struct amdgpu_irq irq;
897
898 /* powerplay */
899 struct amd_powerplay powerplay;
900 struct amdgpu_pm pm;
901 u64 cg_flags;
902 u32 pg_flags;
903
904 /* nbio */
905 struct amdgpu_nbio nbio;
906
907 /* hdp */
908 struct amdgpu_hdp hdp;
909
910 /* smuio */
911 struct amdgpu_smuio smuio;
912
913 /* mmhub */
914 struct amdgpu_mmhub mmhub;
915
916 /* gfxhub */
917 struct amdgpu_gfxhub gfxhub;
918
919 /* gfx */
920 struct amdgpu_gfx gfx;
921
922 /* sdma */
923 struct amdgpu_sdma sdma;
924
925 /* lsdma */
926 struct amdgpu_lsdma lsdma;
927
928 /* uvd */
929 struct amdgpu_uvd uvd;
930
931 /* vce */
932 struct amdgpu_vce vce;
933
934 /* vcn */
935 struct amdgpu_vcn vcn;
936
937 /* jpeg */
938 struct amdgpu_jpeg jpeg;
939
940 /* firmwares */
941 struct amdgpu_firmware firmware;
942
943 /* PSP */
944 struct psp_context psp;
945
946 /* GDS */
947 struct amdgpu_gds gds;
948
949 /* KFD */
950 struct amdgpu_kfd_dev kfd;
951
952 /* UMC */
953 struct amdgpu_umc umc;
954
955 /* display related functionality */
956 struct amdgpu_display_manager dm;
957
958 /* mes */
959 bool enable_mes;
960 bool enable_mes_kiq;
961 struct amdgpu_mes mes;
962 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
963
964 /* df */
965 struct amdgpu_df df;
966
967 /* MCA */
968 struct amdgpu_mca mca;
969
970 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
971 uint32_t harvest_ip_mask;
972 int num_ip_blocks;
973 struct mutex mn_lock;
974 DECLARE_HASHTABLE(mn_hash, 7);
975
976 /* tracking pinned memory */
977 atomic64_t vram_pin_size;
978 atomic64_t visible_pin_size;
979 atomic64_t gart_pin_size;
980
981 /* soc15 register offset based on ip, instance and segment */
982 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
983
984 /* delayed work_func for deferring clockgating during resume */
985 struct delayed_work delayed_init_work;
986
987 struct amdgpu_virt virt;
988
989 /* link all shadow bo */
990 struct list_head shadow_list;
991 struct mutex shadow_list_lock;
992
993 /* record hw reset is performed */
994 bool has_hw_reset;
995 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
996
997 /* s3/s4 mask */
998 bool in_suspend;
999 bool in_s3;
1000 bool in_s4;
1001 bool in_s0ix;
1002 /* indicate amdgpu suspension status */
1003 bool suspend_complete;
1004
1005 enum pp_mp1_state mp1_state;
1006 struct amdgpu_doorbell_index doorbell_index;
1007
1008 struct mutex notifier_lock;
1009
1010 int asic_reset_res;
1011 struct work_struct xgmi_reset_work;
1012 struct list_head reset_list;
1013
1014 long gfx_timeout;
1015 long sdma_timeout;
1016 long video_timeout;
1017 long compute_timeout;
1018
1019 uint64_t unique_id;
1020 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1021
1022 /* enable runtime pm on the device */
1023 bool in_runpm;
1024 bool has_pr3;
1025
1026 bool pm_sysfs_en;
1027 bool ucode_sysfs_en;
1028 bool psp_sysfs_en;
1029
1030 /* Chip product information */
1031 char product_number[20];
1032 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1033 char serial[20];
1034
1035 atomic_t throttling_logging_enabled;
1036 struct ratelimit_state throttling_logging_rs;
1037 uint32_t ras_hw_enabled;
1038 uint32_t ras_enabled;
1039
1040 bool no_hw_access;
1041 struct pci_saved_state *pci_state;
1042 pci_channel_state_t pci_channel_state;
1043
1044 struct amdgpu_reset_control *reset_cntl;
1045 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1046
1047 bool ram_is_direct_mapped;
1048
1049 struct list_head ras_list;
1050
1051 struct ip_discovery_top *ip_top;
1052
1053 struct amdgpu_reset_domain *reset_domain;
1054
1055 struct mutex benchmark_mutex;
1056
1057 /* reset dump register */
1058 uint32_t *reset_dump_reg_list;
1059 uint32_t *reset_dump_reg_value;
1060 int num_regs;
1061 #ifdef CONFIG_DEV_COREDUMP
1062 struct amdgpu_task_info reset_task_info;
1063 bool reset_vram_lost;
1064 struct timespec64 reset_time;
1065 #endif
1066
1067 bool scpm_enabled;
1068 uint32_t scpm_status;
1069
1070 struct work_struct reset_work;
1071
1072 bool job_hang;
1073 };
1074
drm_to_adev(struct drm_device * ddev)1075 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1076 {
1077 return container_of(ddev, struct amdgpu_device, ddev);
1078 }
1079
adev_to_drm(struct amdgpu_device * adev)1080 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1081 {
1082 return &adev->ddev;
1083 }
1084
amdgpu_ttm_adev(struct ttm_device * bdev)1085 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1086 {
1087 return container_of(bdev, struct amdgpu_device, mman.bdev);
1088 }
1089
1090 int amdgpu_device_init(struct amdgpu_device *adev,
1091 uint32_t flags);
1092 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1093 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1094
1095 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1096
1097 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1098 void *buf, size_t size, bool write);
1099 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1100 void *buf, size_t size, bool write);
1101
1102 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1103 void *buf, size_t size, bool write);
1104 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1105 uint32_t reg, uint32_t acc_flags);
1106 void amdgpu_device_wreg(struct amdgpu_device *adev,
1107 uint32_t reg, uint32_t v,
1108 uint32_t acc_flags);
1109 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1110 uint32_t reg, uint32_t v);
1111 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1112 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1113
1114 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1115 u32 pcie_index, u32 pcie_data,
1116 u32 reg_addr);
1117 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1118 u32 pcie_index, u32 pcie_data,
1119 u32 reg_addr);
1120 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1121 u32 pcie_index, u32 pcie_data,
1122 u32 reg_addr, u32 reg_data);
1123 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1124 u32 pcie_index, u32 pcie_data,
1125 u32 reg_addr, u64 reg_data);
1126
1127 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1128 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1129
1130 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1131 struct amdgpu_reset_context *reset_context);
1132
1133 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1134 struct amdgpu_reset_context *reset_context);
1135
1136 int emu_soc_asic_init(struct amdgpu_device *adev);
1137
1138 /*
1139 * Registers read & write functions.
1140 */
1141 #define AMDGPU_REGS_NO_KIQ (1<<1)
1142 #define AMDGPU_REGS_RLC (1<<2)
1143
1144 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1145 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1146
1147 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1148 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1149
1150 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1151 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1152
1153 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1154 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1155 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1156 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1157 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1158 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1159 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1160 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1161 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1162 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1163 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1164 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1165 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1166 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1167 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1168 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1169 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1170 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1171 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1172 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1173 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1174 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1175 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1176 #define WREG32_P(reg, val, mask) \
1177 do { \
1178 uint32_t tmp_ = RREG32(reg); \
1179 tmp_ &= (mask); \
1180 tmp_ |= ((val) & ~(mask)); \
1181 WREG32(reg, tmp_); \
1182 } while (0)
1183 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1184 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1185 #define WREG32_PLL_P(reg, val, mask) \
1186 do { \
1187 uint32_t tmp_ = RREG32_PLL(reg); \
1188 tmp_ &= (mask); \
1189 tmp_ |= ((val) & ~(mask)); \
1190 WREG32_PLL(reg, tmp_); \
1191 } while (0)
1192
1193 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1194 do { \
1195 u32 tmp = RREG32_SMC(_Reg); \
1196 tmp &= (_Mask); \
1197 tmp |= ((_Val) & ~(_Mask)); \
1198 WREG32_SMC(_Reg, tmp); \
1199 } while (0)
1200
1201 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1202
1203 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1204 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1205
1206 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1207 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1208 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1209
1210 #define REG_GET_FIELD(value, reg, field) \
1211 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1212
1213 #define WREG32_FIELD(reg, field, val) \
1214 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1215
1216 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1217 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1218
1219 /*
1220 * BIOS helpers.
1221 */
1222 #define RBIOS8(i) (adev->bios[i])
1223 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1224 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1225
1226 /*
1227 * ASICs macro.
1228 */
1229 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1230 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1231 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1232 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1233 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1234 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1235 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1236 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1237 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1238 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1239 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1240 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1241 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1242 #define amdgpu_asic_flush_hdp(adev, r) \
1243 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1244 #define amdgpu_asic_invalidate_hdp(adev, r) \
1245 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1246 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1247 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1248 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1249 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1250 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1251 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1252 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1253 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1254 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1255 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1256 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1257
1258 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1259
1260 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1261
1262 /* Common functions */
1263 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1264 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1265 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1266 struct amdgpu_job *job,
1267 struct amdgpu_reset_context *reset_context);
1268 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1269 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1270 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1271 bool amdgpu_device_pcie_dynamic_switching_supported(void);
1272 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1273 bool amdgpu_device_aspm_support_quirk(void);
1274
1275 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1276 u64 num_vis_bytes);
1277 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1278 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1279 const u32 *registers,
1280 const u32 array_size);
1281
1282 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1283 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1284 bool amdgpu_device_supports_px(struct drm_device *dev);
1285 bool amdgpu_device_supports_boco(struct drm_device *dev);
1286 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1287 bool amdgpu_device_supports_baco(struct drm_device *dev);
1288 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1289 struct amdgpu_device *peer_adev);
1290 int amdgpu_device_baco_enter(struct drm_device *dev);
1291 int amdgpu_device_baco_exit(struct drm_device *dev);
1292
1293 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1294 struct amdgpu_ring *ring);
1295 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1296 struct amdgpu_ring *ring);
1297
1298 void amdgpu_device_halt(struct amdgpu_device *adev);
1299 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1300 u32 reg);
1301 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1302 u32 reg, u32 v);
1303 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1304 struct dma_fence *gang);
1305 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1306
1307 /* atpx handler */
1308 #if defined(CONFIG_VGA_SWITCHEROO)
1309 void amdgpu_register_atpx_handler(void);
1310 void amdgpu_unregister_atpx_handler(void);
1311 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1312 bool amdgpu_is_atpx_hybrid(void);
1313 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1314 bool amdgpu_has_atpx(void);
1315 #else
amdgpu_register_atpx_handler(void)1316 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1317 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1318 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1319 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1320 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1321 static inline bool amdgpu_has_atpx(void) { return false; }
1322 #endif
1323
1324 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1325 void *amdgpu_atpx_get_dhandle(void);
1326 #else
amdgpu_atpx_get_dhandle(void)1327 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1328 #endif
1329
1330 /*
1331 * KMS
1332 */
1333 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1334 extern const int amdgpu_max_kms_ioctl;
1335
1336 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1337 void amdgpu_driver_unload_kms(struct drm_device *dev);
1338 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1339 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1340 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1341 struct drm_file *file_priv);
1342 void amdgpu_driver_release_kms(struct drm_device *dev);
1343
1344 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1345 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1346 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1347 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1348 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1349 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1350 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *filp);
1352
1353 /*
1354 * functions used by amdgpu_encoder.c
1355 */
1356 struct amdgpu_afmt_acr {
1357 u32 clock;
1358
1359 int n_32khz;
1360 int cts_32khz;
1361
1362 int n_44_1khz;
1363 int cts_44_1khz;
1364
1365 int n_48khz;
1366 int cts_48khz;
1367
1368 };
1369
1370 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1371
1372 /* amdgpu_acpi.c */
1373
1374 /* ATCS Device/Driver State */
1375 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1376 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1377 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1378 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1379
1380 #if defined(CONFIG_ACPI)
1381 int amdgpu_acpi_init(struct amdgpu_device *adev);
1382 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1383 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1384 bool amdgpu_acpi_is_power_shift_control_supported(void);
1385 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1386 u8 perf_req, bool advertise);
1387 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1388 u8 dev_state, bool drv_state);
1389 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1390 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1391
1392 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1393 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1394 void amdgpu_acpi_detect(void);
1395 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1396 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)1397 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
amdgpu_acpi_should_gpu_reset(struct amdgpu_device * adev)1398 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_detect(void)1399 static inline void amdgpu_acpi_detect(void) { }
amdgpu_acpi_is_power_shift_control_supported(void)1400 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
amdgpu_acpi_power_shift_control(struct amdgpu_device * adev,u8 dev_state,bool drv_state)1401 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1402 u8 dev_state, bool drv_state) { return 0; }
amdgpu_acpi_smart_shift_update(struct drm_device * dev,enum amdgpu_ss ss_state)1403 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1404 enum amdgpu_ss ss_state) { return 0; }
1405 #endif
1406
1407 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1408 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1409 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1410 #else
amdgpu_acpi_is_s0ix_active(struct amdgpu_device * adev)1411 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_is_s3_active(struct amdgpu_device * adev)1412 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1413 #endif
1414
1415 #if defined(CONFIG_DRM_AMD_DC)
1416 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1417 #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)1418 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1419 #endif
1420
1421
1422 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1423 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1424
1425 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1426 pci_channel_state_t state);
1427 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1428 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1429 void amdgpu_pci_resume(struct pci_dev *pdev);
1430
1431 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1432 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1433
1434 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1435
1436 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1437 enum amd_clockgating_state state);
1438 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1439 enum amd_powergating_state state);
1440
amdgpu_device_has_timeouts_enabled(struct amdgpu_device * adev)1441 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1442 {
1443 return amdgpu_gpu_recovery != 0 &&
1444 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1445 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1446 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1447 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1448 }
1449
1450 #include "amdgpu_object.h"
1451
amdgpu_is_tmz(struct amdgpu_device * adev)1452 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1453 {
1454 return adev->gmc.tmz_enabled;
1455 }
1456
1457 int amdgpu_in_reset(struct amdgpu_device *adev);
1458
1459 #endif
1460