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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Microchip KSZ8795 register definitions
4  *
5  * Copyright (c) 2017 Microchip Technology Inc.
6  *	Tristram Ha <Tristram.Ha@microchip.com>
7  */
8 
9 #ifndef __KSZ8795_REG_H
10 #define __KSZ8795_REG_H
11 
12 #define KS_PORT_M			0x1F
13 
14 #define KS_PRIO_M			0x3
15 #define KS_PRIO_S			2
16 
17 #define SW_REVISION_M			0x0E
18 #define SW_REVISION_S			1
19 
20 #define KSZ8863_REG_SW_RESET		0x43
21 
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET	BIT(4)
23 #define KSZ8863_PCS_RESET		BIT(0)
24 
25 #define REG_SW_CTRL_0			0x02
26 
27 #define SW_NEW_BACKOFF			BIT(7)
28 #define SW_GLOBAL_RESET			BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE		BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE		BIT(4)
31 #define SW_LINK_AUTO_AGING		BIT(0)
32 
33 #define REG_SW_CTRL_1			0x03
34 
35 #define SW_HUGE_PACKET			BIT(6)
36 #define SW_TX_FLOW_CTRL_DISABLE		BIT(5)
37 #define SW_RX_FLOW_CTRL_DISABLE		BIT(4)
38 #define SW_CHECK_LENGTH			BIT(3)
39 #define SW_AGING_ENABLE			BIT(2)
40 #define SW_FAST_AGING			BIT(1)
41 #define SW_AGGR_BACKOFF			BIT(0)
42 
43 #define REG_SW_CTRL_2			0x04
44 
45 #define UNICAST_VLAN_BOUNDARY		BIT(7)
46 #define SW_BACK_PRESSURE		BIT(5)
47 #define FAIR_FLOW_CTRL			BIT(4)
48 #define NO_EXC_COLLISION_DROP		BIT(3)
49 #define SW_LEGAL_PACKET_DISABLE		BIT(1)
50 
51 #define REG_SW_CTRL_3			0x05
52  #define WEIGHTED_FAIR_QUEUE_ENABLE	BIT(3)
53 
54 #define SW_VLAN_ENABLE			BIT(7)
55 #define SW_IGMP_SNOOP			BIT(6)
56 #define SW_MIRROR_RX_TX			BIT(0)
57 
58 #define REG_SW_CTRL_4			0x06
59 
60 #define SW_HALF_DUPLEX_FLOW_CTRL	BIT(7)
61 #define SW_HALF_DUPLEX			BIT(6)
62 #define SW_FLOW_CTRL			BIT(5)
63 #define SW_10_MBIT			BIT(4)
64 #define SW_REPLACE_VID			BIT(3)
65 
66 #define REG_SW_CTRL_5			0x07
67 
68 #define REG_SW_CTRL_6			0x08
69 
70 #define SW_MIB_COUNTER_FLUSH		BIT(7)
71 #define SW_MIB_COUNTER_FREEZE		BIT(6)
72 #define SW_MIB_COUNTER_CTRL_ENABLE	KS_PORT_M
73 
74 #define REG_SW_CTRL_9			0x0B
75 
76 #define SPI_CLK_125_MHZ			0x80
77 #define SPI_CLK_62_5_MHZ		0x40
78 #define SPI_CLK_31_25_MHZ		0x00
79 
80 #define SW_LED_MODE_M			0x3
81 #define SW_LED_MODE_S			4
82 #define SW_LED_LINK_ACT_SPEED		0
83 #define SW_LED_LINK_ACT			1
84 #define SW_LED_LINK_ACT_DUPLEX		2
85 #define SW_LED_LINK_DUPLEX		3
86 
87 #define REG_SW_CTRL_10			0x0C
88 
89 #define SW_PASS_PAUSE			BIT(0)
90 
91 #define REG_SW_CTRL_11			0x0D
92 
93 #define REG_POWER_MANAGEMENT_1		0x0E
94 
95 #define SW_PLL_POWER_DOWN		BIT(5)
96 #define SW_POWER_MANAGEMENT_MODE_M	0x3
97 #define SW_POWER_MANAGEMENT_MODE_S	3
98 #define SW_POWER_NORMAL			0
99 #define SW_ENERGY_DETECTION		1
100 #define SW_SOFTWARE_POWER_DOWN		2
101 
102 #define REG_POWER_MANAGEMENT_2		0x0F
103 
104 #define REG_PORT_1_CTRL_0		0x10
105 #define REG_PORT_2_CTRL_0		0x20
106 #define REG_PORT_3_CTRL_0		0x30
107 #define REG_PORT_4_CTRL_0		0x40
108 #define REG_PORT_5_CTRL_0		0x50
109 
110 #define PORT_BROADCAST_STORM		BIT(7)
111 #define PORT_DIFFSERV_ENABLE		BIT(6)
112 #define PORT_802_1P_ENABLE		BIT(5)
113 #define PORT_BASED_PRIO_S		3
114 #define PORT_BASED_PRIO_M		KS_PRIO_M
115 #define PORT_BASED_PRIO_0		0
116 #define PORT_BASED_PRIO_1		1
117 #define PORT_BASED_PRIO_2		2
118 #define PORT_BASED_PRIO_3		3
119 #define PORT_INSERT_TAG			BIT(2)
120 #define PORT_REMOVE_TAG			BIT(1)
121 #define PORT_QUEUE_SPLIT_L		BIT(0)
122 
123 #define REG_PORT_1_CTRL_1		0x11
124 #define REG_PORT_2_CTRL_1		0x21
125 #define REG_PORT_3_CTRL_1		0x31
126 #define REG_PORT_4_CTRL_1		0x41
127 #define REG_PORT_5_CTRL_1		0x51
128 
129 #define PORT_MIRROR_SNIFFER		BIT(7)
130 #define PORT_MIRROR_RX			BIT(6)
131 #define PORT_MIRROR_TX			BIT(5)
132 #define PORT_VLAN_MEMBERSHIP		KS_PORT_M
133 
134 #define REG_PORT_1_CTRL_2		0x12
135 #define REG_PORT_2_CTRL_2		0x22
136 #define REG_PORT_3_CTRL_2		0x32
137 #define REG_PORT_4_CTRL_2		0x42
138 #define REG_PORT_5_CTRL_2		0x52
139 
140 #define PORT_INGRESS_FILTER		BIT(6)
141 #define PORT_DISCARD_NON_VID		BIT(5)
142 #define PORT_FORCE_FLOW_CTRL		BIT(4)
143 #define PORT_BACK_PRESSURE		BIT(3)
144 
145 #define REG_PORT_1_CTRL_3		0x13
146 #define REG_PORT_2_CTRL_3		0x23
147 #define REG_PORT_3_CTRL_3		0x33
148 #define REG_PORT_4_CTRL_3		0x43
149 #define REG_PORT_5_CTRL_3		0x53
150 #define REG_PORT_1_CTRL_4		0x14
151 #define REG_PORT_2_CTRL_4		0x24
152 #define REG_PORT_3_CTRL_4		0x34
153 #define REG_PORT_4_CTRL_4		0x44
154 #define REG_PORT_5_CTRL_4		0x54
155 
156 #define PORT_DEFAULT_VID		0x0001
157 
158 #define REG_PORT_1_CTRL_5		0x15
159 #define REG_PORT_2_CTRL_5		0x25
160 #define REG_PORT_3_CTRL_5		0x35
161 #define REG_PORT_4_CTRL_5		0x45
162 #define REG_PORT_5_CTRL_5		0x55
163 
164 #define PORT_ACL_ENABLE			BIT(2)
165 #define PORT_AUTHEN_MODE		0x3
166 #define PORT_AUTHEN_PASS		0
167 #define PORT_AUTHEN_BLOCK		1
168 #define PORT_AUTHEN_TRAP		2
169 
170 #define REG_PORT_5_CTRL_6		0x56
171 
172 #define PORT_MII_INTERNAL_CLOCK		BIT(7)
173 #define PORT_GMII_MAC_MODE		BIT(2)
174 
175 #define REG_PORT_1_CTRL_7		0x17
176 #define REG_PORT_2_CTRL_7		0x27
177 #define REG_PORT_3_CTRL_7		0x37
178 #define REG_PORT_4_CTRL_7		0x47
179 
180 #define PORT_AUTO_NEG_ASYM_PAUSE	BIT(5)
181 #define PORT_AUTO_NEG_SYM_PAUSE		BIT(4)
182 #define PORT_AUTO_NEG_100BTX_FD		BIT(3)
183 #define PORT_AUTO_NEG_100BTX		BIT(2)
184 #define PORT_AUTO_NEG_10BT_FD		BIT(1)
185 #define PORT_AUTO_NEG_10BT		BIT(0)
186 
187 #define REG_PORT_1_STATUS_0		0x18
188 #define REG_PORT_2_STATUS_0		0x28
189 #define REG_PORT_3_STATUS_0		0x38
190 #define REG_PORT_4_STATUS_0		0x48
191 
192 /* For KSZ8765. */
193 #define PORT_REMOTE_ASYM_PAUSE		BIT(5)
194 #define PORT_REMOTE_SYM_PAUSE		BIT(4)
195 #define PORT_REMOTE_100BTX_FD		BIT(3)
196 #define PORT_REMOTE_100BTX		BIT(2)
197 #define PORT_REMOTE_10BT_FD		BIT(1)
198 #define PORT_REMOTE_10BT		BIT(0)
199 
200 #define REG_PORT_1_STATUS_1		0x19
201 #define REG_PORT_2_STATUS_1		0x29
202 #define REG_PORT_3_STATUS_1		0x39
203 #define REG_PORT_4_STATUS_1		0x49
204 
205 #define PORT_HP_MDIX			BIT(7)
206 #define PORT_REVERSED_POLARITY		BIT(5)
207 #define PORT_TX_FLOW_CTRL		BIT(4)
208 #define PORT_RX_FLOW_CTRL		BIT(3)
209 #define PORT_STAT_SPEED_100MBIT		BIT(2)
210 #define PORT_STAT_FULL_DUPLEX		BIT(1)
211 
212 #define PORT_REMOTE_FAULT		BIT(0)
213 
214 #define REG_PORT_1_LINK_MD_CTRL		0x1A
215 #define REG_PORT_2_LINK_MD_CTRL		0x2A
216 #define REG_PORT_3_LINK_MD_CTRL		0x3A
217 #define REG_PORT_4_LINK_MD_CTRL		0x4A
218 
219 #define PORT_CABLE_10M_SHORT		BIT(7)
220 #define PORT_CABLE_DIAG_RESULT_M	GENMASK(6, 5)
221 #define PORT_CABLE_DIAG_RESULT_S	5
222 #define PORT_CABLE_STAT_NORMAL		0
223 #define PORT_CABLE_STAT_OPEN		1
224 #define PORT_CABLE_STAT_SHORT		2
225 #define PORT_CABLE_STAT_FAILED		3
226 #define PORT_START_CABLE_DIAG		BIT(4)
227 #define PORT_FORCE_LINK			BIT(3)
228 #define PORT_POWER_SAVING		BIT(2)
229 #define PORT_PHY_REMOTE_LOOPBACK	BIT(1)
230 #define PORT_CABLE_FAULT_COUNTER_H	0x01
231 
232 #define REG_PORT_1_LINK_MD_RESULT	0x1B
233 #define REG_PORT_2_LINK_MD_RESULT	0x2B
234 #define REG_PORT_3_LINK_MD_RESULT	0x3B
235 #define REG_PORT_4_LINK_MD_RESULT	0x4B
236 
237 #define PORT_CABLE_FAULT_COUNTER_L	0xFF
238 #define PORT_CABLE_FAULT_COUNTER	0x1FF
239 
240 #define REG_PORT_1_CTRL_9		0x1C
241 #define REG_PORT_2_CTRL_9		0x2C
242 #define REG_PORT_3_CTRL_9		0x3C
243 #define REG_PORT_4_CTRL_9		0x4C
244 
245 #define PORT_AUTO_NEG_ENABLE		BIT(7)
246 #define PORT_AUTO_NEG_DISABLE		BIT(7)
247 #define PORT_FORCE_100_MBIT		BIT(6)
248 #define PORT_FORCE_FULL_DUPLEX		BIT(5)
249 
250 #define REG_PORT_1_CTRL_10		0x1D
251 #define REG_PORT_2_CTRL_10		0x2D
252 #define REG_PORT_3_CTRL_10		0x3D
253 #define REG_PORT_4_CTRL_10		0x4D
254 
255 #define PORT_LED_OFF			BIT(7)
256 #define PORT_TX_DISABLE			BIT(6)
257 #define PORT_AUTO_NEG_RESTART		BIT(5)
258 #define PORT_POWER_DOWN			BIT(3)
259 #define PORT_AUTO_MDIX_DISABLE		BIT(2)
260 #define PORT_FORCE_MDIX			BIT(1)
261 #define PORT_MAC_LOOPBACK		BIT(0)
262 
263 #define REG_PORT_1_STATUS_2		0x1E
264 #define REG_PORT_2_STATUS_2		0x2E
265 #define REG_PORT_3_STATUS_2		0x3E
266 #define REG_PORT_4_STATUS_2		0x4E
267 
268 #define PORT_MDIX_STATUS		BIT(7)
269 #define PORT_AUTO_NEG_COMPLETE		BIT(6)
270 #define PORT_STAT_LINK_GOOD		BIT(5)
271 
272 #define REG_PORT_1_STATUS_3		0x1F
273 #define REG_PORT_2_STATUS_3		0x2F
274 #define REG_PORT_3_STATUS_3		0x3F
275 #define REG_PORT_4_STATUS_3		0x4F
276 
277 #define PORT_PHY_LOOPBACK		BIT(7)
278 #define PORT_PHY_ISOLATE		BIT(5)
279 #define PORT_PHY_SOFT_RESET		BIT(4)
280 #define PORT_PHY_FORCE_LINK		BIT(3)
281 #define PORT_PHY_MODE_M			0x7
282 #define PHY_MODE_IN_AUTO_NEG		1
283 #define PHY_MODE_10BT_HALF		2
284 #define PHY_MODE_100BT_HALF		3
285 #define PHY_MODE_10BT_FULL		5
286 #define PHY_MODE_100BT_FULL		6
287 #define PHY_MODE_ISOLDATE		7
288 
289 #define REG_PORT_CTRL_0			0x00
290 #define REG_PORT_CTRL_1			0x01
291 #define REG_PORT_CTRL_2			0x02
292 #define REG_PORT_CTRL_VID		0x03
293 
294 #define REG_PORT_CTRL_5			0x05
295 
296 #define REG_PORT_STATUS_1		0x09
297 #define REG_PORT_LINK_MD_CTRL		0x0A
298 #define REG_PORT_LINK_MD_RESULT		0x0B
299 #define REG_PORT_CTRL_9			0x0C
300 #define REG_PORT_CTRL_10		0x0D
301 #define REG_PORT_STATUS_3		0x0F
302 
303 #define REG_PORT_CTRL_12		0xA0
304 #define REG_PORT_CTRL_13		0xA1
305 #define REG_PORT_RATE_CTRL_3		0xA2
306 #define REG_PORT_RATE_CTRL_2		0xA3
307 #define REG_PORT_RATE_CTRL_1		0xA4
308 #define REG_PORT_RATE_CTRL_0		0xA5
309 #define REG_PORT_RATE_LIMIT		0xA6
310 #define REG_PORT_IN_RATE_0		0xA7
311 #define REG_PORT_IN_RATE_1		0xA8
312 #define REG_PORT_IN_RATE_2		0xA9
313 #define REG_PORT_IN_RATE_3		0xAA
314 #define REG_PORT_OUT_RATE_0		0xAB
315 #define REG_PORT_OUT_RATE_1		0xAC
316 #define REG_PORT_OUT_RATE_2		0xAD
317 #define REG_PORT_OUT_RATE_3		0xAE
318 
319 #define PORT_CTRL_ADDR(port, addr)		\
320 	((addr) + REG_PORT_1_CTRL_0 + (port) *	\
321 		(REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
322 
323 #define REG_SW_MAC_ADDR_0		0x68
324 #define REG_SW_MAC_ADDR_1		0x69
325 #define REG_SW_MAC_ADDR_2		0x6A
326 #define REG_SW_MAC_ADDR_3		0x6B
327 #define REG_SW_MAC_ADDR_4		0x6C
328 #define REG_SW_MAC_ADDR_5		0x6D
329 
330 #define TABLE_EXT_SELECT_S		5
331 #define TABLE_EEE_V			1
332 #define TABLE_ACL_V			2
333 #define TABLE_PME_V			4
334 #define TABLE_LINK_MD_V			5
335 #define TABLE_EEE			(TABLE_EEE_V << TABLE_EXT_SELECT_S)
336 #define TABLE_ACL			(TABLE_ACL_V << TABLE_EXT_SELECT_S)
337 #define TABLE_PME			(TABLE_PME_V << TABLE_EXT_SELECT_S)
338 #define TABLE_LINK_MD			(TABLE_LINK_MD << TABLE_EXT_SELECT_S)
339 #define TABLE_READ			BIT(4)
340 #define TABLE_SELECT_S			2
341 #define TABLE_STATIC_MAC_V		0
342 #define TABLE_VLAN_V			1
343 #define TABLE_DYNAMIC_MAC_V		2
344 #define TABLE_MIB_V			3
345 #define TABLE_STATIC_MAC		(TABLE_STATIC_MAC_V << TABLE_SELECT_S)
346 #define TABLE_VLAN			(TABLE_VLAN_V << TABLE_SELECT_S)
347 #define TABLE_DYNAMIC_MAC		(TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)
348 #define TABLE_MIB			(TABLE_MIB_V << TABLE_SELECT_S)
349 
350 #define REG_IND_CTRL_1			0x6F
351 
352 #define TABLE_ENTRY_MASK		0x03FF
353 #define TABLE_EXT_ENTRY_MASK		0x0FFF
354 
355 #define REG_IND_DATA_5			0x73
356 #define REG_IND_DATA_2			0x76
357 #define REG_IND_DATA_1			0x77
358 #define REG_IND_DATA_0			0x78
359 
360 #define REG_IND_DATA_PME_EEE_ACL	0xA0
361 
362 #define REG_INT_STATUS			0x7C
363 #define REG_INT_ENABLE			0x7D
364 
365 #define INT_PME				BIT(4)
366 
367 #define REG_ACL_INT_STATUS		0x7E
368 #define REG_ACL_INT_ENABLE		0x7F
369 
370 #define INT_PORT_5			BIT(4)
371 #define INT_PORT_4			BIT(3)
372 #define INT_PORT_3			BIT(2)
373 #define INT_PORT_2			BIT(1)
374 #define INT_PORT_1			BIT(0)
375 
376 #define INT_PORT_ALL			\
377 	(INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)
378 
379 #define REG_SW_CTRL_12			0x80
380 #define REG_SW_CTRL_13			0x81
381 
382 #define SWITCH_802_1P_MASK		3
383 #define SWITCH_802_1P_BASE		3
384 #define SWITCH_802_1P_SHIFT		2
385 
386 #define SW_802_1P_MAP_M			KS_PRIO_M
387 #define SW_802_1P_MAP_S			KS_PRIO_S
388 
389 #define REG_SWITCH_CTRL_14		0x82
390 
391 #define SW_PRIO_MAPPING_M		KS_PRIO_M
392 #define SW_PRIO_MAPPING_S		6
393 #define SW_PRIO_MAP_3_HI		0
394 #define SW_PRIO_MAP_2_HI		2
395 #define SW_PRIO_MAP_0_LO		3
396 
397 #define REG_SW_CTRL_15			0x83
398 #define REG_SW_CTRL_16			0x84
399 #define REG_SW_CTRL_17			0x85
400 #define REG_SW_CTRL_18			0x86
401 
402 #define SW_SELF_ADDR_FILTER_ENABLE	BIT(6)
403 
404 #define REG_SW_UNK_UCAST_CTRL		0x83
405 #define REG_SW_UNK_MCAST_CTRL		0x84
406 #define REG_SW_UNK_VID_CTRL		0x85
407 #define REG_SW_UNK_IP_MCAST_CTRL	0x86
408 
409 #define SW_UNK_FWD_ENABLE		BIT(5)
410 #define SW_UNK_FWD_MAP			KS_PORT_M
411 
412 #define REG_SW_CTRL_19			0x87
413 
414 #define SW_IN_RATE_LIMIT_PERIOD_M	0x3
415 #define SW_IN_RATE_LIMIT_PERIOD_S	4
416 #define SW_IN_RATE_LIMIT_16_MS		0
417 #define SW_IN_RATE_LIMIT_64_MS		1
418 #define SW_IN_RATE_LIMIT_256_MS		2
419 #define SW_OUT_RATE_LIMIT_QUEUE_BASED	BIT(3)
420 #define SW_INS_TAG_ENABLE		BIT(2)
421 
422 #define REG_TOS_PRIO_CTRL_0		0x90
423 #define REG_TOS_PRIO_CTRL_1		0x91
424 #define REG_TOS_PRIO_CTRL_2		0x92
425 #define REG_TOS_PRIO_CTRL_3		0x93
426 #define REG_TOS_PRIO_CTRL_4		0x94
427 #define REG_TOS_PRIO_CTRL_5		0x95
428 #define REG_TOS_PRIO_CTRL_6		0x96
429 #define REG_TOS_PRIO_CTRL_7		0x97
430 #define REG_TOS_PRIO_CTRL_8		0x98
431 #define REG_TOS_PRIO_CTRL_9		0x99
432 #define REG_TOS_PRIO_CTRL_10		0x9A
433 #define REG_TOS_PRIO_CTRL_11		0x9B
434 #define REG_TOS_PRIO_CTRL_12		0x9C
435 #define REG_TOS_PRIO_CTRL_13		0x9D
436 #define REG_TOS_PRIO_CTRL_14		0x9E
437 #define REG_TOS_PRIO_CTRL_15		0x9F
438 
439 #define TOS_PRIO_M			KS_PRIO_M
440 #define TOS_PRIO_S			KS_PRIO_S
441 
442 #define REG_SW_CTRL_20			0xA3
443 
444 #define SW_GMII_DRIVE_STRENGTH_S	4
445 #define SW_DRIVE_STRENGTH_M		0x7
446 #define SW_DRIVE_STRENGTH_2MA		0
447 #define SW_DRIVE_STRENGTH_4MA		1
448 #define SW_DRIVE_STRENGTH_8MA		2
449 #define SW_DRIVE_STRENGTH_12MA		3
450 #define SW_DRIVE_STRENGTH_16MA		4
451 #define SW_DRIVE_STRENGTH_20MA		5
452 #define SW_DRIVE_STRENGTH_24MA		6
453 #define SW_DRIVE_STRENGTH_28MA		7
454 #define SW_MII_DRIVE_STRENGTH_S		0
455 
456 #define REG_SW_CTRL_21			0xA4
457 
458 #define SW_IPV6_MLD_OPTION		BIT(3)
459 #define SW_IPV6_MLD_SNOOP		BIT(2)
460 
461 #define REG_PORT_1_CTRL_12		0xB0
462 #define REG_PORT_2_CTRL_12		0xC0
463 #define REG_PORT_3_CTRL_12		0xD0
464 #define REG_PORT_4_CTRL_12		0xE0
465 #define REG_PORT_5_CTRL_12		0xF0
466 
467 #define PORT_PASS_ALL			BIT(6)
468 #define PORT_INS_TAG_FOR_PORT_5_S	3
469 #define PORT_INS_TAG_FOR_PORT_5		BIT(3)
470 #define PORT_INS_TAG_FOR_PORT_4		BIT(2)
471 #define PORT_INS_TAG_FOR_PORT_3		BIT(1)
472 #define PORT_INS_TAG_FOR_PORT_2		BIT(0)
473 
474 #define REG_PORT_1_CTRL_13		0xB1
475 #define REG_PORT_2_CTRL_13		0xC1
476 #define REG_PORT_3_CTRL_13		0xD1
477 #define REG_PORT_4_CTRL_13		0xE1
478 #define REG_PORT_5_CTRL_13		0xF1
479 
480 #define PORT_QUEUE_SPLIT_H		BIT(1)
481 #define PORT_QUEUE_SPLIT_1		0
482 #define PORT_QUEUE_SPLIT_2		1
483 #define PORT_QUEUE_SPLIT_4		2
484 #define PORT_DROP_TAG			BIT(0)
485 
486 #define REG_PORT_1_CTRL_14		0xB2
487 #define REG_PORT_2_CTRL_14		0xC2
488 #define REG_PORT_3_CTRL_14		0xD2
489 #define REG_PORT_4_CTRL_14		0xE2
490 #define REG_PORT_5_CTRL_14		0xF2
491 #define REG_PORT_1_CTRL_15		0xB3
492 #define REG_PORT_2_CTRL_15		0xC3
493 #define REG_PORT_3_CTRL_15		0xD3
494 #define REG_PORT_4_CTRL_15		0xE3
495 #define REG_PORT_5_CTRL_15		0xF3
496 #define REG_PORT_1_CTRL_16		0xB4
497 #define REG_PORT_2_CTRL_16		0xC4
498 #define REG_PORT_3_CTRL_16		0xD4
499 #define REG_PORT_4_CTRL_16		0xE4
500 #define REG_PORT_5_CTRL_16		0xF4
501 #define REG_PORT_1_CTRL_17		0xB5
502 #define REG_PORT_2_CTRL_17		0xC5
503 #define REG_PORT_3_CTRL_17		0xD5
504 #define REG_PORT_4_CTRL_17		0xE5
505 #define REG_PORT_5_CTRL_17		0xF5
506 
507 #define REG_PORT_1_RATE_CTRL_3		0xB2
508 #define REG_PORT_1_RATE_CTRL_2		0xB3
509 #define REG_PORT_1_RATE_CTRL_1		0xB4
510 #define REG_PORT_1_RATE_CTRL_0		0xB5
511 #define REG_PORT_2_RATE_CTRL_3		0xC2
512 #define REG_PORT_2_RATE_CTRL_2		0xC3
513 #define REG_PORT_2_RATE_CTRL_1		0xC4
514 #define REG_PORT_2_RATE_CTRL_0		0xC5
515 #define REG_PORT_3_RATE_CTRL_3		0xD2
516 #define REG_PORT_3_RATE_CTRL_2		0xD3
517 #define REG_PORT_3_RATE_CTRL_1		0xD4
518 #define REG_PORT_3_RATE_CTRL_0		0xD5
519 #define REG_PORT_4_RATE_CTRL_3		0xE2
520 #define REG_PORT_4_RATE_CTRL_2		0xE3
521 #define REG_PORT_4_RATE_CTRL_1		0xE4
522 #define REG_PORT_4_RATE_CTRL_0		0xE5
523 #define REG_PORT_5_RATE_CTRL_3		0xF2
524 #define REG_PORT_5_RATE_CTRL_2		0xF3
525 #define REG_PORT_5_RATE_CTRL_1		0xF4
526 #define REG_PORT_5_RATE_CTRL_0		0xF5
527 
528 #define RATE_CTRL_ENABLE		BIT(7)
529 #define RATE_RATIO_M			(BIT(7) - 1)
530 
531 #define PORT_OUT_RATE_ENABLE		BIT(7)
532 
533 #define REG_PORT_1_RATE_LIMIT		0xB6
534 #define REG_PORT_2_RATE_LIMIT		0xC6
535 #define REG_PORT_3_RATE_LIMIT		0xD6
536 #define REG_PORT_4_RATE_LIMIT		0xE6
537 #define REG_PORT_5_RATE_LIMIT		0xF6
538 
539 #define PORT_IN_PORT_BASED_S		6
540 #define PORT_RATE_PACKET_BASED_S	5
541 #define PORT_IN_FLOW_CTRL_S		4
542 #define PORT_IN_LIMIT_MODE_M		0x3
543 #define PORT_IN_LIMIT_MODE_S		2
544 #define PORT_COUNT_IFG_S		1
545 #define PORT_COUNT_PREAMBLE_S		0
546 #define PORT_IN_PORT_BASED		BIT(PORT_IN_PORT_BASED_S)
547 #define PORT_RATE_PACKET_BASED		BIT(PORT_RATE_PACKET_BASED_S)
548 #define PORT_IN_FLOW_CTRL		BIT(PORT_IN_FLOW_CTRL_S)
549 #define PORT_IN_ALL			0
550 #define PORT_IN_UNICAST			1
551 #define PORT_IN_MULTICAST		2
552 #define PORT_IN_BROADCAST		3
553 #define PORT_COUNT_IFG			BIT(PORT_COUNT_IFG_S)
554 #define PORT_COUNT_PREAMBLE		BIT(PORT_COUNT_PREAMBLE_S)
555 
556 #define REG_PORT_1_IN_RATE_0		0xB7
557 #define REG_PORT_2_IN_RATE_0		0xC7
558 #define REG_PORT_3_IN_RATE_0		0xD7
559 #define REG_PORT_4_IN_RATE_0		0xE7
560 #define REG_PORT_5_IN_RATE_0		0xF7
561 #define REG_PORT_1_IN_RATE_1		0xB8
562 #define REG_PORT_2_IN_RATE_1		0xC8
563 #define REG_PORT_3_IN_RATE_1		0xD8
564 #define REG_PORT_4_IN_RATE_1		0xE8
565 #define REG_PORT_5_IN_RATE_1		0xF8
566 #define REG_PORT_1_IN_RATE_2		0xB9
567 #define REG_PORT_2_IN_RATE_2		0xC9
568 #define REG_PORT_3_IN_RATE_2		0xD9
569 #define REG_PORT_4_IN_RATE_2		0xE9
570 #define REG_PORT_5_IN_RATE_2		0xF9
571 #define REG_PORT_1_IN_RATE_3		0xBA
572 #define REG_PORT_2_IN_RATE_3		0xCA
573 #define REG_PORT_3_IN_RATE_3		0xDA
574 #define REG_PORT_4_IN_RATE_3		0xEA
575 #define REG_PORT_5_IN_RATE_3		0xFA
576 
577 #define PORT_IN_RATE_ENABLE		BIT(7)
578 #define PORT_RATE_LIMIT_M		(BIT(7) - 1)
579 
580 #define REG_PORT_1_OUT_RATE_0		0xBB
581 #define REG_PORT_2_OUT_RATE_0		0xCB
582 #define REG_PORT_3_OUT_RATE_0		0xDB
583 #define REG_PORT_4_OUT_RATE_0		0xEB
584 #define REG_PORT_5_OUT_RATE_0		0xFB
585 #define REG_PORT_1_OUT_RATE_1		0xBC
586 #define REG_PORT_2_OUT_RATE_1		0xCC
587 #define REG_PORT_3_OUT_RATE_1		0xDC
588 #define REG_PORT_4_OUT_RATE_1		0xEC
589 #define REG_PORT_5_OUT_RATE_1		0xFC
590 #define REG_PORT_1_OUT_RATE_2		0xBD
591 #define REG_PORT_2_OUT_RATE_2		0xCD
592 #define REG_PORT_3_OUT_RATE_2		0xDD
593 #define REG_PORT_4_OUT_RATE_2		0xED
594 #define REG_PORT_5_OUT_RATE_2		0xFD
595 #define REG_PORT_1_OUT_RATE_3		0xBE
596 #define REG_PORT_2_OUT_RATE_3		0xCE
597 #define REG_PORT_3_OUT_RATE_3		0xDE
598 #define REG_PORT_4_OUT_RATE_3		0xEE
599 #define REG_PORT_5_OUT_RATE_3		0xFE
600 
601 /* 88x3 specific */
602 
603 #define REG_SW_INSERT_SRC_PVID		0xC2
604 
605 /* PME */
606 
607 #define SW_PME_OUTPUT_ENABLE		BIT(1)
608 #define SW_PME_ACTIVE_HIGH		BIT(0)
609 
610 #define PORT_MAGIC_PACKET_DETECT	BIT(2)
611 #define PORT_LINK_UP_DETECT		BIT(1)
612 #define PORT_ENERGY_DETECT		BIT(0)
613 
614 /* ACL */
615 
616 #define ACL_FIRST_RULE_M		0xF
617 
618 #define ACL_MODE_M			0x3
619 #define ACL_MODE_S			4
620 #define ACL_MODE_DISABLE		0
621 #define ACL_MODE_LAYER_2		1
622 #define ACL_MODE_LAYER_3		2
623 #define ACL_MODE_LAYER_4		3
624 #define ACL_ENABLE_M			0x3
625 #define ACL_ENABLE_S			2
626 #define ACL_ENABLE_2_COUNT		0
627 #define ACL_ENABLE_2_TYPE		1
628 #define ACL_ENABLE_2_MAC		2
629 #define ACL_ENABLE_2_BOTH		3
630 #define ACL_ENABLE_3_IP			1
631 #define ACL_ENABLE_3_SRC_DST_COMP	2
632 #define ACL_ENABLE_4_PROTOCOL		0
633 #define ACL_ENABLE_4_TCP_PORT_COMP	1
634 #define ACL_ENABLE_4_UDP_PORT_COMP	2
635 #define ACL_ENABLE_4_TCP_SEQN_COMP	3
636 #define ACL_SRC				BIT(1)
637 #define ACL_EQUAL			BIT(0)
638 
639 #define ACL_MAX_PORT			0xFFFF
640 
641 #define ACL_MIN_PORT			0xFFFF
642 #define ACL_IP_ADDR			0xFFFFFFFF
643 #define ACL_TCP_SEQNUM			0xFFFFFFFF
644 
645 #define ACL_RESERVED			0xF8
646 #define ACL_PORT_MODE_M			0x3
647 #define ACL_PORT_MODE_S			1
648 #define ACL_PORT_MODE_DISABLE		0
649 #define ACL_PORT_MODE_EITHER		1
650 #define ACL_PORT_MODE_IN_RANGE		2
651 #define ACL_PORT_MODE_OUT_OF_RANGE	3
652 
653 #define ACL_TCP_FLAG_ENABLE		BIT(0)
654 
655 #define ACL_TCP_FLAG_M			0xFF
656 
657 #define ACL_TCP_FLAG			0xFF
658 #define ACL_ETH_TYPE			0xFFFF
659 #define ACL_IP_M			0xFFFFFFFF
660 
661 #define ACL_PRIO_MODE_M			0x3
662 #define ACL_PRIO_MODE_S			6
663 #define ACL_PRIO_MODE_DISABLE		0
664 #define ACL_PRIO_MODE_HIGHER		1
665 #define ACL_PRIO_MODE_LOWER		2
666 #define ACL_PRIO_MODE_REPLACE		3
667 #define ACL_PRIO_M			0x7
668 #define ACL_PRIO_S			3
669 #define ACL_VLAN_PRIO_REPLACE		BIT(2)
670 #define ACL_VLAN_PRIO_M			0x7
671 #define ACL_VLAN_PRIO_HI_M		0x3
672 
673 #define ACL_VLAN_PRIO_LO_M		0x8
674 #define ACL_VLAN_PRIO_S			7
675 #define ACL_MAP_MODE_M			0x3
676 #define ACL_MAP_MODE_S			5
677 #define ACL_MAP_MODE_DISABLE		0
678 #define ACL_MAP_MODE_OR			1
679 #define ACL_MAP_MODE_AND		2
680 #define ACL_MAP_MODE_REPLACE		3
681 #define ACL_MAP_PORT_M			0x1F
682 
683 #define ACL_CNT_M			(BIT(11) - 1)
684 #define ACL_CNT_S			5
685 #define ACL_MSEC_UNIT			BIT(4)
686 #define ACL_INTR_MODE			BIT(3)
687 
688 #define REG_PORT_ACL_BYTE_EN_MSB	0x10
689 
690 #define ACL_BYTE_EN_MSB_M		0x3F
691 
692 #define REG_PORT_ACL_BYTE_EN_LSB	0x11
693 
694 #define ACL_ACTION_START		0xA
695 #define ACL_ACTION_LEN			2
696 #define ACL_INTR_CNT_START		0xB
697 #define ACL_RULESET_START		0xC
698 #define ACL_RULESET_LEN			2
699 #define ACL_TABLE_LEN			14
700 
701 #define ACL_ACTION_ENABLE		0x000C
702 #define ACL_MATCH_ENABLE		0x1FF0
703 #define ACL_RULESET_ENABLE		0x2003
704 #define ACL_BYTE_ENABLE			((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
705 #define ACL_MODE_ENABLE			(0x10 << 8)
706 
707 #define REG_PORT_ACL_CTRL_0		0x12
708 
709 #define PORT_ACL_WRITE_DONE		BIT(6)
710 #define PORT_ACL_READ_DONE		BIT(5)
711 #define PORT_ACL_WRITE			BIT(4)
712 #define PORT_ACL_INDEX_M		0xF
713 
714 #define REG_PORT_ACL_CTRL_1		0x13
715 
716 #define PORT_ACL_FORCE_DLR_MISS		BIT(0)
717 
718 #define KSZ8795_ID_HI			0x0022
719 #define KSZ8795_ID_LO			0x1550
720 #define KSZ8863_ID_LO			0x1430
721 
722 #define KSZ8795_SW_ID			0x8795
723 
724 #define PHY_REG_LINK_MD			0x1D
725 
726 #define PHY_START_CABLE_DIAG		BIT(15)
727 #define PHY_CABLE_DIAG_RESULT_M		GENMASK(14, 13)
728 #define PHY_CABLE_DIAG_RESULT		0x6000
729 #define PHY_CABLE_STAT_NORMAL		0x0000
730 #define PHY_CABLE_STAT_OPEN		0x2000
731 #define PHY_CABLE_STAT_SHORT		0x4000
732 #define PHY_CABLE_STAT_FAILED		0x6000
733 #define PHY_CABLE_10M_SHORT		BIT(12)
734 #define PHY_CABLE_FAULT_COUNTER_M	GENMASK(8, 0)
735 
736 #define PHY_REG_PHY_CTRL		0x1F
737 
738 #define PHY_MODE_M			0x7
739 #define PHY_MODE_S			8
740 #define PHY_STAT_REVERSED_POLARITY	BIT(5)
741 #define PHY_STAT_MDIX			BIT(4)
742 #define PHY_FORCE_LINK			BIT(3)
743 #define PHY_POWER_SAVING_ENABLE		BIT(2)
744 #define PHY_REMOTE_LOOPBACK		BIT(1)
745 
746 /* Chip resource */
747 
748 #define PRIO_QUEUES			4
749 
750 #define KS_PRIO_IN_REG			4
751 
752 #define MIB_COUNTER_NUM		0x20
753 
754 /* Common names used by other drivers */
755 
756 #define P_BCAST_STORM_CTRL		REG_PORT_CTRL_0
757 #define P_PRIO_CTRL			REG_PORT_CTRL_0
758 #define P_TAG_CTRL			REG_PORT_CTRL_0
759 #define P_MIRROR_CTRL			REG_PORT_CTRL_1
760 #define P_802_1P_CTRL			REG_PORT_CTRL_2
761 #define P_PASS_ALL_CTRL			REG_PORT_CTRL_12
762 #define P_INS_SRC_PVID_CTRL		REG_PORT_CTRL_12
763 #define P_DROP_TAG_CTRL			REG_PORT_CTRL_13
764 #define P_RATE_LIMIT_CTRL		REG_PORT_RATE_LIMIT
765 
766 #define S_UNKNOWN_DA_CTRL		REG_SWITCH_CTRL_12
767 #define S_FORWARD_INVALID_VID_CTRL	REG_FORWARD_INVALID_VID
768 
769 #define S_FLUSH_TABLE_CTRL		REG_SW_CTRL_0
770 #define S_LINK_AGING_CTRL		REG_SW_CTRL_0
771 #define S_HUGE_PACKET_CTRL		REG_SW_CTRL_1
772 #define S_MIRROR_CTRL			REG_SW_CTRL_3
773 #define S_REPLACE_VID_CTRL		REG_SW_CTRL_4
774 #define S_PASS_PAUSE_CTRL		REG_SW_CTRL_10
775 #define S_802_1P_PRIO_CTRL		REG_SW_CTRL_12
776 #define S_TOS_PRIO_CTRL			REG_TOS_PRIO_CTRL_0
777 #define S_IPV6_MLD_CTRL			REG_SW_CTRL_21
778 
779 #define IND_ACC_TABLE(table)		((table) << 8)
780 
781 /* */
782 #define REG_IND_EEE_GLOB2_LO		0x34
783 #define REG_IND_EEE_GLOB2_HI		0x35
784 
785 /**
786  * MIB_COUNTER_VALUE			00-00000000-3FFFFFFF
787  * MIB_TOTAL_BYTES			00-0000000F-FFFFFFFF
788  * MIB_PACKET_DROPPED			00-00000000-0000FFFF
789  * MIB_COUNTER_VALID			00-00000020-00000000
790  * MIB_COUNTER_OVERFLOW			00-00000040-00000000
791  */
792 
793 #define MIB_COUNTER_VALUE		0x3FFFFFFF
794 
795 #define KSZ8795_MIB_TOTAL_RX_0		0x100
796 #define KSZ8795_MIB_TOTAL_TX_0		0x101
797 #define KSZ8795_MIB_TOTAL_RX_1		0x104
798 #define KSZ8795_MIB_TOTAL_TX_1		0x105
799 
800 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100
801 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105
802 
803 #define MIB_PACKET_DROPPED		0x0000FFFF
804 
805 #define MIB_TOTAL_BYTES_H		0x0000000F
806 
807 #define TAIL_TAG_OVERRIDE		BIT(6)
808 #define TAIL_TAG_LOOKUP			BIT(7)
809 
810 #define FID_ENTRIES			128
811 
812 #endif
813