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1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #ifndef BNXT_H
12 #define BNXT_H
13 
14 #define DRV_MODULE_NAME		"bnxt_en"
15 
16 /* DO NOT CHANGE DRV_VER_* defines
17  * FIXME: Delete them
18  */
19 #define DRV_VER_MAJ	1
20 #define DRV_VER_MIN	10
21 #define DRV_VER_UPD	2
22 
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <net/devlink.h>
28 #include <net/dst_metadata.h>
29 #include <net/xdp.h>
30 #include <linux/dim.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #ifdef CONFIG_TEE_BNXT_FW
33 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
34 #endif
35 
36 extern struct list_head bnxt_block_cb_list;
37 
38 struct page_pool;
39 
40 struct tx_bd {
41 	__le32 tx_bd_len_flags_type;
42 	#define TX_BD_TYPE					(0x3f << 0)
43 	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)
44 	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)
45 	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
46 	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
47 	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
48 	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 8
49 	#define TX_BD_FLAGS_LHINT				(3 << 13)
50 	 #define TX_BD_FLAGS_LHINT_SHIFT			 13
51 	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)
52 	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)
53 	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)
54 	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)
55 	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
56 	#define TX_BD_LEN					(0xffff << 16)
57 	 #define TX_BD_LEN_SHIFT				 16
58 
59 	u32 tx_bd_opaque;
60 	__le64 tx_bd_haddr;
61 } __packed;
62 
63 struct tx_bd_ext {
64 	__le32 tx_bd_hsize_lflags;
65 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)
66 	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)
67 	#define TX_BD_FLAGS_NO_CRC				(1 << 2)
68 	#define TX_BD_FLAGS_STAMP				(1 << 3)
69 	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)
70 	#define TX_BD_FLAGS_LSO					(1 << 5)
71 	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)
72 	#define TX_BD_FLAGS_T_IPID				(1 << 7)
73 	#define TX_BD_HSIZE					(0xff << 16)
74 	 #define TX_BD_HSIZE_SHIFT				 16
75 
76 	__le32 tx_bd_mss;
77 	__le32 tx_bd_cfa_action;
78 	#define TX_BD_CFA_ACTION				(0xffff << 16)
79 	 #define TX_BD_CFA_ACTION_SHIFT				 16
80 
81 	__le32 tx_bd_cfa_meta;
82 	#define TX_BD_CFA_META_MASK                             0xfffffff
83 	#define TX_BD_CFA_META_VID_MASK                         0xfff
84 	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
85 	 #define TX_BD_CFA_META_PRI_SHIFT                        12
86 	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
87 	 #define TX_BD_CFA_META_TPID_SHIFT                       16
88 	#define TX_BD_CFA_META_KEY                              (0xf << 28)
89 	 #define TX_BD_CFA_META_KEY_SHIFT			 28
90 	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
91 };
92 
93 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
94 
95 struct rx_bd {
96 	__le32 rx_bd_len_flags_type;
97 	#define RX_BD_TYPE					(0x3f << 0)
98 	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4
99 	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5
100 	 #define RX_BD_TYPE_RX_AGG_BD				 0x6
101 	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)
102 	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)
103 	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)
104 	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)
105 	#define RX_BD_FLAGS_SOP					(1 << 6)
106 	#define RX_BD_FLAGS_EOP					(1 << 7)
107 	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
108 	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)
109 	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)
110 	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)
111 	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)
112 	#define RX_BD_LEN					(0xffff << 16)
113 	 #define RX_BD_LEN_SHIFT				 16
114 
115 	u32 rx_bd_opaque;
116 	__le64 rx_bd_haddr;
117 };
118 
119 struct tx_cmp {
120 	__le32 tx_cmp_flags_type;
121 	#define CMP_TYPE					(0x3f << 0)
122 	 #define CMP_TYPE_TX_L2_CMP				 0
123 	 #define CMP_TYPE_RX_L2_CMP				 17
124 	 #define CMP_TYPE_RX_AGG_CMP				 18
125 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19
126 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21
127 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22
128 	 #define CMP_TYPE_STATUS_CMP				 32
129 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34
130 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
131 	 #define CMP_TYPE_ERROR_STATUS				 48
132 	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL
133 	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL
134 	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL
135 	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL
136 	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL
137 
138 	#define TX_CMP_FLAGS_ERROR				(1 << 6)
139 	#define TX_CMP_FLAGS_PUSH				(1 << 7)
140 
141 	u32 tx_cmp_opaque;
142 	__le32 tx_cmp_errors_v;
143 	#define TX_CMP_V					(1 << 0)
144 	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
145 	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0
146 	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2
147 	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4
148 	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5
149 	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)
150 	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)
151 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)
152 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)
153 
154 	__le32 tx_cmp_unsed_3;
155 };
156 
157 struct rx_cmp {
158 	__le32 rx_cmp_len_flags_type;
159 	#define RX_CMP_CMP_TYPE					(0x3f << 0)
160 	#define RX_CMP_FLAGS_ERROR				(1 << 6)
161 	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)
162 	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)
163 	#define RX_CMP_FLAGS_PKT_METADATA_PRESENT		(1 << 11)
164 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12
165 	 #define RX_CMP_FLAGS_ITYPES_MASK			 0xf000
166 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)
167 	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)
168 	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)
169 	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)
170 	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)
171 	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)
172 	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)
173 	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)
174 	#define RX_CMP_LEN					(0xffff << 16)
175 	 #define RX_CMP_LEN_SHIFT				 16
176 
177 	u32 rx_cmp_opaque;
178 	__le32 rx_cmp_misc_v1;
179 	#define RX_CMP_V1					(1 << 0)
180 	#define RX_CMP_AGG_BUFS					(0x1f << 1)
181 	 #define RX_CMP_AGG_BUFS_SHIFT				 1
182 	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)
183 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9
184 	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)
185 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16
186 
187 	__le32 rx_cmp_rss_hash;
188 };
189 
190 #define BNXT_PTP_RX_TS_VALID(flags)				\
191 	(((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
192 
193 #define BNXT_ALL_RX_TS_VALID(flags)				\
194 	!((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
195 
196 #define RX_CMP_HASH_VALID(rxcmp)				\
197 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
198 
199 #define RSS_PROFILE_ID_MASK	0x1f
200 
201 #define RX_CMP_HASH_TYPE(rxcmp)					\
202 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
203 	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
204 
205 struct rx_cmp_ext {
206 	__le32 rx_cmp_flags2;
207 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
208 	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)
209 	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)
210 	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)
211 	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)
212 	__le32 rx_cmp_meta_data;
213 	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff
214 	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff
215 	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000
216 	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16
217 	__le32 rx_cmp_cfa_code_errors_v2;
218 	#define RX_CMP_V					(1 << 0)
219 	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)
220 	 #define RX_CMPL_ERRORS_SFT				 1
221 	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)
222 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)
223 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)
224 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
225 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)
226 	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)
227 	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)
228 	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)
229 	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)
230 	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)
231 	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)
232 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)
233 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)
234 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)
235 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)
236 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)
237 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)
238 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)
239 	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)
240 	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)
241 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)
242 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)
243 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)
244 	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)
245 	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)
246 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)
247 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
248 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)
249 
250 	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)
251 	 #define RX_CMPL_CFA_CODE_SFT				 16
252 
253 	__le32 rx_cmp_timestamp;
254 };
255 
256 #define RX_CMP_L2_ERRORS						\
257 	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
258 
259 #define RX_CMP_L4_CS_BITS						\
260 	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
261 
262 #define RX_CMP_L4_CS_ERR_BITS						\
263 	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
264 
265 #define RX_CMP_L4_CS_OK(rxcmp1)						\
266 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
267 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
268 
269 #define RX_CMP_ENCAP(rxcmp1)						\
270 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
271 	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
272 
273 #define RX_CMP_CFA_CODE(rxcmpl1)					\
274 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
275 	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
276 
277 struct rx_agg_cmp {
278 	__le32 rx_agg_cmp_len_flags_type;
279 	#define RX_AGG_CMP_TYPE					(0x3f << 0)
280 	#define RX_AGG_CMP_LEN					(0xffff << 16)
281 	 #define RX_AGG_CMP_LEN_SHIFT				 16
282 	u32 rx_agg_cmp_opaque;
283 	__le32 rx_agg_cmp_v;
284 	#define RX_AGG_CMP_V					(1 << 0)
285 	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)
286 	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16
287 	__le32 rx_agg_cmp_unused;
288 };
289 
290 #define TPA_AGG_AGG_ID(rx_agg)				\
291 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
292 	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
293 
294 struct rx_tpa_start_cmp {
295 	__le32 rx_tpa_start_cmp_len_flags_type;
296 	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)
297 	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)
298 	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6
299 	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)
300 	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)
301 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7
302 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
303 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
304 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
305 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)
306 	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)
307 	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)
308 	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)
309 	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12
310 	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)
311 	#define RX_TPA_START_CMP_LEN				(0xffff << 16)
312 	 #define RX_TPA_START_CMP_LEN_SHIFT			 16
313 
314 	u32 rx_tpa_start_cmp_opaque;
315 	__le32 rx_tpa_start_cmp_misc_v1;
316 	#define RX_TPA_START_CMP_V1				(0x1 << 0)
317 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)
318 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9
319 	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)
320 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25
321 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)
322 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16
323 
324 	__le32 rx_tpa_start_cmp_rss_hash;
325 };
326 
327 #define TPA_START_HASH_VALID(rx_tpa_start)				\
328 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
329 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
330 
331 #define TPA_START_HASH_TYPE(rx_tpa_start)				\
332 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
333 	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\
334 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
335 
336 #define TPA_START_AGG_ID(rx_tpa_start)					\
337 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
338 	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
339 
340 #define TPA_START_AGG_ID_P5(rx_tpa_start)				\
341 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
342 	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
343 
344 #define TPA_START_ERROR(rx_tpa_start)					\
345 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
346 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
347 
348 struct rx_tpa_start_cmp_ext {
349 	__le32 rx_tpa_start_cmp_flags2;
350 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
351 	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)
352 	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)
353 	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)
354 	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)
355 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)
356 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)
357 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10
358 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)
359 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
360 
361 	__le32 rx_tpa_start_cmp_metadata;
362 	__le32 rx_tpa_start_cmp_cfa_code_v2;
363 	#define RX_TPA_START_CMP_V2				(0x1 << 0)
364 	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)
365 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1
366 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
367 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
368 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
369 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)
370 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16
371 	__le32 rx_tpa_start_cmp_hdr_info;
372 };
373 
374 #define TPA_START_CFA_CODE(rx_tpa_start)				\
375 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
376 	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
377 
378 #define TPA_START_IS_IPV6(rx_tpa_start)				\
379 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
380 	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
381 
382 #define TPA_START_ERROR_CODE(rx_tpa_start)				\
383 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
384 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\
385 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
386 
387 struct rx_tpa_end_cmp {
388 	__le32 rx_tpa_end_cmp_len_flags_type;
389 	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
390 	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)
391 	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6
392 	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)
393 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7
394 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
395 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
396 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
397 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)
398 	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)
399 	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)
400 	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12
401 	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)
402 	#define RX_TPA_END_CMP_LEN				(0xffff << 16)
403 	 #define RX_TPA_END_CMP_LEN_SHIFT			 16
404 
405 	u32 rx_tpa_end_cmp_opaque;
406 	__le32 rx_tpa_end_cmp_misc_v1;
407 	#define RX_TPA_END_CMP_V1				(0x1 << 0)
408 	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)
409 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1
410 	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)
411 	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8
412 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)
413 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16
414 	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)
415 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25
416 	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)
417 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16
418 
419 	__le32 rx_tpa_end_cmp_tsdelta;
420 	#define RX_TPA_END_GRO_TS				(0x1 << 31)
421 };
422 
423 #define TPA_END_AGG_ID(rx_tpa_end)					\
424 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
425 	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
426 
427 #define TPA_END_AGG_ID_P5(rx_tpa_end)					\
428 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
429 	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
430 
431 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\
432 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
433 	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
434 
435 #define TPA_END_AGG_BUFS(rx_tpa_end)					\
436 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
437 	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
438 
439 #define TPA_END_TPA_SEGS(rx_tpa_end)					\
440 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
441 	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
442 
443 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\
444 	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\
445 		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
446 
447 #define TPA_END_GRO(rx_tpa_end)						\
448 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
449 	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
450 
451 #define TPA_END_GRO_TS(rx_tpa_end)					\
452 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
453 	    cpu_to_le32(RX_TPA_END_GRO_TS)))
454 
455 struct rx_tpa_end_cmp_ext {
456 	__le32 rx_tpa_end_cmp_dup_acks;
457 	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)
458 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)
459 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16
460 	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)
461 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24
462 
463 	__le32 rx_tpa_end_cmp_seg_len;
464 	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)
465 
466 	__le32 rx_tpa_end_cmp_errors_v2;
467 	#define RX_TPA_END_CMP_V2				(0x1 << 0)
468 	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)
469 	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)
470 	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1
471 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
472 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
473 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)
474 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)
475 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
476 
477 	u32 rx_tpa_end_cmp_start_opaque;
478 };
479 
480 #define TPA_END_ERRORS(rx_tpa_end_ext)					\
481 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
482 	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
483 
484 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\
485 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
486 	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\
487 	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
488 
489 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\
490 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
491 	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
492 
493 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
494 	(((data1) &							\
495 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
496 	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
497 
498 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)			\
499 	(((data1) &							\
500 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
501 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
502 
503 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)			\
504 	((data2) &							\
505 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
506 
507 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
508 	!!((data1) &							\
509 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
510 
511 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
512 	!!((data1) &							\
513 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
514 
515 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)				\
516 	(((data1) &							\
517 	  ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
518 	 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
519 
520 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)				\
521 	(((data2) &							\
522 	  ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
523 	 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
524 
525 struct nqe_cn {
526 	__le16	type;
527 	#define NQ_CN_TYPE_MASK           0x3fUL
528 	#define NQ_CN_TYPE_SFT            0
529 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
530 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
531 	__le16	reserved16;
532 	__le32	cq_handle_low;
533 	__le32	v;
534 	#define NQ_CN_V     0x1UL
535 	__le32	cq_handle_high;
536 };
537 
538 #define DB_IDX_MASK						0xffffff
539 #define DB_IDX_VALID						(0x1 << 26)
540 #define DB_IRQ_DIS						(0x1 << 27)
541 #define DB_KEY_TX						(0x0 << 28)
542 #define DB_KEY_RX						(0x1 << 28)
543 #define DB_KEY_CP						(0x2 << 28)
544 #define DB_KEY_ST						(0x3 << 28)
545 #define DB_KEY_TX_PUSH						(0x4 << 28)
546 #define DB_LONG_TX_PUSH						(0x2 << 24)
547 
548 #define BNXT_MIN_ROCE_CP_RINGS	2
549 #define BNXT_MIN_ROCE_STAT_CTXS	1
550 
551 /* 64-bit doorbell */
552 #define DBR_INDEX_MASK					0x0000000000ffffffULL
553 #define DBR_XID_MASK					0x000fffff00000000ULL
554 #define DBR_XID_SFT					32
555 #define DBR_PATH_L2					(0x1ULL << 56)
556 #define DBR_TYPE_SQ					(0x0ULL << 60)
557 #define DBR_TYPE_RQ					(0x1ULL << 60)
558 #define DBR_TYPE_SRQ					(0x2ULL << 60)
559 #define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)
560 #define DBR_TYPE_CQ					(0x4ULL << 60)
561 #define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)
562 #define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)
563 #define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)
564 #define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)
565 #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)
566 #define DBR_TYPE_NQ					(0xaULL << 60)
567 #define DBR_TYPE_NQ_ARM					(0xbULL << 60)
568 #define DBR_TYPE_NULL					(0xfULL << 60)
569 
570 #define DB_PF_OFFSET_P5					0x10000
571 #define DB_VF_OFFSET_P5					0x4000
572 
573 #define INVALID_HW_RING_ID	((u16)-1)
574 
575 /* The hardware supports certain page sizes.  Use the supported page sizes
576  * to allocate the rings.
577  */
578 #if (PAGE_SHIFT < 12)
579 #define BNXT_PAGE_SHIFT	12
580 #elif (PAGE_SHIFT <= 13)
581 #define BNXT_PAGE_SHIFT	PAGE_SHIFT
582 #elif (PAGE_SHIFT < 16)
583 #define BNXT_PAGE_SHIFT	13
584 #else
585 #define BNXT_PAGE_SHIFT	16
586 #endif
587 
588 #define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)
589 
590 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
591 #if (PAGE_SHIFT > 15)
592 #define BNXT_RX_PAGE_SHIFT 15
593 #else
594 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
595 #endif
596 
597 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
598 
599 #define BNXT_MAX_MTU		9500
600 
601 /* First RX buffer page in XDP multi-buf mode
602  *
603  * +-------------------------------------------------------------------------+
604  * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size              | skb_shared_info|
605  * | (bp->rx_dma_offset) |                                  |                |
606  * +-------------------------------------------------------------------------+
607  */
608 #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
609 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
610 	 XDP_PACKET_HEADROOM)
611 #define BNXT_MAX_PAGE_MODE_MTU	\
612 	(BNXT_MAX_PAGE_MODE_MTU_SBUF - \
613 	 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
614 
615 #define BNXT_MIN_PKT_SIZE	52
616 
617 #define BNXT_DEFAULT_RX_RING_SIZE	511
618 #define BNXT_DEFAULT_TX_RING_SIZE	511
619 
620 #define MAX_TPA		64
621 #define MAX_TPA_P5	256
622 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
623 #define MAX_TPA_SEGS_P5	0x3f
624 
625 #if (BNXT_PAGE_SHIFT == 16)
626 #define MAX_RX_PAGES_AGG_ENA	1
627 #define MAX_RX_PAGES	4
628 #define MAX_RX_AGG_PAGES	4
629 #define MAX_TX_PAGES	1
630 #define MAX_CP_PAGES	16
631 #else
632 #define MAX_RX_PAGES_AGG_ENA	8
633 #define MAX_RX_PAGES	32
634 #define MAX_RX_AGG_PAGES	32
635 #define MAX_TX_PAGES	8
636 #define MAX_CP_PAGES	128
637 #endif
638 
639 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
640 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
641 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
642 
643 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
644 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
645 
646 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
647 
648 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
649 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
650 
651 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
652 
653 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
654 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA	(RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
655 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
656 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
657 
658 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
659  * BD because the first TX BD is always a long BD.
660  */
661 #define BNXT_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)
662 
663 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
664 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
665 
666 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
667 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
668 
669 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
670 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
671 
672 #define TX_CMP_VALID(txcmp, raw_cons)					\
673 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
674 	 !((raw_cons) & bp->cp_bit))
675 
676 #define RX_CMP_VALID(rxcmp1, raw_cons)					\
677 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
678 	 !((raw_cons) & bp->cp_bit))
679 
680 #define RX_AGG_CMP_VALID(agg, raw_cons)				\
681 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
682 	 !((raw_cons) & bp->cp_bit))
683 
684 #define NQ_CMP_VALID(nqcmp, raw_cons)				\
685 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
686 
687 #define TX_CMP_TYPE(txcmp)					\
688 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
689 
690 #define RX_CMP_TYPE(rxcmp)					\
691 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
692 
693 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
694 
695 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
696 
697 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
698 
699 #define ADV_RAW_CMP(idx, n)	((idx) + (n))
700 #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)
701 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
702 #define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))
703 
704 #define DFLT_HWRM_CMD_TIMEOUT		500
705 
706 #define BNXT_RX_EVENT		1
707 #define BNXT_AGG_EVENT		2
708 #define BNXT_TX_EVENT		4
709 #define BNXT_REDIRECT_EVENT	8
710 
711 struct bnxt_sw_tx_bd {
712 	union {
713 		struct sk_buff		*skb;
714 		struct xdp_frame	*xdpf;
715 	};
716 	DEFINE_DMA_UNMAP_ADDR(mapping);
717 	DEFINE_DMA_UNMAP_LEN(len);
718 	struct page		*page;
719 	u8			is_gso;
720 	u8			is_push;
721 	u8			action;
722 	unsigned short		nr_frags;
723 	u16			rx_prod;
724 };
725 
726 struct bnxt_sw_rx_bd {
727 	void			*data;
728 	u8			*data_ptr;
729 	dma_addr_t		mapping;
730 };
731 
732 struct bnxt_sw_rx_agg_bd {
733 	struct page		*page;
734 	unsigned int		offset;
735 	dma_addr_t		mapping;
736 };
737 
738 struct bnxt_mem_init {
739 	u8	init_val;
740 	u16	offset;
741 #define	BNXT_MEM_INVALID_OFFSET	0xffff
742 	u16	size;
743 };
744 
745 struct bnxt_ring_mem_info {
746 	int			nr_pages;
747 	int			page_size;
748 	u16			flags;
749 #define BNXT_RMEM_VALID_PTE_FLAG	1
750 #define BNXT_RMEM_RING_PTE_FLAG		2
751 #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4
752 
753 	u16			depth;
754 	struct bnxt_mem_init	*mem_init;
755 
756 	void			**pg_arr;
757 	dma_addr_t		*dma_arr;
758 
759 	__le64			*pg_tbl;
760 	dma_addr_t		pg_tbl_map;
761 
762 	int			vmem_size;
763 	void			**vmem;
764 };
765 
766 struct bnxt_ring_struct {
767 	struct bnxt_ring_mem_info	ring_mem;
768 
769 	u16			fw_ring_id; /* Ring id filled by Chimp FW */
770 	union {
771 		u16		grp_idx;
772 		u16		map_idx; /* Used by cmpl rings */
773 	};
774 	u32			handle;
775 	u8			queue_id;
776 };
777 
778 struct tx_push_bd {
779 	__le32			doorbell;
780 	__le32			tx_bd_len_flags_type;
781 	u32			tx_bd_opaque;
782 	struct tx_bd_ext	txbd2;
783 };
784 
785 struct tx_push_buffer {
786 	struct tx_push_bd	push_bd;
787 	u32			data[25];
788 };
789 
790 struct bnxt_db_info {
791 	void __iomem		*doorbell;
792 	union {
793 		u64		db_key64;
794 		u32		db_key32;
795 	};
796 };
797 
798 struct bnxt_tx_ring_info {
799 	struct bnxt_napi	*bnapi;
800 	u16			tx_prod;
801 	u16			tx_cons;
802 	u16			txq_index;
803 	u8			kick_pending;
804 	struct bnxt_db_info	tx_db;
805 
806 	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];
807 	struct bnxt_sw_tx_bd	*tx_buf_ring;
808 
809 	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];
810 
811 	struct tx_push_buffer	*tx_push;
812 	dma_addr_t		tx_push_mapping;
813 	__le64			data_mapping;
814 
815 #define BNXT_DEV_STATE_CLOSING	0x1
816 	u32			dev_state;
817 
818 	struct bnxt_ring_struct	tx_ring_struct;
819 	/* Synchronize simultaneous xdp_xmit on same ring */
820 	spinlock_t		xdp_tx_lock;
821 };
822 
823 #define BNXT_LEGACY_COAL_CMPL_PARAMS					\
824 	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\
825 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\
826 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\
827 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\
828 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\
829 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
830 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\
831 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
832 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
833 
834 #define BNXT_COAL_CMPL_ENABLES						\
835 	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
836 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
837 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
838 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
839 
840 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\
841 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
842 
843 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\
844 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
845 
846 struct bnxt_coal_cap {
847 	u32			cmpl_params;
848 	u32			nq_params;
849 	u16			num_cmpl_dma_aggr_max;
850 	u16			num_cmpl_dma_aggr_during_int_max;
851 	u16			cmpl_aggr_dma_tmr_max;
852 	u16			cmpl_aggr_dma_tmr_during_int_max;
853 	u16			int_lat_tmr_min_max;
854 	u16			int_lat_tmr_max_max;
855 	u16			num_cmpl_aggr_int_max;
856 	u16			timer_units;
857 };
858 
859 struct bnxt_coal {
860 	u16			coal_ticks;
861 	u16			coal_ticks_irq;
862 	u16			coal_bufs;
863 	u16			coal_bufs_irq;
864 			/* RING_IDLE enabled when coal ticks < idle_thresh  */
865 	u16			idle_thresh;
866 	u8			bufs_per_record;
867 	u8			budget;
868 	u16			flags;
869 };
870 
871 struct bnxt_tpa_info {
872 	void			*data;
873 	u8			*data_ptr;
874 	dma_addr_t		mapping;
875 	u16			len;
876 	unsigned short		gso_type;
877 	u32			flags2;
878 	u32			metadata;
879 	enum pkt_hash_types	hash_type;
880 	u32			rss_hash;
881 	u32			hdr_info;
882 
883 #define BNXT_TPA_L4_SIZE(hdr_info)	\
884 	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
885 
886 #define BNXT_TPA_INNER_L3_OFF(hdr_info)	\
887 	(((hdr_info) >> 18) & 0x1ff)
888 
889 #define BNXT_TPA_INNER_L2_OFF(hdr_info)	\
890 	(((hdr_info) >> 9) & 0x1ff)
891 
892 #define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\
893 	((hdr_info) & 0x1ff)
894 
895 	u16			cfa_code; /* cfa_code in TPA start compl */
896 	u8			agg_count;
897 	struct rx_agg_cmp	*agg_arr;
898 };
899 
900 #define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)
901 
902 struct bnxt_tpa_idx_map {
903 	u16		agg_id_tbl[1024];
904 	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
905 };
906 
907 struct bnxt_rx_ring_info {
908 	struct bnxt_napi	*bnapi;
909 	u16			rx_prod;
910 	u16			rx_agg_prod;
911 	u16			rx_sw_agg_prod;
912 	u16			rx_next_cons;
913 	struct bnxt_db_info	rx_db;
914 	struct bnxt_db_info	rx_agg_db;
915 
916 	struct bpf_prog		*xdp_prog;
917 
918 	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];
919 	struct bnxt_sw_rx_bd	*rx_buf_ring;
920 
921 	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];
922 	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;
923 
924 	unsigned long		*rx_agg_bmap;
925 	u16			rx_agg_bmap_size;
926 
927 	struct page		*rx_page;
928 	unsigned int		rx_page_offset;
929 
930 	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];
931 	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
932 
933 	struct bnxt_tpa_info	*rx_tpa;
934 	struct bnxt_tpa_idx_map *rx_tpa_idx_map;
935 
936 	struct bnxt_ring_struct	rx_ring_struct;
937 	struct bnxt_ring_struct	rx_agg_ring_struct;
938 	struct xdp_rxq_info	xdp_rxq;
939 	struct page_pool	*page_pool;
940 };
941 
942 struct bnxt_rx_sw_stats {
943 	u64			rx_l4_csum_errors;
944 	u64			rx_resets;
945 	u64			rx_buf_errors;
946 	u64			rx_oom_discards;
947 	u64			rx_netpoll_discards;
948 };
949 
950 struct bnxt_cmn_sw_stats {
951 	u64			missed_irqs;
952 };
953 
954 struct bnxt_sw_stats {
955 	struct bnxt_rx_sw_stats rx;
956 	struct bnxt_cmn_sw_stats cmn;
957 };
958 
959 struct bnxt_total_ring_err_stats {
960 	u64			rx_total_l4_csum_errors;
961 	u64			rx_total_resets;
962 	u64			rx_total_buf_errors;
963 	u64			rx_total_oom_discards;
964 	u64			rx_total_netpoll_discards;
965 	u64			rx_total_ring_discards;
966 	u64			tx_total_ring_discards;
967 	u64			total_missed_irqs;
968 };
969 
970 struct bnxt_stats_mem {
971 	u64		*sw_stats;
972 	u64		*hw_masks;
973 	void		*hw_stats;
974 	dma_addr_t	hw_stats_map;
975 	int		len;
976 };
977 
978 struct bnxt_cp_ring_info {
979 	struct bnxt_napi	*bnapi;
980 	u32			cp_raw_cons;
981 	struct bnxt_db_info	cp_db;
982 
983 	u8			had_work_done:1;
984 	u8			has_more_work:1;
985 
986 	u32			last_cp_raw_cons;
987 
988 	struct bnxt_coal	rx_ring_coal;
989 	u64			rx_packets;
990 	u64			rx_bytes;
991 	u64			event_ctr;
992 
993 	struct dim		dim;
994 
995 	union {
996 		struct tx_cmp	**cp_desc_ring;
997 		struct nqe_cn	**nq_desc_ring;
998 	};
999 
1000 	dma_addr_t		*cp_desc_mapping;
1001 
1002 	struct bnxt_stats_mem	stats;
1003 	u32			hw_stats_ctx_id;
1004 
1005 	struct bnxt_sw_stats	sw_stats;
1006 
1007 	struct bnxt_ring_struct	cp_ring_struct;
1008 
1009 	struct bnxt_cp_ring_info *cp_ring_arr[2];
1010 #define BNXT_RX_HDL	0
1011 #define BNXT_TX_HDL	1
1012 };
1013 
1014 struct bnxt_napi {
1015 	struct napi_struct	napi;
1016 	struct bnxt		*bp;
1017 
1018 	int			index;
1019 	struct bnxt_cp_ring_info	cp_ring;
1020 	struct bnxt_rx_ring_info	*rx_ring;
1021 	struct bnxt_tx_ring_info	*tx_ring;
1022 
1023 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,
1024 					  int);
1025 	int			tx_pkts;
1026 	u8			events;
1027 
1028 	u32			flags;
1029 #define BNXT_NAPI_FLAG_XDP	0x1
1030 
1031 	bool			in_reset;
1032 };
1033 
1034 struct bnxt_irq {
1035 	irq_handler_t	handler;
1036 	unsigned int	vector;
1037 	u8		requested:1;
1038 	u8		have_cpumask:1;
1039 	char		name[IFNAMSIZ + 2];
1040 	cpumask_var_t	cpu_mask;
1041 };
1042 
1043 #define HWRM_RING_ALLOC_TX	0x1
1044 #define HWRM_RING_ALLOC_RX	0x2
1045 #define HWRM_RING_ALLOC_AGG	0x4
1046 #define HWRM_RING_ALLOC_CMPL	0x8
1047 #define HWRM_RING_ALLOC_NQ	0x10
1048 
1049 #define INVALID_STATS_CTX_ID	-1
1050 
1051 struct bnxt_ring_grp_info {
1052 	u16	fw_stats_ctx;
1053 	u16	fw_grp_id;
1054 	u16	rx_fw_ring_id;
1055 	u16	agg_fw_ring_id;
1056 	u16	cp_fw_ring_id;
1057 };
1058 
1059 struct bnxt_vnic_info {
1060 	u16		fw_vnic_id; /* returned by Chimp during alloc */
1061 #define BNXT_MAX_CTX_PER_VNIC	8
1062 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1063 	u16		fw_l2_ctx_id;
1064 #define BNXT_MAX_UC_ADDRS	4
1065 	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1066 				/* index 0 always dev_addr */
1067 	u16		uc_filter_count;
1068 	u8		*uc_list;
1069 
1070 	u16		*fw_grp_ids;
1071 	dma_addr_t	rss_table_dma_addr;
1072 	__le16		*rss_table;
1073 	dma_addr_t	rss_hash_key_dma_addr;
1074 	u64		*rss_hash_key;
1075 	int		rss_table_size;
1076 #define BNXT_RSS_TABLE_ENTRIES_P5	64
1077 #define BNXT_RSS_TABLE_SIZE_P5		(BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1078 #define BNXT_RSS_TABLE_MAX_TBL_P5	8
1079 #define BNXT_MAX_RSS_TABLE_SIZE_P5				\
1080 	(BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1081 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5				\
1082 	(BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1083 
1084 	u32		rx_mask;
1085 
1086 	u8		*mc_list;
1087 	int		mc_list_size;
1088 	int		mc_list_count;
1089 	dma_addr_t	mc_list_mapping;
1090 #define BNXT_MAX_MC_ADDRS	16
1091 
1092 	u32		flags;
1093 #define BNXT_VNIC_RSS_FLAG	1
1094 #define BNXT_VNIC_RFS_FLAG	2
1095 #define BNXT_VNIC_MCAST_FLAG	4
1096 #define BNXT_VNIC_UCAST_FLAG	8
1097 #define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x10
1098 };
1099 
1100 struct bnxt_hw_resc {
1101 	u16	min_rsscos_ctxs;
1102 	u16	max_rsscos_ctxs;
1103 	u16	min_cp_rings;
1104 	u16	max_cp_rings;
1105 	u16	resv_cp_rings;
1106 	u16	min_tx_rings;
1107 	u16	max_tx_rings;
1108 	u16	resv_tx_rings;
1109 	u16	max_tx_sch_inputs;
1110 	u16	min_rx_rings;
1111 	u16	max_rx_rings;
1112 	u16	resv_rx_rings;
1113 	u16	min_hw_ring_grps;
1114 	u16	max_hw_ring_grps;
1115 	u16	resv_hw_ring_grps;
1116 	u16	min_l2_ctxs;
1117 	u16	max_l2_ctxs;
1118 	u16	min_vnics;
1119 	u16	max_vnics;
1120 	u16	resv_vnics;
1121 	u16	min_stat_ctxs;
1122 	u16	max_stat_ctxs;
1123 	u16	resv_stat_ctxs;
1124 	u16	max_nqs;
1125 	u16	max_irqs;
1126 	u16	resv_irqs;
1127 };
1128 
1129 #if defined(CONFIG_BNXT_SRIOV)
1130 struct bnxt_vf_info {
1131 	u16	fw_fid;
1132 	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */
1133 	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only
1134 					 * stored by PF.
1135 					 */
1136 	u16	vlan;
1137 	u16	func_qcfg_flags;
1138 	u32	flags;
1139 #define BNXT_VF_QOS		0x1
1140 #define BNXT_VF_SPOOFCHK	0x2
1141 #define BNXT_VF_LINK_FORCED	0x4
1142 #define BNXT_VF_LINK_UP		0x8
1143 #define BNXT_VF_TRUST		0x10
1144 	u32	min_tx_rate;
1145 	u32	max_tx_rate;
1146 	void	*hwrm_cmd_req_addr;
1147 	dma_addr_t	hwrm_cmd_req_dma_addr;
1148 };
1149 #endif
1150 
1151 struct bnxt_pf_info {
1152 #define BNXT_FIRST_PF_FID	1
1153 #define BNXT_FIRST_VF_FID	128
1154 	u16	fw_fid;
1155 	u16	port_id;
1156 	u8	mac_addr[ETH_ALEN];
1157 	u32	first_vf_id;
1158 	u16	active_vfs;
1159 	u16	registered_vfs;
1160 	u16	max_vfs;
1161 	u32	max_encap_records;
1162 	u32	max_decap_records;
1163 	u32	max_tx_em_flows;
1164 	u32	max_tx_wm_flows;
1165 	u32	max_rx_em_flows;
1166 	u32	max_rx_wm_flows;
1167 	unsigned long	*vf_event_bmap;
1168 	u16	hwrm_cmd_req_pages;
1169 	u8	vf_resv_strategy;
1170 #define BNXT_VF_RESV_STRATEGY_MAXIMAL	0
1171 #define BNXT_VF_RESV_STRATEGY_MINIMAL	1
1172 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	2
1173 	void			*hwrm_cmd_req_addr[4];
1174 	dma_addr_t		hwrm_cmd_req_dma_addr[4];
1175 	struct bnxt_vf_info	*vf;
1176 };
1177 
1178 struct bnxt_ntuple_filter {
1179 	struct hlist_node	hash;
1180 	u8			dst_mac_addr[ETH_ALEN];
1181 	u8			src_mac_addr[ETH_ALEN];
1182 	struct flow_keys	fkeys;
1183 	__le64			filter_id;
1184 	u16			sw_id;
1185 	u8			l2_fltr_idx;
1186 	u16			rxq;
1187 	u32			flow_id;
1188 	unsigned long		state;
1189 #define BNXT_FLTR_VALID		0
1190 #define BNXT_FLTR_UPDATE	1
1191 };
1192 
1193 struct bnxt_link_info {
1194 	u8			phy_type;
1195 	u8			media_type;
1196 	u8			transceiver;
1197 	u8			phy_addr;
1198 	u8			phy_link_status;
1199 #define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK
1200 #define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL
1201 #define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK
1202 	u8			wire_speed;
1203 	u8			phy_state;
1204 #define BNXT_PHY_STATE_ENABLED		0
1205 #define BNXT_PHY_STATE_DISABLED		1
1206 
1207 	u8			link_state;
1208 #define BNXT_LINK_STATE_UNKNOWN	0
1209 #define BNXT_LINK_STATE_DOWN	1
1210 #define BNXT_LINK_STATE_UP	2
1211 #define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1212 	u8			duplex;
1213 #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1214 #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1215 	u8			pause;
1216 #define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX
1217 #define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX
1218 #define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \
1219 				 PORT_PHY_QCFG_RESP_PAUSE_TX)
1220 	u8			lp_pause;
1221 	u8			auto_pause_setting;
1222 	u8			force_pause_setting;
1223 	u8			duplex_setting;
1224 	u8			auto_mode;
1225 #define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \
1226 				 (mode) <= BNXT_LINK_AUTO_MSK)
1227 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1228 #define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1229 #define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1230 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1231 #define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1232 #define PHY_VER_LEN		3
1233 	u8			phy_ver[PHY_VER_LEN];
1234 	u16			link_speed;
1235 #define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1236 #define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1237 #define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1238 #define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1239 #define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1240 #define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1241 #define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1242 #define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1243 #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1244 #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1245 #define BNXT_LINK_SPEED_200GB	PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1246 	u16			support_speeds;
1247 	u16			support_pam4_speeds;
1248 	u16			auto_link_speeds;	/* fw adv setting */
1249 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1250 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1251 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1252 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1253 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1254 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1255 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1256 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1257 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1258 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1259 	u16			auto_pam4_link_speeds;
1260 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1261 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1262 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1263 	u16			support_auto_speeds;
1264 	u16			support_pam4_auto_speeds;
1265 	u16			lp_auto_link_speeds;
1266 	u16			lp_auto_pam4_link_speeds;
1267 	u16			force_link_speed;
1268 	u16			force_pam4_link_speed;
1269 	u32			preemphasis;
1270 	u8			module_status;
1271 	u8			active_fec_sig_mode;
1272 	u16			fec_cfg;
1273 #define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1274 #define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1275 #define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1276 #define BNXT_FEC_ENC_BASE_R_CAP	\
1277 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1278 #define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1279 #define BNXT_FEC_ENC_RS_CAP	\
1280 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1281 #define BNXT_FEC_ENC_LLRS_CAP	\
1282 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\
1283 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1284 #define BNXT_FEC_ENC_RS		\
1285 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\
1286 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\
1287 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1288 #define BNXT_FEC_ENC_LLRS	\
1289 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\
1290 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1291 
1292 	/* copy of requested setting from ethtool cmd */
1293 	u8			autoneg;
1294 #define BNXT_AUTONEG_SPEED		1
1295 #define BNXT_AUTONEG_FLOW_CTRL		2
1296 	u8			req_signal_mode;
1297 #define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1298 #define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1299 	u8			req_duplex;
1300 	u8			req_flow_ctrl;
1301 	u16			req_link_speed;
1302 	u16			advertising;	/* user adv setting */
1303 	u16			advertising_pam4;
1304 	bool			force_link_chng;
1305 
1306 	bool			phy_retry;
1307 	unsigned long		phy_retry_expires;
1308 
1309 	/* a copy of phy_qcfg output used to report link
1310 	 * info to VF
1311 	 */
1312 	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1313 };
1314 
1315 #define BNXT_FEC_RS544_ON					\
1316 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\
1317 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1318 
1319 #define BNXT_FEC_RS544_OFF					\
1320 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\
1321 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1322 
1323 #define BNXT_FEC_RS272_ON					\
1324 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\
1325 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1326 
1327 #define BNXT_FEC_RS272_OFF					\
1328 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\
1329 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1330 
1331 #define BNXT_PAM4_SUPPORTED(link_info)				\
1332 	((link_info)->support_pam4_speeds)
1333 
1334 #define BNXT_FEC_RS_ON(link_info)				\
1335 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1336 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1337 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1338 	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1339 
1340 #define BNXT_FEC_LLRS_ON					\
1341 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1342 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1343 	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1344 
1345 #define BNXT_FEC_RS_OFF(link_info)				\
1346 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\
1347 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1348 	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1349 
1350 #define BNXT_FEC_BASE_R_ON(link_info)				\
1351 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\
1352 	 BNXT_FEC_RS_OFF(link_info))
1353 
1354 #define BNXT_FEC_ALL_OFF(link_info)				\
1355 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1356 	 BNXT_FEC_RS_OFF(link_info))
1357 
1358 #define BNXT_MAX_QUEUE	8
1359 
1360 struct bnxt_queue_info {
1361 	u8	queue_id;
1362 	u8	queue_profile;
1363 };
1364 
1365 #define BNXT_MAX_LED			4
1366 
1367 struct bnxt_led_info {
1368 	u8	led_id;
1369 	u8	led_type;
1370 	u8	led_group_id;
1371 	u8	unused;
1372 	__le16	led_state_caps;
1373 #define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\
1374 	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1375 
1376 	__le16	led_color_caps;
1377 };
1378 
1379 #define BNXT_MAX_TEST	8
1380 
1381 struct bnxt_test_info {
1382 	u8 offline_mask;
1383 	u16 timeout;
1384 	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1385 };
1386 
1387 #define CHIMP_REG_VIEW_ADDR				\
1388 	((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1389 
1390 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
1391 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
1392 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
1393 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
1394 #define BNXT_CAG_REG_BASE			0x300000
1395 
1396 #define BNXT_GRC_REG_STATUS_P5			0x520
1397 
1398 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
1399 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
1400 
1401 #define BNXT_GRC_REG_CHIP_NUM			0x48
1402 #define BNXT_GRC_REG_BASE			0x260000
1403 
1404 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER		0x640180c
1405 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER		0x6401810
1406 
1407 #define BNXT_GRC_BASE_MASK			0xfffff000
1408 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
1409 
1410 struct bnxt_tc_flow_stats {
1411 	u64		packets;
1412 	u64		bytes;
1413 };
1414 
1415 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1416 struct bnxt_flower_indr_block_cb_priv {
1417 	struct net_device *tunnel_netdev;
1418 	struct bnxt *bp;
1419 	struct list_head list;
1420 };
1421 #endif
1422 
1423 struct bnxt_tc_info {
1424 	bool				enabled;
1425 
1426 	/* hash table to store TC offloaded flows */
1427 	struct rhashtable		flow_table;
1428 	struct rhashtable_params	flow_ht_params;
1429 
1430 	/* hash table to store L2 keys of TC flows */
1431 	struct rhashtable		l2_table;
1432 	struct rhashtable_params	l2_ht_params;
1433 	/* hash table to store L2 keys for TC tunnel decap */
1434 	struct rhashtable		decap_l2_table;
1435 	struct rhashtable_params	decap_l2_ht_params;
1436 	/* hash table to store tunnel decap entries */
1437 	struct rhashtable		decap_table;
1438 	struct rhashtable_params	decap_ht_params;
1439 	/* hash table to store tunnel encap entries */
1440 	struct rhashtable		encap_table;
1441 	struct rhashtable_params	encap_ht_params;
1442 
1443 	/* lock to atomically add/del an l2 node when a flow is
1444 	 * added or deleted.
1445 	 */
1446 	struct mutex			lock;
1447 
1448 	/* Fields used for batching stats query */
1449 	struct rhashtable_iter		iter;
1450 #define BNXT_FLOW_STATS_BATCH_MAX	10
1451 	struct bnxt_tc_stats_batch {
1452 		void			  *flow_node;
1453 		struct bnxt_tc_flow_stats hw_stats;
1454 	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1455 
1456 	/* Stat counter mask (width) */
1457 	u64				bytes_mask;
1458 	u64				packets_mask;
1459 };
1460 
1461 struct bnxt_vf_rep_stats {
1462 	u64			packets;
1463 	u64			bytes;
1464 	u64			dropped;
1465 };
1466 
1467 struct bnxt_vf_rep {
1468 	struct bnxt			*bp;
1469 	struct net_device		*dev;
1470 	struct metadata_dst		*dst;
1471 	u16				vf_idx;
1472 	u16				tx_cfa_action;
1473 	u16				rx_cfa_code;
1474 
1475 	struct bnxt_vf_rep_stats	rx_stats;
1476 	struct bnxt_vf_rep_stats	tx_stats;
1477 };
1478 
1479 #define PTU_PTE_VALID             0x1UL
1480 #define PTU_PTE_LAST              0x2UL
1481 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1482 
1483 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
1484 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
1485 
1486 struct bnxt_ctx_pg_info {
1487 	u32		entries;
1488 	u32		nr_pages;
1489 	void		*ctx_pg_arr[MAX_CTX_PAGES];
1490 	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];
1491 	struct bnxt_ring_mem_info ring_mem;
1492 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
1493 };
1494 
1495 #define BNXT_MAX_TQM_SP_RINGS		1
1496 #define BNXT_MAX_TQM_FP_RINGS		8
1497 #define BNXT_MAX_TQM_RINGS		\
1498 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1499 
1500 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN	256
1501 
1502 #define BNXT_SET_CTX_PAGE_ATTR(attr)					\
1503 do {									\
1504 	if (BNXT_PAGE_SIZE == 0x2000)					\
1505 		attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;	\
1506 	else if (BNXT_PAGE_SIZE == 0x10000)				\
1507 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;	\
1508 	else								\
1509 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;	\
1510 } while (0)
1511 
1512 struct bnxt_ctx_mem_info {
1513 	u32	qp_max_entries;
1514 	u16	qp_min_qp1_entries;
1515 	u16	qp_max_l2_entries;
1516 	u16	qp_entry_size;
1517 	u16	srq_max_l2_entries;
1518 	u32	srq_max_entries;
1519 	u16	srq_entry_size;
1520 	u16	cq_max_l2_entries;
1521 	u32	cq_max_entries;
1522 	u16	cq_entry_size;
1523 	u16	vnic_max_vnic_entries;
1524 	u16	vnic_max_ring_table_entries;
1525 	u16	vnic_entry_size;
1526 	u32	stat_max_entries;
1527 	u16	stat_entry_size;
1528 	u16	tqm_entry_size;
1529 	u32	tqm_min_entries_per_ring;
1530 	u32	tqm_max_entries_per_ring;
1531 	u32	mrav_max_entries;
1532 	u16	mrav_entry_size;
1533 	u16	tim_entry_size;
1534 	u32	tim_max_entries;
1535 	u16	mrav_num_entries_units;
1536 	u8	tqm_entries_multiple;
1537 	u8	tqm_fp_rings_count;
1538 
1539 	u32	flags;
1540 	#define BNXT_CTX_FLAG_INITED	0x01
1541 
1542 	struct bnxt_ctx_pg_info qp_mem;
1543 	struct bnxt_ctx_pg_info srq_mem;
1544 	struct bnxt_ctx_pg_info cq_mem;
1545 	struct bnxt_ctx_pg_info vnic_mem;
1546 	struct bnxt_ctx_pg_info stat_mem;
1547 	struct bnxt_ctx_pg_info mrav_mem;
1548 	struct bnxt_ctx_pg_info tim_mem;
1549 	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1550 
1551 #define BNXT_CTX_MEM_INIT_QP	0
1552 #define BNXT_CTX_MEM_INIT_SRQ	1
1553 #define BNXT_CTX_MEM_INIT_CQ	2
1554 #define BNXT_CTX_MEM_INIT_VNIC	3
1555 #define BNXT_CTX_MEM_INIT_STAT	4
1556 #define BNXT_CTX_MEM_INIT_MRAV	5
1557 #define BNXT_CTX_MEM_INIT_MAX	6
1558 	struct bnxt_mem_init	mem_init[BNXT_CTX_MEM_INIT_MAX];
1559 };
1560 
1561 enum bnxt_health_severity {
1562 	SEVERITY_NORMAL = 0,
1563 	SEVERITY_WARNING,
1564 	SEVERITY_RECOVERABLE,
1565 	SEVERITY_FATAL,
1566 };
1567 
1568 enum bnxt_health_remedy {
1569 	REMEDY_DEVLINK_RECOVER,
1570 	REMEDY_POWER_CYCLE_DEVICE,
1571 	REMEDY_POWER_CYCLE_HOST,
1572 	REMEDY_FW_UPDATE,
1573 	REMEDY_HW_REPLACE,
1574 };
1575 
1576 struct bnxt_fw_health {
1577 	u32 flags;
1578 	u32 polling_dsecs;
1579 	u32 master_func_wait_dsecs;
1580 	u32 normal_func_wait_dsecs;
1581 	u32 post_reset_wait_dsecs;
1582 	u32 post_reset_max_wait_dsecs;
1583 	u32 regs[4];
1584 	u32 mapped_regs[4];
1585 #define BNXT_FW_HEALTH_REG		0
1586 #define BNXT_FW_HEARTBEAT_REG		1
1587 #define BNXT_FW_RESET_CNT_REG		2
1588 #define BNXT_FW_RESET_INPROG_REG	3
1589 	u32 fw_reset_inprog_reg_mask;
1590 	u32 last_fw_heartbeat;
1591 	u32 last_fw_reset_cnt;
1592 	u8 enabled:1;
1593 	u8 primary:1;
1594 	u8 status_reliable:1;
1595 	u8 resets_reliable:1;
1596 	u8 tmr_multiplier;
1597 	u8 tmr_counter;
1598 	u8 fw_reset_seq_cnt;
1599 	u32 fw_reset_seq_regs[16];
1600 	u32 fw_reset_seq_vals[16];
1601 	u32 fw_reset_seq_delay_msec[16];
1602 	u32 echo_req_data1;
1603 	u32 echo_req_data2;
1604 	struct devlink_health_reporter	*fw_reporter;
1605 	/* Protects severity and remedy */
1606 	struct mutex lock;
1607 	enum bnxt_health_severity severity;
1608 	enum bnxt_health_remedy remedy;
1609 	u32 arrests;
1610 	u32 discoveries;
1611 	u32 survivals;
1612 	u32 fatalities;
1613 	u32 diagnoses;
1614 };
1615 
1616 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
1617 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
1618 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
1619 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
1620 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
1621 
1622 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1623 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1624 
1625 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
1626 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
1627 
1628 #define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\
1629 					 ((reg) & BNXT_GRC_OFFSET_MASK))
1630 
1631 #define BNXT_FW_STATUS_HEALTH_MSK	0xffff
1632 #define BNXT_FW_STATUS_HEALTHY		0x8000
1633 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
1634 #define BNXT_FW_STATUS_RECOVERING	0x400000
1635 
1636 #define BNXT_FW_IS_HEALTHY(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1637 					 BNXT_FW_STATUS_HEALTHY)
1638 
1639 #define BNXT_FW_IS_BOOTING(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1640 					 BNXT_FW_STATUS_HEALTHY)
1641 
1642 #define BNXT_FW_IS_ERR(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1643 					 BNXT_FW_STATUS_HEALTHY)
1644 
1645 #define BNXT_FW_IS_RECOVERING(sts)	(BNXT_FW_IS_ERR(sts) &&		       \
1646 					 ((sts) & BNXT_FW_STATUS_RECOVERING))
1647 
1648 #define BNXT_FW_RETRY			5
1649 #define BNXT_FW_IF_RETRY		10
1650 #define BNXT_FW_SLOT_RESET_RETRY	4
1651 
1652 enum board_idx {
1653 	BCM57301,
1654 	BCM57302,
1655 	BCM57304,
1656 	BCM57417_NPAR,
1657 	BCM58700,
1658 	BCM57311,
1659 	BCM57312,
1660 	BCM57402,
1661 	BCM57404,
1662 	BCM57406,
1663 	BCM57402_NPAR,
1664 	BCM57407,
1665 	BCM57412,
1666 	BCM57414,
1667 	BCM57416,
1668 	BCM57417,
1669 	BCM57412_NPAR,
1670 	BCM57314,
1671 	BCM57417_SFP,
1672 	BCM57416_SFP,
1673 	BCM57404_NPAR,
1674 	BCM57406_NPAR,
1675 	BCM57407_SFP,
1676 	BCM57407_NPAR,
1677 	BCM57414_NPAR,
1678 	BCM57416_NPAR,
1679 	BCM57452,
1680 	BCM57454,
1681 	BCM5745x_NPAR,
1682 	BCM57508,
1683 	BCM57504,
1684 	BCM57502,
1685 	BCM57508_NPAR,
1686 	BCM57504_NPAR,
1687 	BCM57502_NPAR,
1688 	BCM58802,
1689 	BCM58804,
1690 	BCM58808,
1691 	NETXTREME_E_VF,
1692 	NETXTREME_C_VF,
1693 	NETXTREME_S_VF,
1694 	NETXTREME_C_VF_HV,
1695 	NETXTREME_E_VF_HV,
1696 	NETXTREME_E_P5_VF,
1697 	NETXTREME_E_P5_VF_HV,
1698 };
1699 
1700 struct bnxt {
1701 	void __iomem		*bar0;
1702 	void __iomem		*bar1;
1703 	void __iomem		*bar2;
1704 
1705 	u32			reg_base;
1706 	u16			chip_num;
1707 #define CHIP_NUM_57301		0x16c8
1708 #define CHIP_NUM_57302		0x16c9
1709 #define CHIP_NUM_57304		0x16ca
1710 #define CHIP_NUM_58700		0x16cd
1711 #define CHIP_NUM_57402		0x16d0
1712 #define CHIP_NUM_57404		0x16d1
1713 #define CHIP_NUM_57406		0x16d2
1714 #define CHIP_NUM_57407		0x16d5
1715 
1716 #define CHIP_NUM_57311		0x16ce
1717 #define CHIP_NUM_57312		0x16cf
1718 #define CHIP_NUM_57314		0x16df
1719 #define CHIP_NUM_57317		0x16e0
1720 #define CHIP_NUM_57412		0x16d6
1721 #define CHIP_NUM_57414		0x16d7
1722 #define CHIP_NUM_57416		0x16d8
1723 #define CHIP_NUM_57417		0x16d9
1724 #define CHIP_NUM_57412L		0x16da
1725 #define CHIP_NUM_57414L		0x16db
1726 
1727 #define CHIP_NUM_5745X		0xd730
1728 #define CHIP_NUM_57452		0xc452
1729 #define CHIP_NUM_57454		0xc454
1730 
1731 #define CHIP_NUM_57508		0x1750
1732 #define CHIP_NUM_57504		0x1751
1733 #define CHIP_NUM_57502		0x1752
1734 
1735 #define CHIP_NUM_58802		0xd802
1736 #define CHIP_NUM_58804		0xd804
1737 #define CHIP_NUM_58808		0xd808
1738 
1739 	u8			chip_rev;
1740 
1741 #define CHIP_NUM_58818		0xd818
1742 
1743 #define BNXT_CHIP_NUM_5730X(chip_num)		\
1744 	((chip_num) >= CHIP_NUM_57301 &&	\
1745 	 (chip_num) <= CHIP_NUM_57304)
1746 
1747 #define BNXT_CHIP_NUM_5740X(chip_num)		\
1748 	(((chip_num) >= CHIP_NUM_57402 &&	\
1749 	  (chip_num) <= CHIP_NUM_57406) ||	\
1750 	 (chip_num) == CHIP_NUM_57407)
1751 
1752 #define BNXT_CHIP_NUM_5731X(chip_num)		\
1753 	((chip_num) == CHIP_NUM_57311 ||	\
1754 	 (chip_num) == CHIP_NUM_57312 ||	\
1755 	 (chip_num) == CHIP_NUM_57314 ||	\
1756 	 (chip_num) == CHIP_NUM_57317)
1757 
1758 #define BNXT_CHIP_NUM_5741X(chip_num)		\
1759 	((chip_num) >= CHIP_NUM_57412 &&	\
1760 	 (chip_num) <= CHIP_NUM_57414L)
1761 
1762 #define BNXT_CHIP_NUM_58700(chip_num)		\
1763 	 ((chip_num) == CHIP_NUM_58700)
1764 
1765 #define BNXT_CHIP_NUM_5745X(chip_num)		\
1766 	((chip_num) == CHIP_NUM_5745X ||	\
1767 	 (chip_num) == CHIP_NUM_57452 ||	\
1768 	 (chip_num) == CHIP_NUM_57454)
1769 
1770 
1771 #define BNXT_CHIP_NUM_57X0X(chip_num)		\
1772 	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1773 
1774 #define BNXT_CHIP_NUM_57X1X(chip_num)		\
1775 	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1776 
1777 #define BNXT_CHIP_NUM_588XX(chip_num)		\
1778 	((chip_num) == CHIP_NUM_58802 ||	\
1779 	 (chip_num) == CHIP_NUM_58804 ||        \
1780 	 (chip_num) == CHIP_NUM_58808)
1781 
1782 #define BNXT_VPD_FLD_LEN	32
1783 	char			board_partno[BNXT_VPD_FLD_LEN];
1784 	char			board_serialno[BNXT_VPD_FLD_LEN];
1785 
1786 	struct net_device	*dev;
1787 	struct pci_dev		*pdev;
1788 
1789 	atomic_t		intr_sem;
1790 
1791 	u32			flags;
1792 	#define BNXT_FLAG_CHIP_P5	0x1
1793 	#define BNXT_FLAG_VF		0x2
1794 	#define BNXT_FLAG_LRO		0x4
1795 #ifdef CONFIG_INET
1796 	#define BNXT_FLAG_GRO		0x8
1797 #else
1798 	/* Cannot support hardware GRO if CONFIG_INET is not set */
1799 	#define BNXT_FLAG_GRO		0x0
1800 #endif
1801 	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1802 	#define BNXT_FLAG_JUMBO		0x10
1803 	#define BNXT_FLAG_STRIP_VLAN	0x20
1804 	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1805 					 BNXT_FLAG_LRO)
1806 	#define BNXT_FLAG_USING_MSIX	0x40
1807 	#define BNXT_FLAG_MSIX_CAP	0x80
1808 	#define BNXT_FLAG_RFS		0x100
1809 	#define BNXT_FLAG_SHARED_RINGS	0x200
1810 	#define BNXT_FLAG_PORT_STATS	0x400
1811 	#define BNXT_FLAG_UDP_RSS_CAP	0x800
1812 	#define BNXT_FLAG_NEW_RSS_CAP	0x2000
1813 	#define BNXT_FLAG_WOL_CAP	0x4000
1814 	#define BNXT_FLAG_ROCEV1_CAP	0x8000
1815 	#define BNXT_FLAG_ROCEV2_CAP	0x10000
1816 	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\
1817 					 BNXT_FLAG_ROCEV2_CAP)
1818 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000
1819 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000
1820 	#define BNXT_FLAG_CHIP_SR2	0x80000
1821 	#define BNXT_FLAG_MULTI_HOST	0x100000
1822 	#define BNXT_FLAG_DSN_VALID	0x200000
1823 	#define BNXT_FLAG_DOUBLE_DB	0x400000
1824 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000
1825 	#define BNXT_FLAG_DIM		0x2000000
1826 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000
1827 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000
1828 
1829 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\
1830 					    BNXT_FLAG_RFS |		\
1831 					    BNXT_FLAG_STRIP_VLAN)
1832 
1833 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1834 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1835 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1836 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1837 #define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1838 #define BNXT_SH_PORT_CFG_OK(bp)	(BNXT_PF(bp) &&				\
1839 				 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1840 #define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\
1841 				  BNXT_SH_PORT_CFG_OK(bp)) &&		\
1842 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1843 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1844 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1845 #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\
1846 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1847 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1848 #define BNXT_RX_JUMBO_MODE(bp)	((bp)->flags & BNXT_FLAG_JUMBO)
1849 
1850 #define BNXT_CHIP_SR2(bp)			\
1851 	((bp)->chip_num == CHIP_NUM_58818)
1852 
1853 #define BNXT_CHIP_P5_THOR(bp)			\
1854 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1855 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1856 	 (bp)->chip_num == CHIP_NUM_57502)
1857 
1858 /* Chip class phase 5 */
1859 #define BNXT_CHIP_P5(bp)			\
1860 	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1861 
1862 /* Chip class phase 4.x */
1863 #define BNXT_CHIP_P4(bp)			\
1864 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1865 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1866 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1867 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1868 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1869 
1870 #define BNXT_CHIP_P4_PLUS(bp)			\
1871 	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1872 
1873 	struct bnxt_en_dev	*edev;
1874 
1875 	struct bnxt_napi	**bnapi;
1876 
1877 	struct bnxt_rx_ring_info	*rx_ring;
1878 	struct bnxt_tx_ring_info	*tx_ring;
1879 	u16			*tx_ring_map;
1880 
1881 	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,
1882 					    struct sk_buff *);
1883 
1884 	struct sk_buff *	(*rx_skb_func)(struct bnxt *,
1885 					       struct bnxt_rx_ring_info *,
1886 					       u16, void *, u8 *, dma_addr_t,
1887 					       unsigned int);
1888 
1889 	u16			max_tpa_v2;
1890 	u16			max_tpa;
1891 	u32			rx_buf_size;
1892 	u32			rx_buf_use_size;	/* useable size */
1893 	u16			rx_offset;
1894 	u16			rx_dma_offset;
1895 	enum dma_data_direction	rx_dir;
1896 	u32			rx_ring_size;
1897 	u32			rx_agg_ring_size;
1898 	u32			rx_copy_thresh;
1899 	u32			rx_ring_mask;
1900 	u32			rx_agg_ring_mask;
1901 	int			rx_nr_pages;
1902 	int			rx_agg_nr_pages;
1903 	int			rx_nr_rings;
1904 	int			rsscos_nr_ctxs;
1905 
1906 	u32			tx_ring_size;
1907 	u32			tx_ring_mask;
1908 	int			tx_nr_pages;
1909 	int			tx_nr_rings;
1910 	int			tx_nr_rings_per_tc;
1911 	int			tx_nr_rings_xdp;
1912 
1913 	int			tx_wake_thresh;
1914 	int			tx_push_thresh;
1915 	int			tx_push_size;
1916 
1917 	u32			cp_ring_size;
1918 	u32			cp_ring_mask;
1919 	u32			cp_bit;
1920 	int			cp_nr_pages;
1921 	int			cp_nr_rings;
1922 
1923 	/* grp_info indexed by completion ring index */
1924 	struct bnxt_ring_grp_info	*grp_info;
1925 	struct bnxt_vnic_info	*vnic_info;
1926 	int			nr_vnics;
1927 	u16			*rss_indir_tbl;
1928 	u16			rss_indir_tbl_entries;
1929 	u32			rss_hash_cfg;
1930 
1931 	u16			max_mtu;
1932 	u8			max_tc;
1933 	u8			max_lltc;	/* lossless TCs */
1934 	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];
1935 	u8			tc_to_qidx[BNXT_MAX_QUEUE];
1936 	u8			q_ids[BNXT_MAX_QUEUE];
1937 	u8			max_q;
1938 
1939 	unsigned int		current_interval;
1940 #define BNXT_TIMER_INTERVAL	HZ
1941 
1942 	struct timer_list	timer;
1943 
1944 	unsigned long		state;
1945 #define BNXT_STATE_OPEN		0
1946 #define BNXT_STATE_IN_SP_TASK	1
1947 #define BNXT_STATE_READ_STATS	2
1948 #define BNXT_STATE_FW_RESET_DET 3
1949 #define BNXT_STATE_IN_FW_RESET	4
1950 #define BNXT_STATE_ABORT_ERR	5
1951 #define BNXT_STATE_FW_FATAL_COND	6
1952 #define BNXT_STATE_DRV_REGISTERED	7
1953 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	8
1954 #define BNXT_STATE_NAPI_DISABLED	9
1955 #define BNXT_STATE_L2_FILTER_RETRY	10
1956 #define BNXT_STATE_FW_ACTIVATE		11
1957 #define BNXT_STATE_RECOVER		12
1958 #define BNXT_STATE_FW_NON_FATAL_COND	13
1959 #define BNXT_STATE_FW_ACTIVATE_RESET	14
1960 #define BNXT_STATE_HALF_OPEN		15	/* For offline ethtool tests */
1961 
1962 #define BNXT_NO_FW_ACCESS(bp)					\
1963 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
1964 	 pci_channel_offline((bp)->pdev))
1965 
1966 	struct bnxt_irq	*irq_tbl;
1967 	int			total_irqs;
1968 	u8			mac_addr[ETH_ALEN];
1969 
1970 #ifdef CONFIG_BNXT_DCB
1971 	struct ieee_pfc		*ieee_pfc;
1972 	struct ieee_ets		*ieee_ets;
1973 	u8			dcbx_cap;
1974 	u8			default_pri;
1975 	u8			max_dscp_value;
1976 #endif /* CONFIG_BNXT_DCB */
1977 
1978 	u32			msg_enable;
1979 
1980 	u32			fw_cap;
1981 	#define BNXT_FW_CAP_SHORT_CMD			0x00000001
1982 	#define BNXT_FW_CAP_LLDP_AGENT			0x00000002
1983 	#define BNXT_FW_CAP_DCBX_AGENT			0x00000004
1984 	#define BNXT_FW_CAP_NEW_RM			0x00000008
1985 	#define BNXT_FW_CAP_IF_CHANGE			0x00000010
1986 	#define BNXT_FW_CAP_KONG_MB_CHNL		0x00000080
1987 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		0x00000400
1988 	#define BNXT_FW_CAP_TRUSTED_VF			0x00000800
1989 	#define BNXT_FW_CAP_ERROR_RECOVERY		0x00002000
1990 	#define BNXT_FW_CAP_PKG_VER			0x00004000
1991 	#define BNXT_FW_CAP_CFA_ADV_FLOW		0x00008000
1992 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	0x00010000
1993 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	0x00020000
1994 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		0x00040000
1995 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		0x00100000
1996 	#define BNXT_FW_CAP_HOT_RESET			0x00200000
1997 	#define BNXT_FW_CAP_PTP_RTC			0x00400000
1998 	#define BNXT_FW_CAP_RX_ALL_PKT_TS		0x00800000
1999 	#define BNXT_FW_CAP_VLAN_RX_STRIP		0x01000000
2000 	#define BNXT_FW_CAP_VLAN_TX_INSERT		0x02000000
2001 	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	0x04000000
2002 	#define BNXT_FW_CAP_LIVEPATCH			0x08000000
2003 	#define BNXT_FW_CAP_PTP_PPS			0x10000000
2004 	#define BNXT_FW_CAP_HOT_RESET_IF		0x20000000
2005 	#define BNXT_FW_CAP_RING_MONITOR		0x40000000
2006 	#define BNXT_FW_CAP_DBG_QCAPS			0x80000000
2007 
2008 	u32			fw_dbg_cap;
2009 
2010 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2011 	u32			hwrm_spec_code;
2012 	u16			hwrm_cmd_seq;
2013 	u16                     hwrm_cmd_kong_seq;
2014 	struct dma_pool		*hwrm_dma_pool;
2015 	struct hlist_head	hwrm_pending_list;
2016 
2017 	struct rtnl_link_stats64	net_stats_prev;
2018 	struct bnxt_stats_mem	port_stats;
2019 	struct bnxt_stats_mem	rx_port_stats_ext;
2020 	struct bnxt_stats_mem	tx_port_stats_ext;
2021 	u16			fw_rx_stats_ext_size;
2022 	u16			fw_tx_stats_ext_size;
2023 	u16			hw_ring_stats_size;
2024 	u8			pri2cos_idx[8];
2025 	u8			pri2cos_valid;
2026 
2027 	struct bnxt_total_ring_err_stats ring_err_stats_prev;
2028 
2029 	u16			hwrm_max_req_len;
2030 	u16			hwrm_max_ext_req_len;
2031 	unsigned int		hwrm_cmd_timeout;
2032 	unsigned int		hwrm_cmd_max_timeout;
2033 	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */
2034 	struct hwrm_ver_get_output	ver_resp;
2035 #define FW_VER_STR_LEN		32
2036 #define BC_HWRM_STR_LEN		21
2037 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2038 	char			fw_ver_str[FW_VER_STR_LEN];
2039 	char			hwrm_ver_supp[FW_VER_STR_LEN];
2040 	char			nvm_cfg_ver[FW_VER_STR_LEN];
2041 	u64			fw_ver_code;
2042 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\
2043 	((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2044 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
2045 
2046 	u16			vxlan_fw_dst_port_id;
2047 	u16			nge_fw_dst_port_id;
2048 	__be16			vxlan_port;
2049 	__be16			nge_port;
2050 	u8			port_partition_type;
2051 	u8			port_count;
2052 	u16			br_mode;
2053 
2054 	struct bnxt_coal_cap	coal_cap;
2055 	struct bnxt_coal	rx_coal;
2056 	struct bnxt_coal	tx_coal;
2057 
2058 	u32			stats_coal_ticks;
2059 #define BNXT_DEF_STATS_COAL_TICKS	 1000000
2060 #define BNXT_MIN_STATS_COAL_TICKS	  250000
2061 #define BNXT_MAX_STATS_COAL_TICKS	 1000000
2062 
2063 	struct work_struct	sp_task;
2064 	unsigned long		sp_event;
2065 #define BNXT_RX_MASK_SP_EVENT		0
2066 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
2067 #define BNXT_LINK_CHNG_SP_EVENT		2
2068 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
2069 #define BNXT_RESET_TASK_SP_EVENT	6
2070 #define BNXT_RST_RING_SP_EVENT		7
2071 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
2072 #define BNXT_PERIODIC_STATS_SP_EVENT	9
2073 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
2074 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
2075 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
2076 #define BNXT_FLOW_STATS_SP_EVENT	15
2077 #define BNXT_UPDATE_PHY_SP_EVENT	16
2078 #define BNXT_RING_COAL_NOW_SP_EVENT	17
2079 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
2080 #define BNXT_FW_EXCEPTION_SP_EVENT	19
2081 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
2082 #define BNXT_FW_ECHO_REQUEST_SP_EVENT	23
2083 
2084 	struct delayed_work	fw_reset_task;
2085 	int			fw_reset_state;
2086 #define BNXT_FW_RESET_STATE_POLL_VF	1
2087 #define BNXT_FW_RESET_STATE_RESET_FW	2
2088 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
2089 #define BNXT_FW_RESET_STATE_POLL_FW	4
2090 #define BNXT_FW_RESET_STATE_OPENING	5
2091 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
2092 
2093 	u16			fw_reset_min_dsecs;
2094 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
2095 	u16			fw_reset_max_dsecs;
2096 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
2097 	unsigned long		fw_reset_timestamp;
2098 
2099 	struct bnxt_fw_health	*fw_health;
2100 
2101 	struct bnxt_hw_resc	hw_resc;
2102 	struct bnxt_pf_info	pf;
2103 	struct bnxt_ctx_mem_info	*ctx;
2104 #ifdef CONFIG_BNXT_SRIOV
2105 	int			nr_vfs;
2106 	struct bnxt_vf_info	vf;
2107 	wait_queue_head_t	sriov_cfg_wait;
2108 	bool			sriov_cfg;
2109 #define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)
2110 #endif
2111 
2112 #if BITS_PER_LONG == 32
2113 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2114 	spinlock_t		db_lock;
2115 #endif
2116 	int			db_size;
2117 
2118 #define BNXT_NTP_FLTR_MAX_FLTR	4096
2119 #define BNXT_NTP_FLTR_HASH_SIZE	512
2120 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
2121 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2122 	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */
2123 
2124 	unsigned long		*ntp_fltr_bmap;
2125 	int			ntp_fltr_count;
2126 
2127 	/* To protect link related settings during link changes and
2128 	 * ethtool settings changes.
2129 	 */
2130 	struct mutex		link_lock;
2131 	struct bnxt_link_info	link_info;
2132 	struct ethtool_eee	eee;
2133 	u32			lpi_tmr_lo;
2134 	u32			lpi_tmr_hi;
2135 
2136 	/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2137 	u32			phy_flags;
2138 #define BNXT_PHY_FL_EEE_CAP		PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2139 #define BNXT_PHY_FL_EXT_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2140 #define BNXT_PHY_FL_AN_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2141 #define BNXT_PHY_FL_SHARED_PORT_CFG	PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2142 #define BNXT_PHY_FL_PORT_STATS_NO_RESET	PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2143 #define BNXT_PHY_FL_NO_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2144 #define BNXT_PHY_FL_FW_MANAGED_LKDN	PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2145 #define BNXT_PHY_FL_NO_FCS		PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2146 #define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2147 #define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2148 
2149 	u8			num_tests;
2150 	struct bnxt_test_info	*test_info;
2151 
2152 	u8			wol_filter_id;
2153 	u8			wol;
2154 
2155 	u8			num_leds;
2156 	struct bnxt_led_info	leds[BNXT_MAX_LED];
2157 	u16			dump_flag;
2158 #define BNXT_DUMP_LIVE		0
2159 #define BNXT_DUMP_CRASH		1
2160 
2161 	struct bpf_prog		*xdp_prog;
2162 
2163 	struct bnxt_ptp_cfg	*ptp_cfg;
2164 	u8			ptp_all_rx_tstamp;
2165 
2166 	/* devlink interface and vf-rep structs */
2167 	struct devlink		*dl;
2168 	struct devlink_port	dl_port;
2169 	enum devlink_eswitch_mode eswitch_mode;
2170 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
2171 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
2172 	u8			dsn[8];
2173 	struct bnxt_tc_info	*tc_info;
2174 	struct list_head	tc_indr_block_list;
2175 	struct dentry		*debugfs_pdev;
2176 	struct device		*hwmon_dev;
2177 	enum board_idx		board_idx;
2178 };
2179 
2180 #define BNXT_NUM_RX_RING_STATS			8
2181 #define BNXT_NUM_TX_RING_STATS			8
2182 #define BNXT_NUM_TPA_RING_STATS			4
2183 #define BNXT_NUM_TPA_RING_STATS_P5		5
2184 #define BNXT_NUM_TPA_RING_STATS_P5_SR2		6
2185 
2186 #define BNXT_RING_STATS_SIZE_P5					\
2187 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2188 	  BNXT_NUM_TPA_RING_STATS_P5) * 8)
2189 
2190 #define BNXT_RING_STATS_SIZE_P5_SR2				\
2191 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2192 	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2193 
2194 #define BNXT_GET_RING_STATS64(sw, counter)		\
2195 	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2196 
2197 #define BNXT_GET_RX_PORT_STATS64(sw, counter)		\
2198 	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2199 
2200 #define BNXT_GET_TX_PORT_STATS64(sw, counter)		\
2201 	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2202 
2203 #define BNXT_PORT_STATS_SIZE				\
2204 	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2205 
2206 #define BNXT_TX_PORT_STATS_BYTE_OFFSET			\
2207 	(sizeof(struct rx_port_stats) + 512)
2208 
2209 #define BNXT_RX_STATS_OFFSET(counter)			\
2210 	(offsetof(struct rx_port_stats, counter) / 8)
2211 
2212 #define BNXT_TX_STATS_OFFSET(counter)			\
2213 	((offsetof(struct tx_port_stats, counter) +	\
2214 	  BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2215 
2216 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
2217 	(offsetof(struct rx_port_stats_ext, counter) / 8)
2218 
2219 #define BNXT_RX_STATS_EXT_NUM_LEGACY                   \
2220 	BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2221 
2222 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
2223 	(offsetof(struct tx_port_stats_ext, counter) / 8)
2224 
2225 #define BNXT_HW_FEATURE_VLAN_ALL_RX				\
2226 	(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2227 #define BNXT_HW_FEATURE_VLAN_ALL_TX				\
2228 	(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2229 
2230 #define I2C_DEV_ADDR_A0				0xa0
2231 #define I2C_DEV_ADDR_A2				0xa2
2232 #define SFF_DIAG_SUPPORT_OFFSET			0x5c
2233 #define SFF_MODULE_ID_SFP			0x3
2234 #define SFF_MODULE_ID_QSFP			0xc
2235 #define SFF_MODULE_ID_QSFP_PLUS			0xd
2236 #define SFF_MODULE_ID_QSFP28			0x11
2237 #define BNXT_MAX_PHY_I2C_RESP_SIZE		64
2238 
bnxt_tx_avail(struct bnxt * bp,struct bnxt_tx_ring_info * txr)2239 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2240 {
2241 	/* Tell compiler to fetch tx indices from memory. */
2242 	barrier();
2243 
2244 	return bp->tx_ring_size -
2245 		((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2246 }
2247 
bnxt_writeq(struct bnxt * bp,u64 val,volatile void __iomem * addr)2248 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2249 			       volatile void __iomem *addr)
2250 {
2251 #if BITS_PER_LONG == 32
2252 	spin_lock(&bp->db_lock);
2253 	lo_hi_writeq(val, addr);
2254 	spin_unlock(&bp->db_lock);
2255 #else
2256 	writeq(val, addr);
2257 #endif
2258 }
2259 
bnxt_writeq_relaxed(struct bnxt * bp,u64 val,volatile void __iomem * addr)2260 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2261 				       volatile void __iomem *addr)
2262 {
2263 #if BITS_PER_LONG == 32
2264 	spin_lock(&bp->db_lock);
2265 	lo_hi_writeq_relaxed(val, addr);
2266 	spin_unlock(&bp->db_lock);
2267 #else
2268 	writeq_relaxed(val, addr);
2269 #endif
2270 }
2271 
2272 /* For TX and RX ring doorbells with no ordering guarantee*/
bnxt_db_write_relaxed(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2273 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2274 					 struct bnxt_db_info *db, u32 idx)
2275 {
2276 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2277 		bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2278 	} else {
2279 		u32 db_val = db->db_key32 | idx;
2280 
2281 		writel_relaxed(db_val, db->doorbell);
2282 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2283 			writel_relaxed(db_val, db->doorbell);
2284 	}
2285 }
2286 
2287 /* For TX and RX ring doorbells */
bnxt_db_write(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2288 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2289 				 u32 idx)
2290 {
2291 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2292 		bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2293 	} else {
2294 		u32 db_val = db->db_key32 | idx;
2295 
2296 		writel(db_val, db->doorbell);
2297 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2298 			writel(db_val, db->doorbell);
2299 	}
2300 }
2301 
2302 /* Must hold rtnl_lock */
bnxt_sriov_cfg(struct bnxt * bp)2303 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2304 {
2305 #if defined(CONFIG_BNXT_SRIOV)
2306 	return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2307 #else
2308 	return false;
2309 #endif
2310 }
2311 
2312 extern const u16 bnxt_lhint_arr[];
2313 
2314 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2315 		       u16 prod, gfp_t gfp);
2316 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2317 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2318 void bnxt_set_tpa_flags(struct bnxt *bp);
2319 void bnxt_set_ring_params(struct bnxt *);
2320 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2321 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2322 			    int bmap_size, bool async_only);
2323 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2324 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2325 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2326 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2327 int bnxt_nq_rings_in_use(struct bnxt *bp);
2328 int bnxt_hwrm_set_coal(struct bnxt *);
2329 void bnxt_free_ctx_mem(struct bnxt *bp);
2330 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2331 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2332 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2333 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2334 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2335 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2336 void bnxt_tx_disable(struct bnxt *bp);
2337 void bnxt_tx_enable(struct bnxt *bp);
2338 void bnxt_report_link(struct bnxt *bp);
2339 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2340 int bnxt_hwrm_set_pause(struct bnxt *);
2341 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2342 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2343 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2344 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2345 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2346 int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2347 int bnxt_hwrm_fw_set_time(struct bnxt *);
2348 int bnxt_open_nic(struct bnxt *, bool, bool);
2349 int bnxt_half_open_nic(struct bnxt *bp);
2350 void bnxt_half_close_nic(struct bnxt *bp);
2351 void bnxt_reenable_sriov(struct bnxt *bp);
2352 void bnxt_close_nic(struct bnxt *, bool, bool);
2353 void bnxt_get_ring_err_stats(struct bnxt *bp,
2354 			     struct bnxt_total_ring_err_stats *stats);
2355 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2356 			 u32 *reg_buf);
2357 void bnxt_fw_exception(struct bnxt *bp);
2358 void bnxt_fw_reset(struct bnxt *bp);
2359 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2360 		     int tx_xdp);
2361 int bnxt_fw_init_one(struct bnxt *bp);
2362 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2363 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2364 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2365 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2366 int bnxt_get_port_parent_id(struct net_device *dev,
2367 			    struct netdev_phys_item_id *ppid);
2368 void bnxt_dim_work(struct work_struct *work);
2369 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2370 void bnxt_print_device_info(struct bnxt *bp);
2371 #endif
2372