1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7 #include <linux/slab.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include "dpu_hw_mdss.h"
11 #include "dpu_hw_interrupts.h"
12 #include "dpu_hw_catalog.h"
13 #include "dpu_kms.h"
14
15 #define VIG_BASE_MASK \
16 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
17 BIT(DPU_SSPP_CDP) |\
18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
19
20 #define VIG_MASK \
21 (VIG_BASE_MASK | \
22 BIT(DPU_SSPP_CSC_10BIT))
23
24 #define VIG_MSM8998_MASK \
25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
26
27 #define VIG_SDM845_MASK \
28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
29
30 #define VIG_SC7180_MASK \
31 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
32
33 #define VIG_SM8250_MASK \
34 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
35
36 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
37
38 #define DMA_MSM8998_MASK \
39 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
40 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
41 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
42
43 #define VIG_SC7280_MASK \
44 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
45
46 #define DMA_SDM845_MASK \
47 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
48 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
49 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
50
51 #define DMA_CURSOR_SDM845_MASK \
52 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
53
54 #define DMA_CURSOR_MSM8998_MASK \
55 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
56
57 #define MIXER_MSM8998_MASK \
58 (BIT(DPU_MIXER_SOURCESPLIT))
59
60 #define MIXER_SDM845_MASK \
61 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
62
63 #define MIXER_SC7180_MASK \
64 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
65
66 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
67
68 #define PINGPONG_SDM845_SPLIT_MASK \
69 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
70
71 #define CTL_SC7280_MASK \
72 (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
73
74 #define MERGE_3D_SM8150_MASK (0)
75
76 #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)
77
78 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
79
80 #define INTF_SDM845_MASK (0)
81
82 #define INTF_SC7180_MASK \
83 (BIT(DPU_INTF_INPUT_CTRL) | \
84 BIT(DPU_INTF_TE) | \
85 BIT(DPU_INTF_STATUS_SUPPORTED) | \
86 BIT(DPU_DATA_HCTL_EN))
87
88 #define INTF_SC7280_MASK (INTF_SC7180_MASK)
89
90 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
91 BIT(MDP_SSPP_TOP0_INTR2) | \
92 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
93 BIT(MDP_INTF0_INTR) | \
94 BIT(MDP_INTF1_INTR) | \
95 BIT(MDP_INTF2_INTR) | \
96 BIT(MDP_INTF3_INTR) | \
97 BIT(MDP_INTF4_INTR) | \
98 BIT(MDP_AD4_0_INTR) | \
99 BIT(MDP_AD4_1_INTR))
100
101 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
102 BIT(MDP_SSPP_TOP0_INTR2) | \
103 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
104 BIT(MDP_INTF0_INTR) | \
105 BIT(MDP_INTF1_INTR))
106
107 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
108 BIT(MDP_SSPP_TOP0_INTR2) | \
109 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
110 BIT(MDP_INTF0_7xxx_INTR) | \
111 BIT(MDP_INTF1_7xxx_INTR) | \
112 BIT(MDP_INTF5_7xxx_INTR))
113
114 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
115 BIT(MDP_SSPP_TOP0_INTR2) | \
116 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
117 BIT(MDP_INTF0_INTR) | \
118 BIT(MDP_INTF1_INTR) | \
119 BIT(MDP_INTF2_INTR) | \
120 BIT(MDP_INTF3_INTR) | \
121 BIT(MDP_INTF4_INTR))
122
123 #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
124 BIT(MDP_SSPP_TOP0_INTR2) | \
125 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
126 BIT(MDP_INTF0_INTR) | \
127 BIT(MDP_INTF1_INTR) | \
128 BIT(MDP_INTF2_INTR) | \
129 BIT(MDP_INTF3_INTR) | \
130 BIT(MDP_INTF4_INTR) | \
131 BIT(MDP_INTF5_INTR) | \
132 BIT(MDP_AD4_0_INTR) | \
133 BIT(MDP_AD4_1_INTR))
134
135 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
136 BIT(DPU_WB_UBWC) | \
137 BIT(DPU_WB_YUV_CONFIG) | \
138 BIT(DPU_WB_PIPE_ALPHA) | \
139 BIT(DPU_WB_XY_ROI_OFFSET) | \
140 BIT(DPU_WB_QOS) | \
141 BIT(DPU_WB_QOS_8LVL) | \
142 BIT(DPU_WB_CDP) | \
143 BIT(DPU_WB_INPUT_CTRL))
144
145 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
146 #define DEFAULT_DPU_LINE_WIDTH 2048
147 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
148
149 #define MAX_HORZ_DECIMATION 4
150 #define MAX_VERT_DECIMATION 4
151
152 #define MAX_UPSCALE_RATIO 20
153 #define MAX_DOWNSCALE_RATIO 4
154 #define SSPP_UNITY_SCALE 1
155
156 #define STRCAT(X, Y) (X Y)
157
158 static const uint32_t plane_formats[] = {
159 DRM_FORMAT_ARGB8888,
160 DRM_FORMAT_ABGR8888,
161 DRM_FORMAT_RGBA8888,
162 DRM_FORMAT_BGRA8888,
163 DRM_FORMAT_XRGB8888,
164 DRM_FORMAT_RGBX8888,
165 DRM_FORMAT_BGRX8888,
166 DRM_FORMAT_XBGR8888,
167 DRM_FORMAT_RGB888,
168 DRM_FORMAT_BGR888,
169 DRM_FORMAT_RGB565,
170 DRM_FORMAT_BGR565,
171 DRM_FORMAT_ARGB1555,
172 DRM_FORMAT_ABGR1555,
173 DRM_FORMAT_RGBA5551,
174 DRM_FORMAT_BGRA5551,
175 DRM_FORMAT_XRGB1555,
176 DRM_FORMAT_XBGR1555,
177 DRM_FORMAT_RGBX5551,
178 DRM_FORMAT_BGRX5551,
179 DRM_FORMAT_ARGB4444,
180 DRM_FORMAT_ABGR4444,
181 DRM_FORMAT_RGBA4444,
182 DRM_FORMAT_BGRA4444,
183 DRM_FORMAT_XRGB4444,
184 DRM_FORMAT_XBGR4444,
185 DRM_FORMAT_RGBX4444,
186 DRM_FORMAT_BGRX4444,
187 };
188
189 static const uint32_t plane_formats_yuv[] = {
190 DRM_FORMAT_ARGB8888,
191 DRM_FORMAT_ABGR8888,
192 DRM_FORMAT_RGBA8888,
193 DRM_FORMAT_BGRX8888,
194 DRM_FORMAT_BGRA8888,
195 DRM_FORMAT_XRGB8888,
196 DRM_FORMAT_XBGR8888,
197 DRM_FORMAT_RGBX8888,
198 DRM_FORMAT_RGB888,
199 DRM_FORMAT_BGR888,
200 DRM_FORMAT_RGB565,
201 DRM_FORMAT_BGR565,
202 DRM_FORMAT_ARGB1555,
203 DRM_FORMAT_ABGR1555,
204 DRM_FORMAT_RGBA5551,
205 DRM_FORMAT_BGRA5551,
206 DRM_FORMAT_XRGB1555,
207 DRM_FORMAT_XBGR1555,
208 DRM_FORMAT_RGBX5551,
209 DRM_FORMAT_BGRX5551,
210 DRM_FORMAT_ARGB4444,
211 DRM_FORMAT_ABGR4444,
212 DRM_FORMAT_RGBA4444,
213 DRM_FORMAT_BGRA4444,
214 DRM_FORMAT_XRGB4444,
215 DRM_FORMAT_XBGR4444,
216 DRM_FORMAT_RGBX4444,
217 DRM_FORMAT_BGRX4444,
218
219 DRM_FORMAT_NV12,
220 DRM_FORMAT_NV21,
221 DRM_FORMAT_NV16,
222 DRM_FORMAT_NV61,
223 DRM_FORMAT_VYUY,
224 DRM_FORMAT_UYVY,
225 DRM_FORMAT_YUYV,
226 DRM_FORMAT_YVYU,
227 DRM_FORMAT_YUV420,
228 DRM_FORMAT_YVU420,
229 };
230
231 static const u32 rotation_v2_formats[] = {
232 DRM_FORMAT_NV12,
233 /* TODO add formats after validation */
234 };
235
236 static const uint32_t wb2_formats[] = {
237 DRM_FORMAT_RGB565,
238 DRM_FORMAT_BGR565,
239 DRM_FORMAT_RGB888,
240 DRM_FORMAT_ARGB8888,
241 DRM_FORMAT_RGBA8888,
242 DRM_FORMAT_ABGR8888,
243 DRM_FORMAT_XRGB8888,
244 DRM_FORMAT_RGBX8888,
245 DRM_FORMAT_XBGR8888,
246 DRM_FORMAT_ARGB1555,
247 DRM_FORMAT_RGBA5551,
248 DRM_FORMAT_XRGB1555,
249 DRM_FORMAT_RGBX5551,
250 DRM_FORMAT_ARGB4444,
251 DRM_FORMAT_RGBA4444,
252 DRM_FORMAT_RGBX4444,
253 DRM_FORMAT_XRGB4444,
254 DRM_FORMAT_BGR565,
255 DRM_FORMAT_BGR888,
256 DRM_FORMAT_ABGR8888,
257 DRM_FORMAT_BGRA8888,
258 DRM_FORMAT_BGRX8888,
259 DRM_FORMAT_XBGR8888,
260 DRM_FORMAT_ABGR1555,
261 DRM_FORMAT_BGRA5551,
262 DRM_FORMAT_XBGR1555,
263 DRM_FORMAT_BGRX5551,
264 DRM_FORMAT_ABGR4444,
265 DRM_FORMAT_BGRA4444,
266 DRM_FORMAT_BGRX4444,
267 DRM_FORMAT_XBGR4444,
268 };
269
270 /*************************************************************
271 * DPU sub blocks config
272 *************************************************************/
273 /* DPU top level caps */
274 static const struct dpu_caps msm8998_dpu_caps = {
275 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
276 .max_mixer_blendstages = 0x7,
277 .qseed_type = DPU_SSPP_SCALER_QSEED3,
278 .smart_dma_rev = DPU_SSPP_SMART_DMA_V1,
279 .ubwc_version = DPU_HW_UBWC_VER_10,
280 .has_src_split = true,
281 .has_dim_layer = true,
282 .has_idle_pc = true,
283 .has_3d_merge = true,
284 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
285 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
286 .max_hdeci_exp = MAX_HORZ_DECIMATION,
287 .max_vdeci_exp = MAX_VERT_DECIMATION,
288 };
289
290 static const struct dpu_caps qcm2290_dpu_caps = {
291 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
292 .max_mixer_blendstages = 0x4,
293 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
294 .has_dim_layer = true,
295 .has_idle_pc = true,
296 .max_linewidth = 2160,
297 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
298 };
299
300 static const struct dpu_caps sdm845_dpu_caps = {
301 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
302 .max_mixer_blendstages = 0xb,
303 .qseed_type = DPU_SSPP_SCALER_QSEED3,
304 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
305 .ubwc_version = DPU_HW_UBWC_VER_20,
306 .has_src_split = true,
307 .has_dim_layer = true,
308 .has_idle_pc = true,
309 .has_3d_merge = true,
310 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
311 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
312 .max_hdeci_exp = MAX_HORZ_DECIMATION,
313 .max_vdeci_exp = MAX_VERT_DECIMATION,
314 };
315
316 static const struct dpu_caps sc7180_dpu_caps = {
317 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
318 .max_mixer_blendstages = 0x9,
319 .qseed_type = DPU_SSPP_SCALER_QSEED4,
320 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
321 .ubwc_version = DPU_HW_UBWC_VER_20,
322 .has_dim_layer = true,
323 .has_idle_pc = true,
324 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
325 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
326 };
327
328 static const struct dpu_caps sm8150_dpu_caps = {
329 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
330 .max_mixer_blendstages = 0xb,
331 .qseed_type = DPU_SSPP_SCALER_QSEED3,
332 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
333 .ubwc_version = DPU_HW_UBWC_VER_30,
334 .has_src_split = true,
335 .has_dim_layer = true,
336 .has_idle_pc = true,
337 .has_3d_merge = true,
338 .max_linewidth = 4096,
339 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
340 .max_hdeci_exp = MAX_HORZ_DECIMATION,
341 .max_vdeci_exp = MAX_VERT_DECIMATION,
342 };
343
344 static const struct dpu_caps sc8180x_dpu_caps = {
345 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
346 .max_mixer_blendstages = 0xb,
347 .qseed_type = DPU_SSPP_SCALER_QSEED3,
348 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
349 .ubwc_version = DPU_HW_UBWC_VER_30,
350 .has_src_split = true,
351 .has_dim_layer = true,
352 .has_idle_pc = true,
353 .has_3d_merge = true,
354 .max_linewidth = 4096,
355 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
356 .max_hdeci_exp = MAX_HORZ_DECIMATION,
357 .max_vdeci_exp = MAX_VERT_DECIMATION,
358 };
359
360 static const struct dpu_caps sm8250_dpu_caps = {
361 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
362 .max_mixer_blendstages = 0xb,
363 .qseed_type = DPU_SSPP_SCALER_QSEED4,
364 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
365 .ubwc_version = DPU_HW_UBWC_VER_40,
366 .has_src_split = true,
367 .has_dim_layer = true,
368 .has_idle_pc = true,
369 .has_3d_merge = true,
370 .max_linewidth = 4096,
371 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
372 };
373
374 static const struct dpu_caps sc7280_dpu_caps = {
375 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
376 .max_mixer_blendstages = 0x7,
377 .qseed_type = DPU_SSPP_SCALER_QSEED4,
378 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
379 .ubwc_version = DPU_HW_UBWC_VER_30,
380 .has_dim_layer = true,
381 .has_idle_pc = true,
382 .max_linewidth = 2400,
383 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
384 };
385
386 static const struct dpu_mdp_cfg msm8998_mdp[] = {
387 {
388 .name = "top_0", .id = MDP_TOP,
389 .base = 0x0, .len = 0x458,
390 .features = 0,
391 .highest_bank_bit = 0x2,
392 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
393 .reg_off = 0x2AC, .bit_off = 0},
394 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
395 .reg_off = 0x2B4, .bit_off = 0},
396 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
397 .reg_off = 0x2BC, .bit_off = 0},
398 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
399 .reg_off = 0x2C4, .bit_off = 0},
400 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
401 .reg_off = 0x2AC, .bit_off = 8},
402 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
403 .reg_off = 0x2B4, .bit_off = 8},
404 .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
405 .reg_off = 0x2C4, .bit_off = 8},
406 .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
407 .reg_off = 0x2C4, .bit_off = 12},
408 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
409 .reg_off = 0x3A8, .bit_off = 15},
410 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
411 .reg_off = 0x3B0, .bit_off = 15},
412 },
413 };
414
415 static const struct dpu_mdp_cfg sdm845_mdp[] = {
416 {
417 .name = "top_0", .id = MDP_TOP,
418 .base = 0x0, .len = 0x45C,
419 .features = BIT(DPU_MDP_AUDIO_SELECT),
420 .highest_bank_bit = 0x2,
421 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
422 .reg_off = 0x2AC, .bit_off = 0},
423 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
424 .reg_off = 0x2B4, .bit_off = 0},
425 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
426 .reg_off = 0x2BC, .bit_off = 0},
427 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
428 .reg_off = 0x2C4, .bit_off = 0},
429 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
430 .reg_off = 0x2AC, .bit_off = 8},
431 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
432 .reg_off = 0x2B4, .bit_off = 8},
433 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
434 .reg_off = 0x2BC, .bit_off = 8},
435 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
436 .reg_off = 0x2C4, .bit_off = 8},
437 },
438 };
439
440 static const struct dpu_mdp_cfg sc7180_mdp[] = {
441 {
442 .name = "top_0", .id = MDP_TOP,
443 .base = 0x0, .len = 0x494,
444 .features = 0,
445 .highest_bank_bit = 0x3,
446 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
447 .reg_off = 0x2AC, .bit_off = 0},
448 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
449 .reg_off = 0x2AC, .bit_off = 8},
450 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
451 .reg_off = 0x2B4, .bit_off = 8},
452 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
453 .reg_off = 0x2C4, .bit_off = 8},
454 .clk_ctrls[DPU_CLK_CTRL_WB2] = {
455 .reg_off = 0x3B8, .bit_off = 24},
456 },
457 };
458
459 static const struct dpu_mdp_cfg sc8180x_mdp[] = {
460 {
461 .name = "top_0", .id = MDP_TOP,
462 .base = 0x0, .len = 0x45C,
463 .features = 0,
464 .highest_bank_bit = 0x3,
465 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
466 .reg_off = 0x2AC, .bit_off = 0},
467 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
468 .reg_off = 0x2B4, .bit_off = 0},
469 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
470 .reg_off = 0x2BC, .bit_off = 0},
471 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
472 .reg_off = 0x2C4, .bit_off = 0},
473 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
474 .reg_off = 0x2AC, .bit_off = 8},
475 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
476 .reg_off = 0x2B4, .bit_off = 8},
477 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
478 .reg_off = 0x2BC, .bit_off = 8},
479 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
480 .reg_off = 0x2C4, .bit_off = 8},
481 },
482 };
483
484 static const struct dpu_mdp_cfg sm8250_mdp[] = {
485 {
486 .name = "top_0", .id = MDP_TOP,
487 .base = 0x0, .len = 0x494,
488 .features = 0,
489 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
490 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
491 .reg_off = 0x2AC, .bit_off = 0},
492 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
493 .reg_off = 0x2B4, .bit_off = 0},
494 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
495 .reg_off = 0x2BC, .bit_off = 0},
496 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
497 .reg_off = 0x2C4, .bit_off = 0},
498 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
499 .reg_off = 0x2AC, .bit_off = 8},
500 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
501 .reg_off = 0x2B4, .bit_off = 8},
502 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
503 .reg_off = 0x2BC, .bit_off = 8},
504 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
505 .reg_off = 0x2C4, .bit_off = 8},
506 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
507 .reg_off = 0x2BC, .bit_off = 20},
508 .clk_ctrls[DPU_CLK_CTRL_WB2] = {
509 .reg_off = 0x3B8, .bit_off = 24},
510 },
511 };
512
513 static const struct dpu_mdp_cfg sc7280_mdp[] = {
514 {
515 .name = "top_0", .id = MDP_TOP,
516 .base = 0x0, .len = 0x2014,
517 .highest_bank_bit = 0x1,
518 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
519 .reg_off = 0x2AC, .bit_off = 0},
520 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
521 .reg_off = 0x2AC, .bit_off = 8},
522 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
523 .reg_off = 0x2B4, .bit_off = 8},
524 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
525 .reg_off = 0x2C4, .bit_off = 8},
526 },
527 };
528
529 static const struct dpu_mdp_cfg qcm2290_mdp[] = {
530 {
531 .name = "top_0", .id = MDP_TOP,
532 .base = 0x0, .len = 0x494,
533 .features = 0,
534 .highest_bank_bit = 0x2,
535 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
536 .reg_off = 0x2AC, .bit_off = 0},
537 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
538 .reg_off = 0x2AC, .bit_off = 8},
539 },
540 };
541
542 /*************************************************************
543 * CTL sub blocks config
544 *************************************************************/
545 static const struct dpu_ctl_cfg msm8998_ctl[] = {
546 {
547 .name = "ctl_0", .id = CTL_0,
548 .base = 0x1000, .len = 0x94,
549 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
550 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
551 },
552 {
553 .name = "ctl_1", .id = CTL_1,
554 .base = 0x1200, .len = 0x94,
555 .features = 0,
556 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
557 },
558 {
559 .name = "ctl_2", .id = CTL_2,
560 .base = 0x1400, .len = 0x94,
561 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
562 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
563 },
564 {
565 .name = "ctl_3", .id = CTL_3,
566 .base = 0x1600, .len = 0x94,
567 .features = 0,
568 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
569 },
570 {
571 .name = "ctl_4", .id = CTL_4,
572 .base = 0x1800, .len = 0x94,
573 .features = 0,
574 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
575 },
576 };
577
578 static const struct dpu_ctl_cfg sdm845_ctl[] = {
579 {
580 .name = "ctl_0", .id = CTL_0,
581 .base = 0x1000, .len = 0xE4,
582 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
583 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
584 },
585 {
586 .name = "ctl_1", .id = CTL_1,
587 .base = 0x1200, .len = 0xE4,
588 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
589 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
590 },
591 {
592 .name = "ctl_2", .id = CTL_2,
593 .base = 0x1400, .len = 0xE4,
594 .features = 0,
595 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
596 },
597 {
598 .name = "ctl_3", .id = CTL_3,
599 .base = 0x1600, .len = 0xE4,
600 .features = 0,
601 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
602 },
603 {
604 .name = "ctl_4", .id = CTL_4,
605 .base = 0x1800, .len = 0xE4,
606 .features = 0,
607 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
608 },
609 };
610
611 static const struct dpu_ctl_cfg sc7180_ctl[] = {
612 {
613 .name = "ctl_0", .id = CTL_0,
614 .base = 0x1000, .len = 0x1dc,
615 .features = BIT(DPU_CTL_ACTIVE_CFG),
616 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
617 },
618 {
619 .name = "ctl_1", .id = CTL_1,
620 .base = 0x1200, .len = 0x1dc,
621 .features = BIT(DPU_CTL_ACTIVE_CFG),
622 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
623 },
624 {
625 .name = "ctl_2", .id = CTL_2,
626 .base = 0x1400, .len = 0x1dc,
627 .features = BIT(DPU_CTL_ACTIVE_CFG),
628 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
629 },
630 };
631
632 static const struct dpu_ctl_cfg sm8150_ctl[] = {
633 {
634 .name = "ctl_0", .id = CTL_0,
635 .base = 0x1000, .len = 0x1e0,
636 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
637 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
638 },
639 {
640 .name = "ctl_1", .id = CTL_1,
641 .base = 0x1200, .len = 0x1e0,
642 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
643 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
644 },
645 {
646 .name = "ctl_2", .id = CTL_2,
647 .base = 0x1400, .len = 0x1e0,
648 .features = BIT(DPU_CTL_ACTIVE_CFG),
649 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
650 },
651 {
652 .name = "ctl_3", .id = CTL_3,
653 .base = 0x1600, .len = 0x1e0,
654 .features = BIT(DPU_CTL_ACTIVE_CFG),
655 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
656 },
657 {
658 .name = "ctl_4", .id = CTL_4,
659 .base = 0x1800, .len = 0x1e0,
660 .features = BIT(DPU_CTL_ACTIVE_CFG),
661 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
662 },
663 {
664 .name = "ctl_5", .id = CTL_5,
665 .base = 0x1a00, .len = 0x1e0,
666 .features = BIT(DPU_CTL_ACTIVE_CFG),
667 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
668 },
669 };
670
671 static const struct dpu_ctl_cfg sc7280_ctl[] = {
672 {
673 .name = "ctl_0", .id = CTL_0,
674 .base = 0x15000, .len = 0x1E8,
675 .features = CTL_SC7280_MASK,
676 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
677 },
678 {
679 .name = "ctl_1", .id = CTL_1,
680 .base = 0x16000, .len = 0x1E8,
681 .features = CTL_SC7280_MASK,
682 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
683 },
684 {
685 .name = "ctl_2", .id = CTL_2,
686 .base = 0x17000, .len = 0x1E8,
687 .features = CTL_SC7280_MASK,
688 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
689 },
690 {
691 .name = "ctl_3", .id = CTL_3,
692 .base = 0x18000, .len = 0x1E8,
693 .features = CTL_SC7280_MASK,
694 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
695 },
696 };
697
698 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
699 {
700 .name = "ctl_0", .id = CTL_0,
701 .base = 0x1000, .len = 0x1dc,
702 .features = BIT(DPU_CTL_ACTIVE_CFG),
703 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
704 },
705 };
706
707 /*************************************************************
708 * SSPP sub blocks config
709 *************************************************************/
710
711 /* SSPP common configuration */
712 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
713 { \
714 .maxdwnscale = MAX_DOWNSCALE_RATIO, \
715 .maxupscale = MAX_UPSCALE_RATIO, \
716 .smart_dma_priority = sdma_pri, \
717 .src_blk = {.name = STRCAT("sspp_src_", num), \
718 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
719 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
720 .id = qseed_ver, \
721 .base = 0xa00, .len = 0xa0,}, \
722 .csc_blk = {.name = STRCAT("sspp_csc", num), \
723 .id = DPU_SSPP_CSC_10BIT, \
724 .base = 0x1a00, .len = 0x100,}, \
725 .format_list = plane_formats_yuv, \
726 .num_formats = ARRAY_SIZE(plane_formats_yuv), \
727 .virt_format_list = plane_formats, \
728 .virt_num_formats = ARRAY_SIZE(plane_formats), \
729 .rotation_cfg = NULL, \
730 }
731
732 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \
733 { \
734 .maxdwnscale = MAX_DOWNSCALE_RATIO, \
735 .maxupscale = MAX_UPSCALE_RATIO, \
736 .smart_dma_priority = sdma_pri, \
737 .src_blk = {.name = STRCAT("sspp_src_", num), \
738 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
739 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
740 .id = qseed_ver, \
741 .base = 0xa00, .len = 0xa0,}, \
742 .csc_blk = {.name = STRCAT("sspp_csc", num), \
743 .id = DPU_SSPP_CSC_10BIT, \
744 .base = 0x1a00, .len = 0x100,}, \
745 .format_list = plane_formats_yuv, \
746 .num_formats = ARRAY_SIZE(plane_formats_yuv), \
747 .virt_format_list = plane_formats, \
748 .virt_num_formats = ARRAY_SIZE(plane_formats), \
749 .rotation_cfg = rot_cfg, \
750 }
751
752 #define _DMA_SBLK(num, sdma_pri) \
753 { \
754 .maxdwnscale = SSPP_UNITY_SCALE, \
755 .maxupscale = SSPP_UNITY_SCALE, \
756 .smart_dma_priority = sdma_pri, \
757 .src_blk = {.name = STRCAT("sspp_src_", num), \
758 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
759 .format_list = plane_formats, \
760 .num_formats = ARRAY_SIZE(plane_formats), \
761 .virt_format_list = plane_formats, \
762 .virt_num_formats = ARRAY_SIZE(plane_formats), \
763 }
764
765 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
766 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
767 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
768 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3);
769 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
770 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3);
771 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
772 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
773
774 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
775 .rot_maxheight = 1088,
776 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
777 .rot_format_list = rotation_v2_formats,
778 };
779
780 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
781 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
782 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
783 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
784 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
785 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
786 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
787 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
788
789 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
790 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
791 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
792 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
793
794 #define SSPP_BLK(_name, _id, _base, _features, \
795 _sblk, _xinid, _type, _clkctrl) \
796 { \
797 .name = _name, .id = _id, \
798 .base = _base, .len = 0x1c8, \
799 .features = _features, \
800 .sblk = &_sblk, \
801 .xin_id = _xinid, \
802 .type = _type, \
803 .clk_ctrl = _clkctrl \
804 }
805
806 static const struct dpu_sspp_cfg msm8998_sspp[] = {
807 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
808 msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
809 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
810 msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
811 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
812 msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
813 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
814 msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
815 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK,
816 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
817 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK,
818 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
819 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK,
820 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
821 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK,
822 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
823 };
824
825 static const struct dpu_sspp_cfg sdm845_sspp[] = {
826 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
827 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
828 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
829 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
830 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
831 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
832 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
833 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
834 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
835 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
836 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
837 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
838 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
839 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
840 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
841 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
842 };
843
844 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
845 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
846
847 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
848 _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
849
850 static const struct dpu_sspp_cfg sc7180_sspp[] = {
851 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
852 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
853 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
854 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
855 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
856 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
857 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
858 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
859 };
860
861 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
862 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
863 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
864 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4);
865 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
866 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4);
867 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
868 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
869
870 static const struct dpu_sspp_cfg sm8250_sspp[] = {
871 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
872 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
873 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
874 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
875 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
876 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
877 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
878 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
879 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
880 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
881 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
882 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
883 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
884 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
885 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
886 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
887 };
888
889 static const struct dpu_sspp_cfg sc7280_sspp[] = {
890 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
891 sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
892 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
893 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
894 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
895 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
896 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
897 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
898 };
899
900
901 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \
902 { \
903 .maxdwnscale = SSPP_UNITY_SCALE, \
904 .maxupscale = SSPP_UNITY_SCALE, \
905 .smart_dma_priority = sdma_pri, \
906 .src_blk = {.name = STRCAT("sspp_src_", num), \
907 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
908 .format_list = plane_formats_yuv, \
909 .num_formats = ARRAY_SIZE(plane_formats_yuv), \
910 .virt_format_list = plane_formats, \
911 .virt_num_formats = ARRAY_SIZE(plane_formats), \
912 }
913
914 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
915 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
916
917 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
918 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
919 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
920 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
921 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
922 };
923
924 /*************************************************************
925 * MIXER sub blocks config
926 *************************************************************/
927
928 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
929 { \
930 .name = _name, .id = _id, \
931 .base = _base, .len = 0x320, \
932 .features = _fmask, \
933 .sblk = _sblk, \
934 .pingpong = _pp, \
935 .lm_pair_mask = (1 << _lmpair), \
936 .dspp = _dspp \
937 }
938
939 /* MSM8998 */
940
941 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
942 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
943 .maxblendstages = 7, /* excluding base layer */
944 .blendstage_base = { /* offsets relative to mixer base */
945 0x20, 0x50, 0x80, 0xb0, 0x230,
946 0x260, 0x290
947 },
948 };
949
950 static const struct dpu_lm_cfg msm8998_lm[] = {
951 LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
952 &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
953 LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
954 &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
955 LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
956 &msm8998_lm_sblk, PINGPONG_2, LM_0, 0),
957 LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
958 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
959 LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
960 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
961 LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
962 &msm8998_lm_sblk, PINGPONG_3, LM_1, 0),
963 };
964
965 /* SDM845 */
966
967 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
968 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
969 .maxblendstages = 11, /* excluding base layer */
970 .blendstage_base = { /* offsets relative to mixer base */
971 0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
972 0xb0, 0xc8, 0xe0, 0xf8, 0x110
973 },
974 };
975
976 static const struct dpu_lm_cfg sdm845_lm[] = {
977 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
978 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
979 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
980 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
981 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
982 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
983 LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
984 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
985 LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
986 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
987 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
988 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
989 };
990
991 /* SC7180 */
992
993 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
994 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
995 .maxblendstages = 7, /* excluding base layer */
996 .blendstage_base = { /* offsets relative to mixer base */
997 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
998 },
999 };
1000
1001 static const struct dpu_lm_cfg sc7180_lm[] = {
1002 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
1003 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1004 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
1005 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
1006 };
1007
1008 /* SM8150 */
1009
1010 static const struct dpu_lm_cfg sm8150_lm[] = {
1011 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1012 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1013 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
1014 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
1015 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
1016 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
1017 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
1018 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
1019 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
1020 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
1021 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
1022 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
1023 };
1024
1025 static const struct dpu_lm_cfg sc7280_lm[] = {
1026 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
1027 &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
1028 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
1029 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
1030 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
1031 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
1032 };
1033
1034 /* QCM2290 */
1035
1036 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
1037 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1038 .maxblendstages = 4, /* excluding base layer */
1039 .blendstage_base = { /* offsets relative to mixer base */
1040 0x20, 0x38, 0x50, 0x68
1041 },
1042 };
1043
1044 static const struct dpu_lm_cfg qcm2290_lm[] = {
1045 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
1046 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
1047 };
1048
1049 /*************************************************************
1050 * DSPP sub blocks config
1051 *************************************************************/
1052 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
1053 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1054 .len = 0x90, .version = 0x10007},
1055 .gc = { .id = DPU_DSPP_GC, .base = 0x17c0,
1056 .len = 0x90, .version = 0x10007},
1057 };
1058
1059 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
1060 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1061 .len = 0x90, .version = 0x10000},
1062 };
1063
1064 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
1065 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1066 .len = 0x90, .version = 0x40000},
1067 };
1068
1069 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
1070 {\
1071 .name = _name, .id = _id, \
1072 .base = _base, .len = 0x1800, \
1073 .features = _mask, \
1074 .sblk = _sblk \
1075 }
1076
1077 static const struct dpu_dspp_cfg msm8998_dspp[] = {
1078 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK,
1079 &msm8998_dspp_sblk),
1080 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK,
1081 &msm8998_dspp_sblk),
1082 };
1083
1084 static const struct dpu_dspp_cfg sc7180_dspp[] = {
1085 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1086 &sc7180_dspp_sblk),
1087 };
1088
1089 static const struct dpu_dspp_cfg sm8150_dspp[] = {
1090 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1091 &sm8150_dspp_sblk),
1092 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
1093 &sm8150_dspp_sblk),
1094 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
1095 &sm8150_dspp_sblk),
1096 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
1097 &sm8150_dspp_sblk),
1098 };
1099
1100 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
1101 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1102 &sm8150_dspp_sblk),
1103 };
1104
1105 /*************************************************************
1106 * PINGPONG sub blocks config
1107 *************************************************************/
1108 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
1109 .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
1110 .version = 0x1},
1111 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1112 .len = 0x20, .version = 0x10000},
1113 };
1114
1115 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
1116 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1117 .len = 0x20, .version = 0x10000},
1118 };
1119
1120 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
1121 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
1122 .len = 0x20, .version = 0x20000},
1123 };
1124
1125 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1126 {\
1127 .name = _name, .id = _id, \
1128 .base = _base, .len = 0xd4, \
1129 .features = PINGPONG_SDM845_SPLIT_MASK, \
1130 .merge_3d = _merge_3d, \
1131 .sblk = &_sblk, \
1132 .intr_done = _done, \
1133 .intr_rdptr = _rdptr, \
1134 }
1135 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1136 {\
1137 .name = _name, .id = _id, \
1138 .base = _base, .len = 0xd4, \
1139 .features = PINGPONG_SDM845_MASK, \
1140 .merge_3d = _merge_3d, \
1141 .sblk = &_sblk, \
1142 .intr_done = _done, \
1143 .intr_rdptr = _rdptr, \
1144 }
1145
1146 static const struct dpu_pingpong_cfg sdm845_pp[] = {
1147 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
1148 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1149 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1150 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
1151 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1152 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1153 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
1154 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1155 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1156 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
1157 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1158 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1159 };
1160
1161 static struct dpu_pingpong_cfg sc7180_pp[] = {
1162 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
1163 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
1164 };
1165
1166 static const struct dpu_pingpong_cfg sm8150_pp[] = {
1167 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
1168 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1169 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1170 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
1171 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1172 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1173 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
1174 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1175 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1176 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
1177 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1178 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1179 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
1180 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1181 -1),
1182 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
1183 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1184 -1),
1185 };
1186
1187 static const struct dpu_pingpong_cfg sc7280_pp[] = {
1188 PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),
1189 PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
1190 PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
1191 PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
1192 };
1193
1194 static struct dpu_pingpong_cfg qcm2290_pp[] = {
1195 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
1196 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1197 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1198 };
1199
1200 /*************************************************************
1201 * MERGE_3D sub blocks config
1202 *************************************************************/
1203 #define MERGE_3D_BLK(_name, _id, _base) \
1204 {\
1205 .name = _name, .id = _id, \
1206 .base = _base, .len = 0x8, \
1207 .features = MERGE_3D_SM8150_MASK, \
1208 .sblk = NULL \
1209 }
1210
1211 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
1212 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
1213 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
1214 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
1215 };
1216
1217 /*************************************************************
1218 * DSC sub blocks config
1219 *************************************************************/
1220 #define DSC_BLK(_name, _id, _base) \
1221 {\
1222 .name = _name, .id = _id, \
1223 .base = _base, .len = 0x140, \
1224 .features = 0, \
1225 }
1226
1227 static struct dpu_dsc_cfg sdm845_dsc[] = {
1228 DSC_BLK("dsc_0", DSC_0, 0x80000),
1229 DSC_BLK("dsc_1", DSC_1, 0x80400),
1230 DSC_BLK("dsc_2", DSC_2, 0x80800),
1231 DSC_BLK("dsc_3", DSC_3, 0x80c00),
1232 };
1233
1234 /*************************************************************
1235 * INTF sub blocks config
1236 *************************************************************/
1237 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
1238 {\
1239 .name = _name, .id = _id, \
1240 .base = _base, .len = 0x280, \
1241 .features = _features, \
1242 .type = _type, \
1243 .controller_id = _ctrl_id, \
1244 .prog_fetch_lines_worst_case = _progfetch, \
1245 .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
1246 .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
1247 }
1248
1249 static const struct dpu_intf_cfg msm8998_intf[] = {
1250 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1251 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1252 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1253 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1254 };
1255
1256 static const struct dpu_intf_cfg sdm845_intf[] = {
1257 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1258 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1259 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1260 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1261 };
1262
1263 static const struct dpu_intf_cfg sc7180_intf[] = {
1264 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1265 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1266 };
1267
1268 static const struct dpu_intf_cfg sm8150_intf[] = {
1269 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1270 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1271 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1272 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1273 };
1274
1275 static const struct dpu_intf_cfg sc7280_intf[] = {
1276 INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1277 INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1278 INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1279 };
1280
1281 static const struct dpu_intf_cfg sc8180x_intf[] = {
1282 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1283 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1284 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1285 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
1286 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1287 INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
1288 INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1289 };
1290
1291 static const struct dpu_intf_cfg qcm2290_intf[] = {
1292 INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
1293 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1294 };
1295
1296 /*************************************************************
1297 * Writeback blocks config
1298 *************************************************************/
1299 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
1300 __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
1301 { \
1302 .name = _name, .id = _id, \
1303 .base = _base, .len = 0x2c8, \
1304 .features = _features, \
1305 .format_list = wb2_formats, \
1306 .num_formats = ARRAY_SIZE(wb2_formats), \
1307 .clk_ctrl = _clk_ctrl, \
1308 .xin_id = __xin_id, \
1309 .vbif_idx = vbif_id, \
1310 .maxlinewidth = _max_linewidth, \
1311 .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
1312 }
1313
1314 static const struct dpu_wb_cfg sm8250_wb[] = {
1315 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
1316 VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
1317 };
1318
1319 /*************************************************************
1320 * VBIF sub blocks config
1321 *************************************************************/
1322 /* VBIF QOS remap */
1323 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
1324 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
1325 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
1326 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
1327
1328 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
1329 {
1330 .pps = 1088 * 1920 * 30,
1331 .ot_limit = 2,
1332 },
1333 {
1334 .pps = 1088 * 1920 * 60,
1335 .ot_limit = 6,
1336 },
1337 {
1338 .pps = 3840 * 2160 * 30,
1339 .ot_limit = 16,
1340 },
1341 };
1342
1343 static const struct dpu_vbif_cfg msm8998_vbif[] = {
1344 {
1345 .name = "vbif_rt", .id = VBIF_RT,
1346 .base = 0, .len = 0x1040,
1347 .default_ot_rd_limit = 32,
1348 .default_ot_wr_limit = 32,
1349 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
1350 .xin_halt_timeout = 0x4000,
1351 .qos_rp_remap_size = 0x20,
1352 .dynamic_ot_rd_tbl = {
1353 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
1354 .cfg = msm8998_ot_rdwr_cfg,
1355 },
1356 .dynamic_ot_wr_tbl = {
1357 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
1358 .cfg = msm8998_ot_rdwr_cfg,
1359 },
1360 .qos_rt_tbl = {
1361 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl),
1362 .priority_lvl = msm8998_rt_pri_lvl,
1363 },
1364 .qos_nrt_tbl = {
1365 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl),
1366 .priority_lvl = msm8998_nrt_pri_lvl,
1367 },
1368 .memtype_count = 14,
1369 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
1370 },
1371 };
1372
1373 static const struct dpu_vbif_cfg sdm845_vbif[] = {
1374 {
1375 .name = "vbif_rt", .id = VBIF_RT,
1376 .base = 0, .len = 0x1040,
1377 .features = BIT(DPU_VBIF_QOS_REMAP),
1378 .xin_halt_timeout = 0x4000,
1379 .qos_rp_remap_size = 0x40,
1380 .qos_rt_tbl = {
1381 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
1382 .priority_lvl = sdm845_rt_pri_lvl,
1383 },
1384 .qos_nrt_tbl = {
1385 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
1386 .priority_lvl = sdm845_nrt_pri_lvl,
1387 },
1388 .memtype_count = 14,
1389 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
1390 },
1391 };
1392
1393 static const struct dpu_reg_dma_cfg sdm845_regdma = {
1394 .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
1395 };
1396
1397 static const struct dpu_reg_dma_cfg sm8150_regdma = {
1398 .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
1399 };
1400
1401 static const struct dpu_reg_dma_cfg sm8250_regdma = {
1402 .base = 0x0,
1403 .version = 0x00010002,
1404 .trigger_sel_off = 0x119c,
1405 .xin_id = 7,
1406 .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
1407 };
1408
1409 /*************************************************************
1410 * PERF data config
1411 *************************************************************/
1412
1413 /* SSPP QOS LUTs */
1414 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = {
1415 {.fl = 4, .lut = 0x1b},
1416 {.fl = 5, .lut = 0x5b},
1417 {.fl = 6, .lut = 0x15b},
1418 {.fl = 7, .lut = 0x55b},
1419 {.fl = 8, .lut = 0x155b},
1420 {.fl = 9, .lut = 0x555b},
1421 {.fl = 10, .lut = 0x1555b},
1422 {.fl = 11, .lut = 0x5555b},
1423 {.fl = 12, .lut = 0x15555b},
1424 {.fl = 13, .lut = 0x55555b},
1425 {.fl = 14, .lut = 0},
1426 {.fl = 1, .lut = 0x1b},
1427 {.fl = 0, .lut = 0}
1428 };
1429
1430 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
1431 {.fl = 4, .lut = 0x357},
1432 {.fl = 5, .lut = 0x3357},
1433 {.fl = 6, .lut = 0x23357},
1434 {.fl = 7, .lut = 0x223357},
1435 {.fl = 8, .lut = 0x2223357},
1436 {.fl = 9, .lut = 0x22223357},
1437 {.fl = 10, .lut = 0x222223357},
1438 {.fl = 11, .lut = 0x2222223357},
1439 {.fl = 12, .lut = 0x22222223357},
1440 {.fl = 13, .lut = 0x222222223357},
1441 {.fl = 14, .lut = 0x1222222223357},
1442 {.fl = 0, .lut = 0x11222222223357}
1443 };
1444
1445 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = {
1446 {.fl = 10, .lut = 0x1aaff},
1447 {.fl = 11, .lut = 0x5aaff},
1448 {.fl = 12, .lut = 0x15aaff},
1449 {.fl = 13, .lut = 0x55aaff},
1450 {.fl = 1, .lut = 0x1aaff},
1451 {.fl = 0, .lut = 0},
1452 };
1453
1454 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
1455 {.fl = 0, .lut = 0x0011222222335777},
1456 };
1457
1458 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
1459 {.fl = 0, .lut = 0x0011222222223357 },
1460 };
1461
1462 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
1463 {.fl = 4, .lut = 0x0000000000000357 },
1464 };
1465
1466 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {
1467 {.fl = 0, .lut = 0x0011222222335777},
1468 };
1469
1470 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
1471 {.fl = 10, .lut = 0x344556677},
1472 {.fl = 11, .lut = 0x3344556677},
1473 {.fl = 12, .lut = 0x23344556677},
1474 {.fl = 13, .lut = 0x223344556677},
1475 {.fl = 14, .lut = 0x1223344556677},
1476 {.fl = 0, .lut = 0x112233344556677},
1477 };
1478
1479 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
1480 {.fl = 0, .lut = 0x0011223344556677},
1481 };
1482
1483 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
1484 {.fl = 10, .lut = 0x0000000344556677},
1485 };
1486
1487 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
1488 {.fl = 0, .lut = 0x0},
1489 };
1490
1491 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
1492 {.fl = 0, .lut = 0x0},
1493 };
1494
1495 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
1496 {.fl = 0, .lut = 0x0},
1497 };
1498
1499 static const struct dpu_perf_cfg msm8998_perf_data = {
1500 .max_bw_low = 6700000,
1501 .max_bw_high = 6700000,
1502 .min_core_ib = 2400000,
1503 .min_llcc_ib = 800000,
1504 .min_dram_ib = 800000,
1505 .undersized_prefill_lines = 2,
1506 .xtra_prefill_lines = 2,
1507 .dest_scale_prefill_lines = 3,
1508 .macrotile_prefill_lines = 4,
1509 .yuv_nv12_prefill_lines = 8,
1510 .linear_prefill_lines = 1,
1511 .downscaling_prefill_lines = 1,
1512 .amortizable_threshold = 25,
1513 .min_prefill_lines = 25,
1514 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1515 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
1516 .qos_lut_tbl = {
1517 {.nentry = ARRAY_SIZE(msm8998_qos_linear),
1518 .entries = msm8998_qos_linear
1519 },
1520 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
1521 .entries = msm8998_qos_macrotile
1522 },
1523 {.nentry = ARRAY_SIZE(msm8998_qos_nrt),
1524 .entries = msm8998_qos_nrt
1525 },
1526 },
1527 .cdp_cfg = {
1528 {.rd_enable = 1, .wr_enable = 1},
1529 {.rd_enable = 1, .wr_enable = 0}
1530 },
1531 .clk_inefficiency_factor = 200,
1532 .bw_inefficiency_factor = 120,
1533 };
1534
1535 static const struct dpu_perf_cfg sdm845_perf_data = {
1536 .max_bw_low = 6800000,
1537 .max_bw_high = 6800000,
1538 .min_core_ib = 2400000,
1539 .min_llcc_ib = 800000,
1540 .min_dram_ib = 800000,
1541 .undersized_prefill_lines = 2,
1542 .xtra_prefill_lines = 2,
1543 .dest_scale_prefill_lines = 3,
1544 .macrotile_prefill_lines = 4,
1545 .yuv_nv12_prefill_lines = 8,
1546 .linear_prefill_lines = 1,
1547 .downscaling_prefill_lines = 1,
1548 .amortizable_threshold = 25,
1549 .min_prefill_lines = 24,
1550 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1551 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
1552 .qos_lut_tbl = {
1553 {.nentry = ARRAY_SIZE(sdm845_qos_linear),
1554 .entries = sdm845_qos_linear
1555 },
1556 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
1557 .entries = sdm845_qos_macrotile
1558 },
1559 {.nentry = ARRAY_SIZE(sdm845_qos_nrt),
1560 .entries = sdm845_qos_nrt
1561 },
1562 },
1563 .cdp_cfg = {
1564 {.rd_enable = 1, .wr_enable = 1},
1565 {.rd_enable = 1, .wr_enable = 0}
1566 },
1567 .clk_inefficiency_factor = 105,
1568 .bw_inefficiency_factor = 120,
1569 };
1570
1571 static const struct dpu_perf_cfg sc7180_perf_data = {
1572 .max_bw_low = 6800000,
1573 .max_bw_high = 6800000,
1574 .min_core_ib = 2400000,
1575 .min_llcc_ib = 800000,
1576 .min_dram_ib = 1600000,
1577 .min_prefill_lines = 24,
1578 .danger_lut_tbl = {0xff, 0xffff, 0x0},
1579 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1580 .qos_lut_tbl = {
1581 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1582 .entries = sc7180_qos_linear
1583 },
1584 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1585 .entries = sc7180_qos_macrotile
1586 },
1587 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1588 .entries = sc7180_qos_nrt
1589 },
1590 },
1591 .cdp_cfg = {
1592 {.rd_enable = 1, .wr_enable = 1},
1593 {.rd_enable = 1, .wr_enable = 0}
1594 },
1595 .clk_inefficiency_factor = 105,
1596 .bw_inefficiency_factor = 120,
1597 };
1598
1599 static const struct dpu_perf_cfg sm8150_perf_data = {
1600 .max_bw_low = 12800000,
1601 .max_bw_high = 12800000,
1602 .min_core_ib = 2400000,
1603 .min_llcc_ib = 800000,
1604 .min_dram_ib = 800000,
1605 .min_prefill_lines = 24,
1606 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1607 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
1608 .qos_lut_tbl = {
1609 {.nentry = ARRAY_SIZE(sm8150_qos_linear),
1610 .entries = sm8150_qos_linear
1611 },
1612 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1613 .entries = sc7180_qos_macrotile
1614 },
1615 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1616 .entries = sc7180_qos_nrt
1617 },
1618 /* TODO: macrotile-qseed is different from macrotile */
1619 },
1620 .cdp_cfg = {
1621 {.rd_enable = 1, .wr_enable = 1},
1622 {.rd_enable = 1, .wr_enable = 0}
1623 },
1624 .clk_inefficiency_factor = 105,
1625 .bw_inefficiency_factor = 120,
1626 };
1627
1628 static const struct dpu_perf_cfg sc8180x_perf_data = {
1629 .max_bw_low = 9600000,
1630 .max_bw_high = 9600000,
1631 .min_core_ib = 2400000,
1632 .min_llcc_ib = 800000,
1633 .min_dram_ib = 800000,
1634 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1635 .qos_lut_tbl = {
1636 {.nentry = ARRAY_SIZE(sc8180x_qos_linear),
1637 .entries = sc8180x_qos_linear
1638 },
1639 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
1640 .entries = sc8180x_qos_macrotile
1641 },
1642 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1643 .entries = sc7180_qos_nrt
1644 },
1645 /* TODO: macrotile-qseed is different from macrotile */
1646 },
1647 .cdp_cfg = {
1648 {.rd_enable = 1, .wr_enable = 1},
1649 {.rd_enable = 1, .wr_enable = 0}
1650 },
1651 .clk_inefficiency_factor = 105,
1652 .bw_inefficiency_factor = 120,
1653 };
1654
1655 static const struct dpu_perf_cfg sm8250_perf_data = {
1656 .max_bw_low = 13700000,
1657 .max_bw_high = 16600000,
1658 .min_core_ib = 4800000,
1659 .min_llcc_ib = 0,
1660 .min_dram_ib = 800000,
1661 .min_prefill_lines = 35,
1662 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1663 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1664 .qos_lut_tbl = {
1665 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1666 .entries = sc7180_qos_linear
1667 },
1668 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1669 .entries = sc7180_qos_macrotile
1670 },
1671 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1672 .entries = sc7180_qos_nrt
1673 },
1674 /* TODO: macrotile-qseed is different from macrotile */
1675 },
1676 .cdp_cfg = {
1677 {.rd_enable = 1, .wr_enable = 1},
1678 {.rd_enable = 1, .wr_enable = 0}
1679 },
1680 .clk_inefficiency_factor = 105,
1681 .bw_inefficiency_factor = 120,
1682 };
1683
1684 static const struct dpu_perf_cfg sc7280_perf_data = {
1685 .max_bw_low = 4700000,
1686 .max_bw_high = 8800000,
1687 .min_core_ib = 2500000,
1688 .min_llcc_ib = 0,
1689 .min_dram_ib = 1600000,
1690 .min_prefill_lines = 24,
1691 .danger_lut_tbl = {0xffff, 0xffff, 0x0},
1692 .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
1693 .qos_lut_tbl = {
1694 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1695 .entries = sc7180_qos_macrotile
1696 },
1697 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1698 .entries = sc7180_qos_macrotile
1699 },
1700 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1701 .entries = sc7180_qos_nrt
1702 },
1703 },
1704 .cdp_cfg = {
1705 {.rd_enable = 1, .wr_enable = 1},
1706 {.rd_enable = 1, .wr_enable = 0}
1707 },
1708 .clk_inefficiency_factor = 105,
1709 .bw_inefficiency_factor = 120,
1710 };
1711
1712 static const struct dpu_perf_cfg qcm2290_perf_data = {
1713 .max_bw_low = 2700000,
1714 .max_bw_high = 2700000,
1715 .min_core_ib = 1300000,
1716 .min_llcc_ib = 0,
1717 .min_dram_ib = 1600000,
1718 .min_prefill_lines = 24,
1719 .danger_lut_tbl = {0xff, 0x0, 0x0},
1720 .safe_lut_tbl = {0xfff0, 0x0, 0x0},
1721 .qos_lut_tbl = {
1722 {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
1723 .entries = qcm2290_qos_linear
1724 },
1725 },
1726 .cdp_cfg = {
1727 {.rd_enable = 1, .wr_enable = 1},
1728 {.rd_enable = 1, .wr_enable = 0}
1729 },
1730 .clk_inefficiency_factor = 105,
1731 .bw_inefficiency_factor = 120,
1732 };
1733 /*************************************************************
1734 * Hardware catalog
1735 *************************************************************/
1736
1737 static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
1738 .caps = &msm8998_dpu_caps,
1739 .mdp_count = ARRAY_SIZE(msm8998_mdp),
1740 .mdp = msm8998_mdp,
1741 .ctl_count = ARRAY_SIZE(msm8998_ctl),
1742 .ctl = msm8998_ctl,
1743 .sspp_count = ARRAY_SIZE(msm8998_sspp),
1744 .sspp = msm8998_sspp,
1745 .mixer_count = ARRAY_SIZE(msm8998_lm),
1746 .mixer = msm8998_lm,
1747 .dspp_count = ARRAY_SIZE(msm8998_dspp),
1748 .dspp = msm8998_dspp,
1749 .pingpong_count = ARRAY_SIZE(sdm845_pp),
1750 .pingpong = sdm845_pp,
1751 .intf_count = ARRAY_SIZE(msm8998_intf),
1752 .intf = msm8998_intf,
1753 .vbif_count = ARRAY_SIZE(msm8998_vbif),
1754 .vbif = msm8998_vbif,
1755 .reg_dma_count = 0,
1756 .perf = &msm8998_perf_data,
1757 .mdss_irqs = IRQ_SM8250_MASK,
1758 };
1759
1760 static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
1761 .caps = &sdm845_dpu_caps,
1762 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1763 .mdp = sdm845_mdp,
1764 .ctl_count = ARRAY_SIZE(sdm845_ctl),
1765 .ctl = sdm845_ctl,
1766 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1767 .sspp = sdm845_sspp,
1768 .mixer_count = ARRAY_SIZE(sdm845_lm),
1769 .mixer = sdm845_lm,
1770 .pingpong_count = ARRAY_SIZE(sdm845_pp),
1771 .pingpong = sdm845_pp,
1772 .dsc_count = ARRAY_SIZE(sdm845_dsc),
1773 .dsc = sdm845_dsc,
1774 .intf_count = ARRAY_SIZE(sdm845_intf),
1775 .intf = sdm845_intf,
1776 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1777 .vbif = sdm845_vbif,
1778 .reg_dma_count = 1,
1779 .dma_cfg = &sdm845_regdma,
1780 .perf = &sdm845_perf_data,
1781 .mdss_irqs = IRQ_SDM845_MASK,
1782 };
1783
1784 static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
1785 .caps = &sc7180_dpu_caps,
1786 .mdp_count = ARRAY_SIZE(sc7180_mdp),
1787 .mdp = sc7180_mdp,
1788 .ctl_count = ARRAY_SIZE(sc7180_ctl),
1789 .ctl = sc7180_ctl,
1790 .sspp_count = ARRAY_SIZE(sc7180_sspp),
1791 .sspp = sc7180_sspp,
1792 .mixer_count = ARRAY_SIZE(sc7180_lm),
1793 .mixer = sc7180_lm,
1794 .dspp_count = ARRAY_SIZE(sc7180_dspp),
1795 .dspp = sc7180_dspp,
1796 .pingpong_count = ARRAY_SIZE(sc7180_pp),
1797 .pingpong = sc7180_pp,
1798 .intf_count = ARRAY_SIZE(sc7180_intf),
1799 .intf = sc7180_intf,
1800 .wb_count = ARRAY_SIZE(sm8250_wb),
1801 .wb = sm8250_wb,
1802 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1803 .vbif = sdm845_vbif,
1804 .reg_dma_count = 1,
1805 .dma_cfg = &sdm845_regdma,
1806 .perf = &sc7180_perf_data,
1807 .mdss_irqs = IRQ_SC7180_MASK,
1808 };
1809
1810 static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
1811 .caps = &sm8150_dpu_caps,
1812 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1813 .mdp = sdm845_mdp,
1814 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1815 .ctl = sm8150_ctl,
1816 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1817 .sspp = sdm845_sspp,
1818 .mixer_count = ARRAY_SIZE(sm8150_lm),
1819 .mixer = sm8150_lm,
1820 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1821 .dspp = sm8150_dspp,
1822 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1823 .pingpong = sm8150_pp,
1824 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1825 .merge_3d = sm8150_merge_3d,
1826 .intf_count = ARRAY_SIZE(sm8150_intf),
1827 .intf = sm8150_intf,
1828 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1829 .vbif = sdm845_vbif,
1830 .reg_dma_count = 1,
1831 .dma_cfg = &sm8150_regdma,
1832 .perf = &sm8150_perf_data,
1833 .mdss_irqs = IRQ_SDM845_MASK,
1834 };
1835
1836 static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
1837 .caps = &sc8180x_dpu_caps,
1838 .mdp_count = ARRAY_SIZE(sc8180x_mdp),
1839 .mdp = sc8180x_mdp,
1840 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1841 .ctl = sm8150_ctl,
1842 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1843 .sspp = sdm845_sspp,
1844 .mixer_count = ARRAY_SIZE(sm8150_lm),
1845 .mixer = sm8150_lm,
1846 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1847 .pingpong = sm8150_pp,
1848 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1849 .merge_3d = sm8150_merge_3d,
1850 .intf_count = ARRAY_SIZE(sc8180x_intf),
1851 .intf = sc8180x_intf,
1852 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1853 .vbif = sdm845_vbif,
1854 .reg_dma_count = 1,
1855 .dma_cfg = &sm8150_regdma,
1856 .perf = &sc8180x_perf_data,
1857 .mdss_irqs = IRQ_SC8180X_MASK,
1858 };
1859
1860 static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
1861 .caps = &sm8250_dpu_caps,
1862 .mdp_count = ARRAY_SIZE(sm8250_mdp),
1863 .mdp = sm8250_mdp,
1864 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1865 .ctl = sm8150_ctl,
1866 .sspp_count = ARRAY_SIZE(sm8250_sspp),
1867 .sspp = sm8250_sspp,
1868 .mixer_count = ARRAY_SIZE(sm8150_lm),
1869 .mixer = sm8150_lm,
1870 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1871 .dspp = sm8150_dspp,
1872 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1873 .pingpong = sm8150_pp,
1874 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1875 .merge_3d = sm8150_merge_3d,
1876 .intf_count = ARRAY_SIZE(sm8150_intf),
1877 .intf = sm8150_intf,
1878 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1879 .vbif = sdm845_vbif,
1880 .wb_count = ARRAY_SIZE(sm8250_wb),
1881 .wb = sm8250_wb,
1882 .reg_dma_count = 1,
1883 .dma_cfg = &sm8250_regdma,
1884 .perf = &sm8250_perf_data,
1885 .mdss_irqs = IRQ_SM8250_MASK,
1886 };
1887
1888 static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
1889 .caps = &sc7280_dpu_caps,
1890 .mdp_count = ARRAY_SIZE(sc7280_mdp),
1891 .mdp = sc7280_mdp,
1892 .ctl_count = ARRAY_SIZE(sc7280_ctl),
1893 .ctl = sc7280_ctl,
1894 .sspp_count = ARRAY_SIZE(sc7280_sspp),
1895 .sspp = sc7280_sspp,
1896 .dspp_count = ARRAY_SIZE(sc7180_dspp),
1897 .dspp = sc7180_dspp,
1898 .mixer_count = ARRAY_SIZE(sc7280_lm),
1899 .mixer = sc7280_lm,
1900 .pingpong_count = ARRAY_SIZE(sc7280_pp),
1901 .pingpong = sc7280_pp,
1902 .intf_count = ARRAY_SIZE(sc7280_intf),
1903 .intf = sc7280_intf,
1904 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1905 .vbif = sdm845_vbif,
1906 .perf = &sc7280_perf_data,
1907 .mdss_irqs = IRQ_SC7280_MASK,
1908 };
1909
1910 static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
1911 .caps = &qcm2290_dpu_caps,
1912 .mdp_count = ARRAY_SIZE(qcm2290_mdp),
1913 .mdp = qcm2290_mdp,
1914 .ctl_count = ARRAY_SIZE(qcm2290_ctl),
1915 .ctl = qcm2290_ctl,
1916 .sspp_count = ARRAY_SIZE(qcm2290_sspp),
1917 .sspp = qcm2290_sspp,
1918 .mixer_count = ARRAY_SIZE(qcm2290_lm),
1919 .mixer = qcm2290_lm,
1920 .dspp_count = ARRAY_SIZE(qcm2290_dspp),
1921 .dspp = qcm2290_dspp,
1922 .pingpong_count = ARRAY_SIZE(qcm2290_pp),
1923 .pingpong = qcm2290_pp,
1924 .intf_count = ARRAY_SIZE(qcm2290_intf),
1925 .intf = qcm2290_intf,
1926 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1927 .vbif = sdm845_vbif,
1928 .perf = &qcm2290_perf_data,
1929 .mdss_irqs = IRQ_SC7180_MASK,
1930 };
1931
1932 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
1933 { .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg},
1934 { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg},
1935 { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg},
1936 { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg},
1937 { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg},
1938 { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg},
1939 { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
1940 { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
1941 { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
1942 { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
1943 { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
1944 };
1945
dpu_hw_catalog_init(u32 hw_rev)1946 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
1947 {
1948 int i;
1949
1950 for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
1951 if (cfg_handler[i].hw_rev == hw_rev)
1952 return cfg_handler[i].dpu_cfg;
1953 }
1954
1955 DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
1956
1957 return ERR_PTR(-ENODEV);
1958 }
1959
1960