1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021 Advanced Micro Devices, Inc.
7 //
8 // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9
10 /*
11 * Hardware interface for ACP DSP Firmware binaries loader
12 */
13
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17
18 #include "../ops.h"
19 #include "acp-dsp-offset.h"
20 #include "acp.h"
21
22 #define FW_BIN 0
23 #define FW_DATA_BIN 1
24
25 #define FW_BIN_PTE_OFFSET 0x00
26 #define FW_DATA_BIN_PTE_OFFSET 0x08
27
28 #define ACP_DSP_RUN 0x00
29
acp_dsp_block_read(struct snd_sof_dev * sdev,enum snd_sof_fw_blk_type blk_type,u32 offset,void * dest,size_t size)30 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
31 u32 offset, void *dest, size_t size)
32 {
33 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
34 switch (blk_type) {
35 case SOF_FW_BLK_TYPE_SRAM:
36 offset = offset - desc->sram_pte_offset;
37 memcpy_from_scratch(sdev, offset, dest, size);
38 break;
39 default:
40 dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
41 return -EINVAL;
42 }
43
44 return 0;
45 }
46 EXPORT_SYMBOL_NS(acp_dsp_block_read, SND_SOC_SOF_AMD_COMMON);
47
acp_dsp_block_write(struct snd_sof_dev * sdev,enum snd_sof_fw_blk_type blk_type,u32 offset,void * src,size_t size)48 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
49 u32 offset, void *src, size_t size)
50 {
51 struct snd_sof_pdata *plat_data = sdev->pdata;
52 struct pci_dev *pci = to_pci_dev(sdev->dev);
53 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
54 struct acp_dev_data *adata;
55 void *dest;
56 u32 dma_size, page_count;
57 unsigned int size_fw;
58
59 adata = sdev->pdata->hw_pdata;
60
61 switch (blk_type) {
62 case SOF_FW_BLK_TYPE_IRAM:
63 if (!adata->bin_buf) {
64 size_fw = plat_data->fw->size;
65 page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
66 dma_size = page_count * ACP_PAGE_SIZE;
67 adata->bin_buf = dma_alloc_coherent(&pci->dev, dma_size,
68 &adata->sha_dma_addr,
69 GFP_ATOMIC);
70 if (!adata->bin_buf)
71 return -ENOMEM;
72 }
73 adata->fw_bin_size = size + offset;
74 dest = adata->bin_buf + offset;
75 break;
76 case SOF_FW_BLK_TYPE_DRAM:
77 if (!adata->data_buf) {
78 adata->data_buf = dma_alloc_coherent(&pci->dev,
79 ACP_DEFAULT_DRAM_LENGTH,
80 &adata->dma_addr,
81 GFP_ATOMIC);
82 if (!adata->data_buf)
83 return -ENOMEM;
84 }
85 dest = adata->data_buf + offset;
86 adata->fw_data_bin_size = size + offset;
87 break;
88 case SOF_FW_BLK_TYPE_SRAM:
89 offset = offset - desc->sram_pte_offset;
90 memcpy_to_scratch(sdev, offset, src, size);
91 return 0;
92 default:
93 dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
94 return -EINVAL;
95 }
96
97 memcpy(dest, src, size);
98 return 0;
99 }
100 EXPORT_SYMBOL_NS(acp_dsp_block_write, SND_SOC_SOF_AMD_COMMON);
101
acp_get_bar_index(struct snd_sof_dev * sdev,u32 type)102 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
103 {
104 return type;
105 }
106 EXPORT_SYMBOL_NS(acp_get_bar_index, SND_SOC_SOF_AMD_COMMON);
107
configure_pte_for_fw_loading(int type,int num_pages,struct acp_dev_data * adata)108 static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev_data *adata)
109 {
110 struct snd_sof_dev *sdev = adata->dev;
111 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
112 unsigned int low, high;
113 dma_addr_t addr;
114 u16 page_idx;
115 u32 offset;
116
117 switch (type) {
118 case FW_BIN:
119 offset = FW_BIN_PTE_OFFSET;
120 addr = adata->sha_dma_addr;
121 break;
122 case FW_DATA_BIN:
123 offset = adata->fw_bin_page_count * 8;
124 addr = adata->dma_addr;
125 break;
126 default:
127 dev_err(sdev->dev, "Invalid data type %x\n", type);
128 return;
129 }
130
131 /* Group Enable */
132 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
133 desc->sram_pte_offset | BIT(31));
134 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
135 PAGE_SIZE_4K_ENABLE);
136
137 for (page_idx = 0; page_idx < num_pages; page_idx++) {
138 low = lower_32_bits(addr);
139 high = upper_32_bits(addr);
140 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset, low);
141 high |= BIT(31);
142 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset + 4, high);
143 offset += 8;
144 addr += PAGE_SIZE;
145 }
146
147 /* Flush ATU Cache after PTE Update */
148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
149 }
150
151 /* pre fw run operations */
acp_dsp_pre_fw_run(struct snd_sof_dev * sdev)152 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
153 {
154 struct pci_dev *pci = to_pci_dev(sdev->dev);
155 struct snd_sof_pdata *plat_data = sdev->pdata;
156 struct acp_dev_data *adata;
157 unsigned int src_addr, size_fw;
158 u32 page_count, dma_size;
159 int ret;
160
161 adata = sdev->pdata->hw_pdata;
162 size_fw = adata->fw_bin_size;
163
164 page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
165 adata->fw_bin_page_count = page_count;
166
167 configure_pte_for_fw_loading(FW_BIN, page_count, adata);
168 ret = configure_and_run_sha_dma(adata, adata->bin_buf, ACP_SYSTEM_MEMORY_WINDOW,
169 ACP_IRAM_BASE_ADDRESS, size_fw);
170 if (ret < 0) {
171 dev_err(sdev->dev, "SHA DMA transfer failed status: %d\n", ret);
172 return ret;
173 }
174 configure_pte_for_fw_loading(FW_DATA_BIN, ACP_DRAM_PAGE_COUNT, adata);
175
176 src_addr = ACP_SYSTEM_MEMORY_WINDOW + page_count * ACP_PAGE_SIZE;
177 ret = configure_and_run_dma(adata, src_addr, ACP_DATA_RAM_BASE_ADDRESS,
178 adata->fw_data_bin_size);
179 if (ret < 0) {
180 dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret);
181 return ret;
182 }
183
184 ret = acp_dma_status(adata, 0);
185 if (ret < 0)
186 dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
187
188 /* Free memory once DMA is complete */
189 dma_size = (PAGE_ALIGN(plat_data->fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE;
190 dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr);
191 dma_free_coherent(&pci->dev, ACP_DEFAULT_DRAM_LENGTH, adata->data_buf, adata->dma_addr);
192 adata->bin_buf = NULL;
193 adata->data_buf = NULL;
194
195 return ret;
196 }
197 EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON);
198
acp_sof_dsp_run(struct snd_sof_dev * sdev)199 int acp_sof_dsp_run(struct snd_sof_dev *sdev)
200 {
201 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
202 int val;
203
204 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL, ACP_DSP_RUN);
205 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL);
206 dev_dbg(sdev->dev, "ACP_DSP0_RUNSTALL : 0x%0x\n", val);
207
208 /* Some platforms won't support fusion DSP,keep offset zero for no support */
209 if (desc->fusion_dsp_offset) {
210 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset, ACP_DSP_RUN);
211 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset);
212 dev_dbg(sdev->dev, "ACP_DSP0_FUSION_RUNSTALL : 0x%0x\n", val);
213 }
214 return 0;
215 }
216 EXPORT_SYMBOL_NS(acp_sof_dsp_run, SND_SOC_SOF_AMD_COMMON);
217