1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include "soc15_common.h"
34 #include "gc/gc_11_0_0_offset.h"
35 #include "gc/gc_11_0_0_sh_mask.h"
36 #include <asm/div64.h>
37
38 #include <linux/pci.h>
39 #include <linux/pm_runtime.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_damage_helper.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_gem_framebuffer_helper.h>
45 #include <drm/drm_fb_helper.h>
46 #include <drm/drm_fourcc.h>
47 #include <drm/drm_vblank.h>
48
49 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
50 struct amdgpu_framebuffer *rfb,
51 const struct drm_mode_fb_cmd2 *mode_cmd,
52 struct drm_gem_object *obj);
53
amdgpu_display_flip_callback(struct dma_fence * f,struct dma_fence_cb * cb)54 static void amdgpu_display_flip_callback(struct dma_fence *f,
55 struct dma_fence_cb *cb)
56 {
57 struct amdgpu_flip_work *work =
58 container_of(cb, struct amdgpu_flip_work, cb);
59
60 dma_fence_put(f);
61 schedule_work(&work->flip_work.work);
62 }
63
amdgpu_display_flip_handle_fence(struct amdgpu_flip_work * work,struct dma_fence ** f)64 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
65 struct dma_fence **f)
66 {
67 struct dma_fence *fence= *f;
68
69 if (fence == NULL)
70 return false;
71
72 *f = NULL;
73
74 if (!dma_fence_add_callback(fence, &work->cb,
75 amdgpu_display_flip_callback))
76 return true;
77
78 dma_fence_put(fence);
79 return false;
80 }
81
amdgpu_display_flip_work_func(struct work_struct * __work)82 static void amdgpu_display_flip_work_func(struct work_struct *__work)
83 {
84 struct delayed_work *delayed_work =
85 container_of(__work, struct delayed_work, work);
86 struct amdgpu_flip_work *work =
87 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
88 struct amdgpu_device *adev = work->adev;
89 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
90
91 struct drm_crtc *crtc = &amdgpu_crtc->base;
92 unsigned long flags;
93 unsigned int i;
94 int vpos, hpos;
95
96 for (i = 0; i < work->shared_count; ++i)
97 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
98 return;
99
100 /* Wait until we're out of the vertical blank period before the one
101 * targeted by the flip
102 */
103 if (amdgpu_crtc->enabled &&
104 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
105 &vpos, &hpos, NULL, NULL,
106 &crtc->hwmode)
107 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
108 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
109 (int)(work->target_vblank -
110 amdgpu_get_vblank_counter_kms(crtc)) > 0) {
111 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
112 return;
113 }
114
115 /* We borrow the event spin lock for protecting flip_status */
116 spin_lock_irqsave(&crtc->dev->event_lock, flags);
117
118 /* Do the flip (mmio) */
119 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
120
121 /* Set the flip status */
122 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
123 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
124
125
126 drm_dbg_vbl(adev_to_drm(adev),
127 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
128 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
129
130 }
131
132 /*
133 * Handle unpin events outside the interrupt handler proper.
134 */
amdgpu_display_unpin_work_func(struct work_struct * __work)135 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
136 {
137 struct amdgpu_flip_work *work =
138 container_of(__work, struct amdgpu_flip_work, unpin_work);
139 int r;
140
141 /* unpin of the old buffer */
142 r = amdgpu_bo_reserve(work->old_abo, true);
143 if (likely(r == 0)) {
144 amdgpu_bo_unpin(work->old_abo);
145 amdgpu_bo_unreserve(work->old_abo);
146 } else
147 DRM_ERROR("failed to reserve buffer after flip\n");
148
149 amdgpu_bo_unref(&work->old_abo);
150 kfree(work->shared);
151 kfree(work);
152 }
153
amdgpu_display_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)154 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
155 struct drm_framebuffer *fb,
156 struct drm_pending_vblank_event *event,
157 uint32_t page_flip_flags, uint32_t target,
158 struct drm_modeset_acquire_ctx *ctx)
159 {
160 struct drm_device *dev = crtc->dev;
161 struct amdgpu_device *adev = drm_to_adev(dev);
162 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
163 struct drm_gem_object *obj;
164 struct amdgpu_flip_work *work;
165 struct amdgpu_bo *new_abo;
166 unsigned long flags;
167 u64 tiling_flags;
168 int i, r;
169
170 work = kzalloc(sizeof(*work), GFP_KERNEL);
171 if (work == NULL)
172 return -ENOMEM;
173
174 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
175 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
176
177 work->event = event;
178 work->adev = adev;
179 work->crtc_id = amdgpu_crtc->crtc_id;
180 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
181
182 /* schedule unpin of the old buffer */
183 obj = crtc->primary->fb->obj[0];
184
185 /* take a reference to the old object */
186 work->old_abo = gem_to_amdgpu_bo(obj);
187 amdgpu_bo_ref(work->old_abo);
188
189 obj = fb->obj[0];
190 new_abo = gem_to_amdgpu_bo(obj);
191
192 /* pin the new buffer */
193 r = amdgpu_bo_reserve(new_abo, false);
194 if (unlikely(r != 0)) {
195 DRM_ERROR("failed to reserve new abo buffer before flip\n");
196 goto cleanup;
197 }
198
199 if (!adev->enable_virtual_display) {
200 r = amdgpu_bo_pin(new_abo,
201 amdgpu_display_supported_domains(adev, new_abo->flags));
202 if (unlikely(r != 0)) {
203 DRM_ERROR("failed to pin new abo buffer before flip\n");
204 goto unreserve;
205 }
206 }
207
208 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
209 if (unlikely(r != 0)) {
210 DRM_ERROR("%p bind failed\n", new_abo);
211 goto unpin;
212 }
213
214 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
215 &work->shared_count,
216 &work->shared);
217 if (unlikely(r != 0)) {
218 DRM_ERROR("failed to get fences for buffer\n");
219 goto unpin;
220 }
221
222 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
223 amdgpu_bo_unreserve(new_abo);
224
225 if (!adev->enable_virtual_display)
226 work->base = amdgpu_bo_gpu_offset(new_abo);
227 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
228 amdgpu_get_vblank_counter_kms(crtc);
229
230 /* we borrow the event spin lock for protecting flip_wrok */
231 spin_lock_irqsave(&crtc->dev->event_lock, flags);
232 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
233 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
234 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
235 r = -EBUSY;
236 goto pflip_cleanup;
237 }
238
239 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
240 amdgpu_crtc->pflip_works = work;
241
242
243 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
244 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
245 /* update crtc fb */
246 crtc->primary->fb = fb;
247 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
248 amdgpu_display_flip_work_func(&work->flip_work.work);
249 return 0;
250
251 pflip_cleanup:
252 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
253 DRM_ERROR("failed to reserve new abo in error path\n");
254 goto cleanup;
255 }
256 unpin:
257 if (!adev->enable_virtual_display)
258 amdgpu_bo_unpin(new_abo);
259
260 unreserve:
261 amdgpu_bo_unreserve(new_abo);
262
263 cleanup:
264 amdgpu_bo_unref(&work->old_abo);
265 for (i = 0; i < work->shared_count; ++i)
266 dma_fence_put(work->shared[i]);
267 kfree(work->shared);
268 kfree(work);
269
270 return r;
271 }
272
amdgpu_display_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)273 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
274 struct drm_modeset_acquire_ctx *ctx)
275 {
276 struct drm_device *dev;
277 struct amdgpu_device *adev;
278 struct drm_crtc *crtc;
279 bool active = false;
280 int ret;
281
282 if (!set || !set->crtc)
283 return -EINVAL;
284
285 dev = set->crtc->dev;
286
287 ret = pm_runtime_get_sync(dev->dev);
288 if (ret < 0)
289 goto out;
290
291 ret = drm_crtc_helper_set_config(set, ctx);
292
293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
294 if (crtc->enabled)
295 active = true;
296
297 pm_runtime_mark_last_busy(dev->dev);
298
299 adev = drm_to_adev(dev);
300 /* if we have active crtcs and we don't have a power ref,
301 * take the current one
302 */
303 if (active && !adev->have_disp_power_ref) {
304 adev->have_disp_power_ref = true;
305 return ret;
306 }
307 /* if we have no active crtcs, then go to
308 * drop the power ref we got before
309 */
310 if (!active && adev->have_disp_power_ref)
311 adev->have_disp_power_ref = false;
312 out:
313 /* drop the power reference we got coming in here */
314 pm_runtime_put_autosuspend(dev->dev);
315 return ret;
316 }
317
318 static const char *encoder_names[41] = {
319 "NONE",
320 "INTERNAL_LVDS",
321 "INTERNAL_TMDS1",
322 "INTERNAL_TMDS2",
323 "INTERNAL_DAC1",
324 "INTERNAL_DAC2",
325 "INTERNAL_SDVOA",
326 "INTERNAL_SDVOB",
327 "SI170B",
328 "CH7303",
329 "CH7301",
330 "INTERNAL_DVO1",
331 "EXTERNAL_SDVOA",
332 "EXTERNAL_SDVOB",
333 "TITFP513",
334 "INTERNAL_LVTM1",
335 "VT1623",
336 "HDMI_SI1930",
337 "HDMI_INTERNAL",
338 "INTERNAL_KLDSCP_TMDS1",
339 "INTERNAL_KLDSCP_DVO1",
340 "INTERNAL_KLDSCP_DAC1",
341 "INTERNAL_KLDSCP_DAC2",
342 "SI178",
343 "MVPU_FPGA",
344 "INTERNAL_DDI",
345 "VT1625",
346 "HDMI_SI1932",
347 "DP_AN9801",
348 "DP_DP501",
349 "INTERNAL_UNIPHY",
350 "INTERNAL_KLDSCP_LVTMA",
351 "INTERNAL_UNIPHY1",
352 "INTERNAL_UNIPHY2",
353 "NUTMEG",
354 "TRAVIS",
355 "INTERNAL_VCE",
356 "INTERNAL_UNIPHY3",
357 "HDMI_ANX9805",
358 "INTERNAL_AMCLK",
359 "VIRTUAL",
360 };
361
362 static const char *hpd_names[6] = {
363 "HPD1",
364 "HPD2",
365 "HPD3",
366 "HPD4",
367 "HPD5",
368 "HPD6",
369 };
370
amdgpu_display_print_display_setup(struct drm_device * dev)371 void amdgpu_display_print_display_setup(struct drm_device *dev)
372 {
373 struct drm_connector *connector;
374 struct amdgpu_connector *amdgpu_connector;
375 struct drm_encoder *encoder;
376 struct amdgpu_encoder *amdgpu_encoder;
377 struct drm_connector_list_iter iter;
378 uint32_t devices;
379 int i = 0;
380
381 drm_connector_list_iter_begin(dev, &iter);
382 DRM_INFO("AMDGPU Display Connectors\n");
383 drm_for_each_connector_iter(connector, &iter) {
384 amdgpu_connector = to_amdgpu_connector(connector);
385 DRM_INFO("Connector %d:\n", i);
386 DRM_INFO(" %s\n", connector->name);
387 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
388 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
389 if (amdgpu_connector->ddc_bus) {
390 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
391 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
392 amdgpu_connector->ddc_bus->rec.mask_data_reg,
393 amdgpu_connector->ddc_bus->rec.a_clk_reg,
394 amdgpu_connector->ddc_bus->rec.a_data_reg,
395 amdgpu_connector->ddc_bus->rec.en_clk_reg,
396 amdgpu_connector->ddc_bus->rec.en_data_reg,
397 amdgpu_connector->ddc_bus->rec.y_clk_reg,
398 amdgpu_connector->ddc_bus->rec.y_data_reg);
399 if (amdgpu_connector->router.ddc_valid)
400 DRM_INFO(" DDC Router 0x%x/0x%x\n",
401 amdgpu_connector->router.ddc_mux_control_pin,
402 amdgpu_connector->router.ddc_mux_state);
403 if (amdgpu_connector->router.cd_valid)
404 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
405 amdgpu_connector->router.cd_mux_control_pin,
406 amdgpu_connector->router.cd_mux_state);
407 } else {
408 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
409 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
410 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
411 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
412 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
413 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
414 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
415 }
416 DRM_INFO(" Encoders:\n");
417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
418 amdgpu_encoder = to_amdgpu_encoder(encoder);
419 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
420 if (devices) {
421 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
422 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
423 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
424 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
425 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
426 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
427 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
428 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
429 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
430 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
431 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
432 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
433 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
434 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
435 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
436 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
437 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
438 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
439 if (devices & ATOM_DEVICE_TV1_SUPPORT)
440 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
441 if (devices & ATOM_DEVICE_CV_SUPPORT)
442 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
443 }
444 }
445 i++;
446 }
447 drm_connector_list_iter_end(&iter);
448 }
449
amdgpu_display_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)450 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
451 bool use_aux)
452 {
453 u8 out = 0x0;
454 u8 buf[8];
455 int ret;
456 struct i2c_msg msgs[] = {
457 {
458 .addr = DDC_ADDR,
459 .flags = 0,
460 .len = 1,
461 .buf = &out,
462 },
463 {
464 .addr = DDC_ADDR,
465 .flags = I2C_M_RD,
466 .len = 8,
467 .buf = buf,
468 }
469 };
470
471 /* on hw with routers, select right port */
472 if (amdgpu_connector->router.ddc_valid)
473 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
474
475 if (use_aux)
476 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
477 else
478 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
479
480 if (ret != 2)
481 /* Couldn't find an accessible DDC on this connector */
482 return false;
483 /* Probe also for valid EDID header
484 * EDID header starts with:
485 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
486 * Only the first 6 bytes must be valid as
487 * drm_edid_block_valid() can fix the last 2 bytes
488 */
489 if (drm_edid_header_is_valid(buf) < 6) {
490 /* Couldn't find an accessible EDID on this
491 * connector
492 */
493 return false;
494 }
495 return true;
496 }
497
amdgpu_dirtyfb(struct drm_framebuffer * fb,struct drm_file * file,unsigned int flags,unsigned int color,struct drm_clip_rect * clips,unsigned int num_clips)498 static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file,
499 unsigned int flags, unsigned int color,
500 struct drm_clip_rect *clips, unsigned int num_clips)
501 {
502
503 if (file)
504 return -ENOSYS;
505
506 return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
507 num_clips);
508 }
509
510 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
511 .destroy = drm_gem_fb_destroy,
512 .create_handle = drm_gem_fb_create_handle,
513 };
514
515 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
516 .destroy = drm_gem_fb_destroy,
517 .create_handle = drm_gem_fb_create_handle,
518 .dirty = amdgpu_dirtyfb
519 };
520
amdgpu_display_supported_domains(struct amdgpu_device * adev,uint64_t bo_flags)521 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
522 uint64_t bo_flags)
523 {
524 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
525
526 #if defined(CONFIG_DRM_AMD_DC)
527 /*
528 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
529 * is not supported for this board. But this mapping is required
530 * to avoid hang caused by placement of scanout BO in GTT on certain
531 * APUs. So force the BO placement to VRAM in case this architecture
532 * will not allow USWC mappings.
533 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
534 */
535 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
536 amdgpu_bo_support_uswc(bo_flags) &&
537 amdgpu_device_asic_has_dc_support(adev->asic_type) &&
538 adev->mode_info.gpu_vm_support)
539 domain |= AMDGPU_GEM_DOMAIN_GTT;
540 #endif
541
542 return domain;
543 }
544
545 static const struct drm_format_info dcc_formats[] = {
546 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
547 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
548 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
549 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
550 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
551 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
552 .has_alpha = true, },
553 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
554 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
555 .has_alpha = true, },
556 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
557 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
558 .has_alpha = true, },
559 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
560 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
561 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
562 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
563 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
564 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
565 .has_alpha = true, },
566 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
567 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
568 .has_alpha = true, },
569 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
570 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
571 };
572
573 static const struct drm_format_info dcc_retile_formats[] = {
574 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
575 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
576 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
577 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
578 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
579 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
580 .has_alpha = true, },
581 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
582 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
583 .has_alpha = true, },
584 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
585 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
586 .has_alpha = true, },
587 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
588 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
589 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
590 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
591 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
592 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
593 .has_alpha = true, },
594 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
595 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
596 .has_alpha = true, },
597 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
598 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
599 };
600
601 static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],int num_formats,u32 format)602 lookup_format_info(const struct drm_format_info formats[],
603 int num_formats, u32 format)
604 {
605 int i;
606
607 for (i = 0; i < num_formats; i++) {
608 if (formats[i].format == format)
609 return &formats[i];
610 }
611
612 return NULL;
613 }
614
615 const struct drm_format_info *
amdgpu_lookup_format_info(u32 format,uint64_t modifier)616 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
617 {
618 if (!IS_AMD_FMT_MOD(modifier))
619 return NULL;
620
621 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
622 return lookup_format_info(dcc_retile_formats,
623 ARRAY_SIZE(dcc_retile_formats),
624 format);
625
626 if (AMD_FMT_MOD_GET(DCC, modifier))
627 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
628 format);
629
630 /* returning NULL will cause the default format structs to be used. */
631 return NULL;
632 }
633
634
635 /*
636 * Tries to extract the renderable DCC offset from the opaque metadata attached
637 * to the buffer.
638 */
639 static int
extract_render_dcc_offset(struct amdgpu_device * adev,struct drm_gem_object * obj,uint64_t * offset)640 extract_render_dcc_offset(struct amdgpu_device *adev,
641 struct drm_gem_object *obj,
642 uint64_t *offset)
643 {
644 struct amdgpu_bo *rbo;
645 int r = 0;
646 uint32_t metadata[10]; /* Something that fits a descriptor + header. */
647 uint32_t size;
648
649 rbo = gem_to_amdgpu_bo(obj);
650 r = amdgpu_bo_reserve(rbo, false);
651
652 if (unlikely(r)) {
653 /* Don't show error message when returning -ERESTARTSYS */
654 if (r != -ERESTARTSYS)
655 DRM_ERROR("Unable to reserve buffer: %d\n", r);
656 return r;
657 }
658
659 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
660 amdgpu_bo_unreserve(rbo);
661
662 if (r)
663 return r;
664
665 /*
666 * The first word is the metadata version, and we need space for at least
667 * the version + pci vendor+device id + 8 words for a descriptor.
668 */
669 if (size < 40 || metadata[0] != 1)
670 return -EINVAL;
671
672 if (adev->family >= AMDGPU_FAMILY_NV) {
673 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
674 *offset = ((u64)metadata[9] << 16u) |
675 ((metadata[8] & 0xFF000000u) >> 16);
676 } else {
677 /* resource word 5/7 META_DATA_ADDRESS */
678 *offset = ((u64)metadata[9] << 8u) |
679 ((u64)(metadata[7] & 0x1FE0000u) << 23);
680 }
681
682 return 0;
683 }
684
convert_tiling_flags_to_modifier(struct amdgpu_framebuffer * afb)685 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
686 {
687 struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
688 uint64_t modifier = 0;
689 int num_pipes = 0;
690 int num_pkrs = 0;
691
692 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
693 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
694
695 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
696 modifier = DRM_FORMAT_MOD_LINEAR;
697 } else {
698 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
699 bool has_xor = swizzle >= 16;
700 int block_size_bits;
701 int version;
702 int pipe_xor_bits = 0;
703 int bank_xor_bits = 0;
704 int packers = 0;
705 int rb = 0;
706 int pipes = ilog2(num_pipes);
707 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
708
709 switch (swizzle >> 2) {
710 case 0: /* 256B */
711 block_size_bits = 8;
712 break;
713 case 1: /* 4KiB */
714 case 5: /* 4KiB _X */
715 block_size_bits = 12;
716 break;
717 case 2: /* 64KiB */
718 case 4: /* 64 KiB _T */
719 case 6: /* 64 KiB _X */
720 block_size_bits = 16;
721 break;
722 case 7: /* 256 KiB */
723 block_size_bits = 18;
724 break;
725 default:
726 /* RESERVED or VAR */
727 return -EINVAL;
728 }
729
730 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
731 version = AMD_FMT_MOD_TILE_VER_GFX11;
732 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
733 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
734 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
735 version = AMD_FMT_MOD_TILE_VER_GFX10;
736 else
737 version = AMD_FMT_MOD_TILE_VER_GFX9;
738
739 switch (swizzle & 3) {
740 case 0: /* Z microtiling */
741 return -EINVAL;
742 case 1: /* S microtiling */
743 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
744 if (!has_xor)
745 version = AMD_FMT_MOD_TILE_VER_GFX9;
746 }
747 break;
748 case 2:
749 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
750 if (!has_xor && afb->base.format->cpp[0] != 4)
751 version = AMD_FMT_MOD_TILE_VER_GFX9;
752 }
753 break;
754 case 3:
755 break;
756 }
757
758 if (has_xor) {
759 if (num_pipes == num_pkrs && num_pkrs == 0) {
760 DRM_ERROR("invalid number of pipes and packers\n");
761 return -EINVAL;
762 }
763
764 switch (version) {
765 case AMD_FMT_MOD_TILE_VER_GFX11:
766 pipe_xor_bits = min(block_size_bits - 8, pipes);
767 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
768 break;
769 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
770 pipe_xor_bits = min(block_size_bits - 8, pipes);
771 packers = min(block_size_bits - 8 - pipe_xor_bits,
772 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
773 break;
774 case AMD_FMT_MOD_TILE_VER_GFX10:
775 pipe_xor_bits = min(block_size_bits - 8, pipes);
776 break;
777 case AMD_FMT_MOD_TILE_VER_GFX9:
778 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
779 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
780 pipe_xor_bits = min(block_size_bits - 8, pipes +
781 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
782 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
783 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
784 break;
785 }
786 }
787
788 modifier = AMD_FMT_MOD |
789 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
790 AMD_FMT_MOD_SET(TILE_VERSION, version) |
791 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
792 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
793 AMD_FMT_MOD_SET(PACKERS, packers);
794
795 if (dcc_offset != 0) {
796 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
797 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
798 const struct drm_format_info *format_info;
799 u64 render_dcc_offset;
800
801 /* Enable constant encode on RAVEN2 and later. */
802 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
803 (adev->asic_type == CHIP_RAVEN &&
804 adev->external_rev_id >= 0x81)) &&
805 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
806
807 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
808 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
809 AMD_FMT_MOD_DCC_BLOCK_256B;
810
811 modifier |= AMD_FMT_MOD_SET(DCC, 1) |
812 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
813 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
814 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
815 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
816
817 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
818 afb->base.pitches[1] =
819 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
820
821 /*
822 * If the userspace driver uses retiling the tiling flags do not contain
823 * info on the renderable DCC buffer. Luckily the opaque metadata contains
824 * the info so we can try to extract it. The kernel does not use this info
825 * but we should convert it to a modifier plane for getfb2, so the
826 * userspace driver that gets it doesn't have to juggle around another DCC
827 * plane internally.
828 */
829 if (extract_render_dcc_offset(adev, afb->base.obj[0],
830 &render_dcc_offset) == 0 &&
831 render_dcc_offset != 0 &&
832 render_dcc_offset != afb->base.offsets[1] &&
833 render_dcc_offset < UINT_MAX) {
834 uint32_t dcc_block_bits; /* of base surface data */
835
836 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
837 afb->base.offsets[2] = render_dcc_offset;
838
839 if (adev->family >= AMDGPU_FAMILY_NV) {
840 int extra_pipe = 0;
841
842 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
843 pipes == packers && pipes > 1)
844 extra_pipe = 1;
845
846 dcc_block_bits = max(20, 16 + pipes + extra_pipe);
847 } else {
848 modifier |= AMD_FMT_MOD_SET(RB, rb) |
849 AMD_FMT_MOD_SET(PIPE, pipes);
850 dcc_block_bits = max(20, 18 + rb);
851 }
852
853 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
854 afb->base.pitches[2] = ALIGN(afb->base.width,
855 1u << ((dcc_block_bits + 1) / 2));
856 }
857 format_info = amdgpu_lookup_format_info(afb->base.format->format,
858 modifier);
859 if (!format_info)
860 return -EINVAL;
861
862 afb->base.format = format_info;
863 }
864 }
865
866 afb->base.modifier = modifier;
867 afb->base.flags |= DRM_MODE_FB_MODIFIERS;
868 return 0;
869 }
870
871 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
check_tiling_flags_gfx6(struct amdgpu_framebuffer * afb)872 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
873 {
874 u64 micro_tile_mode;
875
876 /* Zero swizzle mode means linear */
877 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
878 return 0;
879
880 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
881 switch (micro_tile_mode) {
882 case 0: /* DISPLAY */
883 case 3: /* RENDER */
884 return 0;
885 default:
886 drm_dbg_kms(afb->base.dev,
887 "Micro tile mode %llu not supported for scanout\n",
888 micro_tile_mode);
889 return -EINVAL;
890 }
891 }
892
get_block_dimensions(unsigned int block_log2,unsigned int cpp,unsigned int * width,unsigned int * height)893 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
894 unsigned int *width, unsigned int *height)
895 {
896 unsigned int cpp_log2 = ilog2(cpp);
897 unsigned int pixel_log2 = block_log2 - cpp_log2;
898 unsigned int width_log2 = (pixel_log2 + 1) / 2;
899 unsigned int height_log2 = pixel_log2 - width_log2;
900
901 *width = 1 << width_log2;
902 *height = 1 << height_log2;
903 }
904
get_dcc_block_size(uint64_t modifier,bool rb_aligned,bool pipe_aligned)905 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
906 bool pipe_aligned)
907 {
908 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
909
910 switch (ver) {
911 case AMD_FMT_MOD_TILE_VER_GFX9: {
912 /*
913 * TODO: for pipe aligned we may need to check the alignment of the
914 * total size of the surface, which may need to be bigger than the
915 * natural alignment due to some HW workarounds
916 */
917 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
918 }
919 case AMD_FMT_MOD_TILE_VER_GFX10:
920 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
921 case AMD_FMT_MOD_TILE_VER_GFX11: {
922 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
923
924 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
925 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
926 ++pipes_log2;
927
928 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
929 }
930 default:
931 return 0;
932 }
933 }
934
amdgpu_display_verify_plane(struct amdgpu_framebuffer * rfb,int plane,const struct drm_format_info * format,unsigned int block_width,unsigned int block_height,unsigned int block_size_log2)935 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
936 const struct drm_format_info *format,
937 unsigned int block_width, unsigned int block_height,
938 unsigned int block_size_log2)
939 {
940 unsigned int width = rfb->base.width /
941 ((plane && plane < format->num_planes) ? format->hsub : 1);
942 unsigned int height = rfb->base.height /
943 ((plane && plane < format->num_planes) ? format->vsub : 1);
944 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
945 unsigned int block_pitch = block_width * cpp;
946 unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
947 unsigned int block_size = 1 << block_size_log2;
948 uint64_t size;
949
950 if (rfb->base.pitches[plane] % block_pitch) {
951 drm_dbg_kms(rfb->base.dev,
952 "pitch %d for plane %d is not a multiple of block pitch %d\n",
953 rfb->base.pitches[plane], plane, block_pitch);
954 return -EINVAL;
955 }
956 if (rfb->base.pitches[plane] < min_pitch) {
957 drm_dbg_kms(rfb->base.dev,
958 "pitch %d for plane %d is less than minimum pitch %d\n",
959 rfb->base.pitches[plane], plane, min_pitch);
960 return -EINVAL;
961 }
962
963 /* Force at least natural alignment. */
964 if (rfb->base.offsets[plane] % block_size) {
965 drm_dbg_kms(rfb->base.dev,
966 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
967 rfb->base.offsets[plane], plane, block_size);
968 return -EINVAL;
969 }
970
971 size = rfb->base.offsets[plane] +
972 (uint64_t)rfb->base.pitches[plane] / block_pitch *
973 block_size * DIV_ROUND_UP(height, block_height);
974
975 if (rfb->base.obj[0]->size < size) {
976 drm_dbg_kms(rfb->base.dev,
977 "BO size 0x%zx is less than 0x%llx required for plane %d\n",
978 rfb->base.obj[0]->size, size, plane);
979 return -EINVAL;
980 }
981
982 return 0;
983 }
984
985
amdgpu_display_verify_sizes(struct amdgpu_framebuffer * rfb)986 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
987 {
988 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
989 uint64_t modifier = rfb->base.modifier;
990 int ret;
991 unsigned int i, block_width, block_height, block_size_log2;
992
993 if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
994 return 0;
995
996 for (i = 0; i < format_info->num_planes; ++i) {
997 if (modifier == DRM_FORMAT_MOD_LINEAR) {
998 block_width = 256 / format_info->cpp[i];
999 block_height = 1;
1000 block_size_log2 = 8;
1001 } else {
1002 int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1003
1004 switch ((swizzle & ~3) + 1) {
1005 case DC_SW_256B_S:
1006 block_size_log2 = 8;
1007 break;
1008 case DC_SW_4KB_S:
1009 case DC_SW_4KB_S_X:
1010 block_size_log2 = 12;
1011 break;
1012 case DC_SW_64KB_S:
1013 case DC_SW_64KB_S_T:
1014 case DC_SW_64KB_S_X:
1015 block_size_log2 = 16;
1016 break;
1017 case DC_SW_VAR_S_X:
1018 block_size_log2 = 18;
1019 break;
1020 default:
1021 drm_dbg_kms(rfb->base.dev,
1022 "Swizzle mode with unknown block size: %d\n", swizzle);
1023 return -EINVAL;
1024 }
1025
1026 get_block_dimensions(block_size_log2, format_info->cpp[i],
1027 &block_width, &block_height);
1028 }
1029
1030 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1031 block_width, block_height, block_size_log2);
1032 if (ret)
1033 return ret;
1034 }
1035
1036 if (AMD_FMT_MOD_GET(DCC, modifier)) {
1037 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1038 block_size_log2 = get_dcc_block_size(modifier, false, false);
1039 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1040 &block_width, &block_height);
1041 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1042 block_width, block_height,
1043 block_size_log2);
1044 if (ret)
1045 return ret;
1046
1047 ++i;
1048 block_size_log2 = get_dcc_block_size(modifier, true, true);
1049 } else {
1050 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1051
1052 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1053 }
1054 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1055 &block_width, &block_height);
1056 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1057 block_width, block_height, block_size_log2);
1058 if (ret)
1059 return ret;
1060 }
1061
1062 return 0;
1063 }
1064
amdgpu_display_get_fb_info(const struct amdgpu_framebuffer * amdgpu_fb,uint64_t * tiling_flags,bool * tmz_surface)1065 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1066 uint64_t *tiling_flags, bool *tmz_surface)
1067 {
1068 struct amdgpu_bo *rbo;
1069 int r;
1070
1071 if (!amdgpu_fb) {
1072 *tiling_flags = 0;
1073 *tmz_surface = false;
1074 return 0;
1075 }
1076
1077 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1078 r = amdgpu_bo_reserve(rbo, false);
1079
1080 if (unlikely(r)) {
1081 /* Don't show error message when returning -ERESTARTSYS */
1082 if (r != -ERESTARTSYS)
1083 DRM_ERROR("Unable to reserve buffer: %d\n", r);
1084 return r;
1085 }
1086
1087 if (tiling_flags)
1088 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1089
1090 if (tmz_surface)
1091 *tmz_surface = amdgpu_bo_encrypted(rbo);
1092
1093 amdgpu_bo_unreserve(rbo);
1094
1095 return r;
1096 }
1097
amdgpu_display_gem_fb_verify_and_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1098 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1099 struct amdgpu_framebuffer *rfb,
1100 struct drm_file *file_priv,
1101 const struct drm_mode_fb_cmd2 *mode_cmd,
1102 struct drm_gem_object *obj)
1103 {
1104 int ret;
1105
1106 rfb->base.obj[0] = obj;
1107 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1108 /* Verify that the modifier is supported. */
1109 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1110 mode_cmd->modifier[0])) {
1111 drm_dbg_kms(dev,
1112 "unsupported pixel format %p4cc / modifier 0x%llx\n",
1113 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1114
1115 ret = -EINVAL;
1116 goto err;
1117 }
1118
1119 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1120 if (ret)
1121 goto err;
1122
1123 if (drm_drv_uses_atomic_modeset(dev))
1124 ret = drm_framebuffer_init(dev, &rfb->base,
1125 &amdgpu_fb_funcs_atomic);
1126 else
1127 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1128
1129 if (ret)
1130 goto err;
1131
1132 return 0;
1133 err:
1134 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1135 rfb->base.obj[0] = NULL;
1136 return ret;
1137 }
1138
amdgpu_display_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1139 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1140 struct amdgpu_framebuffer *rfb,
1141 const struct drm_mode_fb_cmd2 *mode_cmd,
1142 struct drm_gem_object *obj)
1143 {
1144 struct amdgpu_device *adev = drm_to_adev(dev);
1145 int ret, i;
1146
1147 /*
1148 * This needs to happen before modifier conversion as that might change
1149 * the number of planes.
1150 */
1151 for (i = 1; i < rfb->base.format->num_planes; ++i) {
1152 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1153 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1154 i, mode_cmd->handles[0], mode_cmd->handles[i]);
1155 ret = -EINVAL;
1156 return ret;
1157 }
1158 }
1159
1160 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1161 if (ret)
1162 return ret;
1163
1164 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1165 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1166 "GFX9+ requires FB check based on format modifier\n");
1167 ret = check_tiling_flags_gfx6(rfb);
1168 if (ret)
1169 return ret;
1170 }
1171
1172 if (!dev->mode_config.fb_modifiers_not_supported &&
1173 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1174 ret = convert_tiling_flags_to_modifier(rfb);
1175 if (ret) {
1176 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1177 rfb->tiling_flags);
1178 return ret;
1179 }
1180 }
1181
1182 ret = amdgpu_display_verify_sizes(rfb);
1183 if (ret)
1184 return ret;
1185
1186 for (i = 0; i < rfb->base.format->num_planes; ++i) {
1187 drm_gem_object_get(rfb->base.obj[0]);
1188 rfb->base.obj[i] = rfb->base.obj[0];
1189 }
1190
1191 return 0;
1192 }
1193
1194 struct drm_framebuffer *
amdgpu_display_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1195 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1196 struct drm_file *file_priv,
1197 const struct drm_mode_fb_cmd2 *mode_cmd)
1198 {
1199 struct amdgpu_framebuffer *amdgpu_fb;
1200 struct drm_gem_object *obj;
1201 struct amdgpu_bo *bo;
1202 uint32_t domains;
1203 int ret;
1204
1205 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1206 if (obj == NULL) {
1207 drm_dbg_kms(dev,
1208 "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
1209 mode_cmd->handles[0]);
1210
1211 return ERR_PTR(-ENOENT);
1212 }
1213
1214 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1215 bo = gem_to_amdgpu_bo(obj);
1216 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1217 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1218 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1219 drm_gem_object_put(obj);
1220 return ERR_PTR(-EINVAL);
1221 }
1222
1223 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1224 if (amdgpu_fb == NULL) {
1225 drm_gem_object_put(obj);
1226 return ERR_PTR(-ENOMEM);
1227 }
1228
1229 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1230 mode_cmd, obj);
1231 if (ret) {
1232 kfree(amdgpu_fb);
1233 drm_gem_object_put(obj);
1234 return ERR_PTR(ret);
1235 }
1236
1237 drm_gem_object_put(obj);
1238 return &amdgpu_fb->base;
1239 }
1240
1241 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1242 .fb_create = amdgpu_display_user_framebuffer_create,
1243 };
1244
1245 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1246 { { UNDERSCAN_OFF, "off" },
1247 { UNDERSCAN_ON, "on" },
1248 { UNDERSCAN_AUTO, "auto" },
1249 };
1250
1251 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1252 { { AMDGPU_AUDIO_DISABLE, "off" },
1253 { AMDGPU_AUDIO_ENABLE, "on" },
1254 { AMDGPU_AUDIO_AUTO, "auto" },
1255 };
1256
1257 /* XXX support different dither options? spatial, temporal, both, etc. */
1258 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1259 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
1260 { AMDGPU_FMT_DITHER_ENABLE, "on" },
1261 };
1262
amdgpu_display_modeset_create_props(struct amdgpu_device * adev)1263 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1264 {
1265 int sz;
1266
1267 adev->mode_info.coherent_mode_property =
1268 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1269 if (!adev->mode_info.coherent_mode_property)
1270 return -ENOMEM;
1271
1272 adev->mode_info.load_detect_property =
1273 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1274 if (!adev->mode_info.load_detect_property)
1275 return -ENOMEM;
1276
1277 drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1278
1279 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1280 adev->mode_info.underscan_property =
1281 drm_property_create_enum(adev_to_drm(adev), 0,
1282 "underscan",
1283 amdgpu_underscan_enum_list, sz);
1284
1285 adev->mode_info.underscan_hborder_property =
1286 drm_property_create_range(adev_to_drm(adev), 0,
1287 "underscan hborder", 0, 128);
1288 if (!adev->mode_info.underscan_hborder_property)
1289 return -ENOMEM;
1290
1291 adev->mode_info.underscan_vborder_property =
1292 drm_property_create_range(adev_to_drm(adev), 0,
1293 "underscan vborder", 0, 128);
1294 if (!adev->mode_info.underscan_vborder_property)
1295 return -ENOMEM;
1296
1297 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1298 adev->mode_info.audio_property =
1299 drm_property_create_enum(adev_to_drm(adev), 0,
1300 "audio",
1301 amdgpu_audio_enum_list, sz);
1302
1303 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1304 adev->mode_info.dither_property =
1305 drm_property_create_enum(adev_to_drm(adev), 0,
1306 "dither",
1307 amdgpu_dither_enum_list, sz);
1308
1309 if (amdgpu_device_has_dc_support(adev)) {
1310 adev->mode_info.abm_level_property =
1311 drm_property_create_range(adev_to_drm(adev), 0,
1312 "abm level", 0, 4);
1313 if (!adev->mode_info.abm_level_property)
1314 return -ENOMEM;
1315 }
1316
1317 return 0;
1318 }
1319
amdgpu_display_update_priority(struct amdgpu_device * adev)1320 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1321 {
1322 /* adjustment options for the display watermarks */
1323 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1324 adev->mode_info.disp_priority = 0;
1325 else
1326 adev->mode_info.disp_priority = amdgpu_disp_priority;
1327
1328 }
1329
amdgpu_display_is_hdtv_mode(const struct drm_display_mode * mode)1330 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1331 {
1332 /* try and guess if this is a tv or a monitor */
1333 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1334 (mode->vdisplay == 576) || /* 576p */
1335 (mode->vdisplay == 720) || /* 720p */
1336 (mode->vdisplay == 1080)) /* 1080p */
1337 return true;
1338 else
1339 return false;
1340 }
1341
amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1342 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1343 const struct drm_display_mode *mode,
1344 struct drm_display_mode *adjusted_mode)
1345 {
1346 struct drm_device *dev = crtc->dev;
1347 struct drm_encoder *encoder;
1348 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1349 struct amdgpu_encoder *amdgpu_encoder;
1350 struct drm_connector *connector;
1351 u32 src_v = 1, dst_v = 1;
1352 u32 src_h = 1, dst_h = 1;
1353
1354 amdgpu_crtc->h_border = 0;
1355 amdgpu_crtc->v_border = 0;
1356
1357 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1358 if (encoder->crtc != crtc)
1359 continue;
1360 amdgpu_encoder = to_amdgpu_encoder(encoder);
1361 connector = amdgpu_get_connector_for_encoder(encoder);
1362
1363 /* set scaling */
1364 if (amdgpu_encoder->rmx_type == RMX_OFF)
1365 amdgpu_crtc->rmx_type = RMX_OFF;
1366 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1367 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1368 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1369 else
1370 amdgpu_crtc->rmx_type = RMX_OFF;
1371 /* copy native mode */
1372 memcpy(&amdgpu_crtc->native_mode,
1373 &amdgpu_encoder->native_mode,
1374 sizeof(struct drm_display_mode));
1375 src_v = crtc->mode.vdisplay;
1376 dst_v = amdgpu_crtc->native_mode.vdisplay;
1377 src_h = crtc->mode.hdisplay;
1378 dst_h = amdgpu_crtc->native_mode.hdisplay;
1379
1380 /* fix up for overscan on hdmi */
1381 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1382 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1383 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1384 connector->display_info.is_hdmi &&
1385 amdgpu_display_is_hdtv_mode(mode)))) {
1386 if (amdgpu_encoder->underscan_hborder != 0)
1387 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1388 else
1389 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1390 if (amdgpu_encoder->underscan_vborder != 0)
1391 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1392 else
1393 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1394 amdgpu_crtc->rmx_type = RMX_FULL;
1395 src_v = crtc->mode.vdisplay;
1396 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1397 src_h = crtc->mode.hdisplay;
1398 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1399 }
1400 }
1401 if (amdgpu_crtc->rmx_type != RMX_OFF) {
1402 fixed20_12 a, b;
1403
1404 a.full = dfixed_const(src_v);
1405 b.full = dfixed_const(dst_v);
1406 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1407 a.full = dfixed_const(src_h);
1408 b.full = dfixed_const(dst_h);
1409 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1410 } else {
1411 amdgpu_crtc->vsc.full = dfixed_const(1);
1412 amdgpu_crtc->hsc.full = dfixed_const(1);
1413 }
1414 return true;
1415 }
1416
1417 /*
1418 * Retrieve current video scanout position of crtc on a given gpu, and
1419 * an optional accurate timestamp of when query happened.
1420 *
1421 * \param dev Device to query.
1422 * \param pipe Crtc to query.
1423 * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1424 * For driver internal use only also supports these flags:
1425 *
1426 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1427 * of a fudged earlier start of vblank.
1428 *
1429 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1430 * fudged earlier start of vblank in *vpos and the distance
1431 * to true start of vblank in *hpos.
1432 *
1433 * \param *vpos Location where vertical scanout position should be stored.
1434 * \param *hpos Location where horizontal scanout position should go.
1435 * \param *stime Target location for timestamp taken immediately before
1436 * scanout position query. Can be NULL to skip timestamp.
1437 * \param *etime Target location for timestamp taken immediately after
1438 * scanout position query. Can be NULL to skip timestamp.
1439 *
1440 * Returns vpos as a positive number while in active scanout area.
1441 * Returns vpos as a negative number inside vblank, counting the number
1442 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1443 * until start of active scanout / end of vblank."
1444 *
1445 * \return Flags, or'ed together as follows:
1446 *
1447 * DRM_SCANOUTPOS_VALID = Query successful.
1448 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1449 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1450 * this flag means that returned position may be offset by a constant but
1451 * unknown small number of scanlines wrt. real scanout position.
1452 *
1453 */
amdgpu_display_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1454 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1455 unsigned int pipe, unsigned int flags, int *vpos,
1456 int *hpos, ktime_t *stime, ktime_t *etime,
1457 const struct drm_display_mode *mode)
1458 {
1459 u32 vbl = 0, position = 0;
1460 int vbl_start, vbl_end, vtotal, ret = 0;
1461 bool in_vbl = true;
1462
1463 struct amdgpu_device *adev = drm_to_adev(dev);
1464
1465 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1466
1467 /* Get optional system timestamp before query. */
1468 if (stime)
1469 *stime = ktime_get();
1470
1471 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1472 ret |= DRM_SCANOUTPOS_VALID;
1473
1474 /* Get optional system timestamp after query. */
1475 if (etime)
1476 *etime = ktime_get();
1477
1478 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1479
1480 /* Decode into vertical and horizontal scanout position. */
1481 *vpos = position & 0x1fff;
1482 *hpos = (position >> 16) & 0x1fff;
1483
1484 /* Valid vblank area boundaries from gpu retrieved? */
1485 if (vbl > 0) {
1486 /* Yes: Decode. */
1487 ret |= DRM_SCANOUTPOS_ACCURATE;
1488 vbl_start = vbl & 0x1fff;
1489 vbl_end = (vbl >> 16) & 0x1fff;
1490 }
1491 else {
1492 /* No: Fake something reasonable which gives at least ok results. */
1493 vbl_start = mode->crtc_vdisplay;
1494 vbl_end = 0;
1495 }
1496
1497 /* Called from driver internal vblank counter query code? */
1498 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1499 /* Caller wants distance from real vbl_start in *hpos */
1500 *hpos = *vpos - vbl_start;
1501 }
1502
1503 /* Fudge vblank to start a few scanlines earlier to handle the
1504 * problem that vblank irqs fire a few scanlines before start
1505 * of vblank. Some driver internal callers need the true vblank
1506 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1507 *
1508 * The cause of the "early" vblank irq is that the irq is triggered
1509 * by the line buffer logic when the line buffer read position enters
1510 * the vblank, whereas our crtc scanout position naturally lags the
1511 * line buffer read position.
1512 */
1513 if (!(flags & USE_REAL_VBLANKSTART))
1514 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1515
1516 /* Test scanout position against vblank region. */
1517 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1518 in_vbl = false;
1519
1520 /* In vblank? */
1521 if (in_vbl)
1522 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1523
1524 /* Called from driver internal vblank counter query code? */
1525 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1526 /* Caller wants distance from fudged earlier vbl_start */
1527 *vpos -= vbl_start;
1528 return ret;
1529 }
1530
1531 /* Check if inside vblank area and apply corrective offsets:
1532 * vpos will then be >=0 in video scanout area, but negative
1533 * within vblank area, counting down the number of lines until
1534 * start of scanout.
1535 */
1536
1537 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1538 if (in_vbl && (*vpos >= vbl_start)) {
1539 vtotal = mode->crtc_vtotal;
1540
1541 /* With variable refresh rate displays the vpos can exceed
1542 * the vtotal value. Clamp to 0 to return -vbl_end instead
1543 * of guessing the remaining number of lines until scanout.
1544 */
1545 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1546 }
1547
1548 /* Correct for shifted end of vbl at vbl_end. */
1549 *vpos = *vpos - vbl_end;
1550
1551 return ret;
1552 }
1553
amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)1554 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1555 {
1556 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1557 return AMDGPU_CRTC_IRQ_NONE;
1558
1559 switch (crtc) {
1560 case 0:
1561 return AMDGPU_CRTC_IRQ_VBLANK1;
1562 case 1:
1563 return AMDGPU_CRTC_IRQ_VBLANK2;
1564 case 2:
1565 return AMDGPU_CRTC_IRQ_VBLANK3;
1566 case 3:
1567 return AMDGPU_CRTC_IRQ_VBLANK4;
1568 case 4:
1569 return AMDGPU_CRTC_IRQ_VBLANK5;
1570 case 5:
1571 return AMDGPU_CRTC_IRQ_VBLANK6;
1572 default:
1573 return AMDGPU_CRTC_IRQ_NONE;
1574 }
1575 }
1576
amdgpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1577 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1578 bool in_vblank_irq, int *vpos,
1579 int *hpos, ktime_t *stime, ktime_t *etime,
1580 const struct drm_display_mode *mode)
1581 {
1582 struct drm_device *dev = crtc->dev;
1583 unsigned int pipe = crtc->index;
1584
1585 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1586 stime, etime, mode);
1587 }
1588
1589 static bool
amdgpu_display_robj_is_fb(struct amdgpu_device * adev,struct amdgpu_bo * robj)1590 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1591 {
1592 struct drm_device *dev = adev_to_drm(adev);
1593 struct drm_fb_helper *fb_helper = dev->fb_helper;
1594
1595 if (!fb_helper || !fb_helper->buffer)
1596 return false;
1597
1598 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1599 return false;
1600
1601 return true;
1602 }
1603
amdgpu_display_suspend_helper(struct amdgpu_device * adev)1604 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1605 {
1606 struct drm_device *dev = adev_to_drm(adev);
1607 struct drm_crtc *crtc;
1608 struct drm_connector *connector;
1609 struct drm_connector_list_iter iter;
1610 int r;
1611
1612 /* turn off display hw */
1613 drm_modeset_lock_all(dev);
1614 drm_connector_list_iter_begin(dev, &iter);
1615 drm_for_each_connector_iter(connector, &iter)
1616 drm_helper_connector_dpms(connector,
1617 DRM_MODE_DPMS_OFF);
1618 drm_connector_list_iter_end(&iter);
1619 drm_modeset_unlock_all(dev);
1620 /* unpin the front buffers and cursors */
1621 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1622 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1623 struct drm_framebuffer *fb = crtc->primary->fb;
1624 struct amdgpu_bo *robj;
1625
1626 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1627 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1628
1629 r = amdgpu_bo_reserve(aobj, true);
1630 if (r == 0) {
1631 amdgpu_bo_unpin(aobj);
1632 amdgpu_bo_unreserve(aobj);
1633 }
1634 }
1635
1636 if (!fb || !fb->obj[0])
1637 continue;
1638
1639 robj = gem_to_amdgpu_bo(fb->obj[0]);
1640 if (!amdgpu_display_robj_is_fb(adev, robj)) {
1641 r = amdgpu_bo_reserve(robj, true);
1642 if (r == 0) {
1643 amdgpu_bo_unpin(robj);
1644 amdgpu_bo_unreserve(robj);
1645 }
1646 }
1647 }
1648 return 0;
1649 }
1650
amdgpu_display_resume_helper(struct amdgpu_device * adev)1651 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1652 {
1653 struct drm_device *dev = adev_to_drm(adev);
1654 struct drm_connector *connector;
1655 struct drm_connector_list_iter iter;
1656 struct drm_crtc *crtc;
1657 int r;
1658
1659 /* pin cursors */
1660 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1661 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1662
1663 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1664 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1665
1666 r = amdgpu_bo_reserve(aobj, true);
1667 if (r == 0) {
1668 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1669 if (r != 0)
1670 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1671 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1672 amdgpu_bo_unreserve(aobj);
1673 }
1674 }
1675 }
1676
1677 drm_helper_resume_force_mode(dev);
1678
1679 /* turn on display hw */
1680 drm_modeset_lock_all(dev);
1681
1682 drm_connector_list_iter_begin(dev, &iter);
1683 drm_for_each_connector_iter(connector, &iter)
1684 drm_helper_connector_dpms(connector,
1685 DRM_MODE_DPMS_ON);
1686 drm_connector_list_iter_end(&iter);
1687
1688 drm_modeset_unlock_all(dev);
1689
1690 return 0;
1691 }
1692
1693