1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_drv.h>
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
34 #include "atom.h"
35
36 #include <linux/vga_switcheroo.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pci.h>
40 #include <linux/pm_runtime.h>
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_gem.h"
43 #include "amdgpu_display.h"
44 #include "amdgpu_ras.h"
45
amdgpu_unregister_gpu_instance(struct amdgpu_device * adev)46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
47 {
48 struct amdgpu_gpu_instance *gpu_instance;
49 int i;
50
51 mutex_lock(&mgpu_info.mutex);
52
53 for (i = 0; i < mgpu_info.num_gpu; i++) {
54 gpu_instance = &(mgpu_info.gpu_ins[i]);
55 if (gpu_instance->adev == adev) {
56 mgpu_info.gpu_ins[i] =
57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
58 mgpu_info.num_gpu--;
59 if (adev->flags & AMD_IS_APU)
60 mgpu_info.num_apu--;
61 else
62 mgpu_info.num_dgpu--;
63 break;
64 }
65 }
66
67 mutex_unlock(&mgpu_info.mutex);
68 }
69
70 /**
71 * amdgpu_driver_unload_kms - Main unload function for KMS.
72 *
73 * @dev: drm dev pointer
74 *
75 * This is the main unload function for KMS (all asics).
76 * Returns 0 on success.
77 */
amdgpu_driver_unload_kms(struct drm_device * dev)78 void amdgpu_driver_unload_kms(struct drm_device *dev)
79 {
80 struct amdgpu_device *adev = drm_to_adev(dev);
81
82 if (adev == NULL)
83 return;
84
85 amdgpu_unregister_gpu_instance(adev);
86
87 if (adev->rmmio == NULL)
88 return;
89
90 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
91 DRM_WARN("smart shift update failed\n");
92
93 amdgpu_acpi_fini(adev);
94 amdgpu_device_fini_hw(adev);
95 }
96
amdgpu_register_gpu_instance(struct amdgpu_device * adev)97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
98 {
99 struct amdgpu_gpu_instance *gpu_instance;
100
101 mutex_lock(&mgpu_info.mutex);
102
103 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
104 DRM_ERROR("Cannot register more gpu instance\n");
105 mutex_unlock(&mgpu_info.mutex);
106 return;
107 }
108
109 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
110 gpu_instance->adev = adev;
111 gpu_instance->mgpu_fan_enabled = 0;
112
113 mgpu_info.num_gpu++;
114 if (adev->flags & AMD_IS_APU)
115 mgpu_info.num_apu++;
116 else
117 mgpu_info.num_dgpu++;
118
119 mutex_unlock(&mgpu_info.mutex);
120 }
121
122 /**
123 * amdgpu_driver_load_kms - Main load function for KMS.
124 *
125 * @adev: pointer to struct amdgpu_device
126 * @flags: device flags
127 *
128 * This is the main load function for KMS (all asics).
129 * Returns 0 on success, error on failure.
130 */
amdgpu_driver_load_kms(struct amdgpu_device * adev,unsigned long flags)131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
132 {
133 struct drm_device *dev;
134 int r, acpi_status;
135
136 dev = adev_to_drm(adev);
137
138 /* amdgpu_device_init should report only fatal error
139 * like memory allocation failure or iomapping failure,
140 * or memory manager initialization failure, it must
141 * properly initialize the GPU MC controller and permit
142 * VRAM allocation
143 */
144 r = amdgpu_device_init(adev, flags);
145 if (r) {
146 dev_err(dev->dev, "Fatal error during GPU init\n");
147 goto out;
148 }
149
150 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
151 if (amdgpu_device_supports_px(dev) &&
152 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
153 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
154 dev_info(adev->dev, "Using ATPX for runtime pm\n");
155 } else if (amdgpu_device_supports_boco(dev) &&
156 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
157 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
158 dev_info(adev->dev, "Using BOCO for runtime pm\n");
159 } else if (amdgpu_device_supports_baco(dev) &&
160 (amdgpu_runtime_pm != 0)) {
161 switch (adev->asic_type) {
162 case CHIP_VEGA20:
163 case CHIP_ARCTURUS:
164 /* enable BACO as runpm mode if runpm=1 */
165 if (amdgpu_runtime_pm > 0)
166 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
167 break;
168 case CHIP_VEGA10:
169 /* enable BACO as runpm mode if noretry=0 */
170 if (!adev->gmc.noretry)
171 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
172 break;
173 default:
174 /* enable BACO as runpm mode on CI+ */
175 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
176 break;
177 }
178
179 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
180 dev_info(adev->dev, "Using BACO for runtime pm\n");
181 }
182
183 /* Call ACPI methods: require modeset init
184 * but failure is not fatal
185 */
186
187 acpi_status = amdgpu_acpi_init(adev);
188 if (acpi_status)
189 dev_dbg(dev->dev, "Error during ACPI methods call\n");
190
191 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
192 DRM_WARN("smart shift update failed\n");
193
194 out:
195 if (r)
196 amdgpu_driver_unload_kms(dev);
197
198 return r;
199 }
200
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
202 struct drm_amdgpu_query_fw *query_fw,
203 struct amdgpu_device *adev)
204 {
205 switch (query_fw->fw_type) {
206 case AMDGPU_INFO_FW_VCE:
207 fw_info->ver = adev->vce.fw_version;
208 fw_info->feature = adev->vce.fb_version;
209 break;
210 case AMDGPU_INFO_FW_UVD:
211 fw_info->ver = adev->uvd.fw_version;
212 fw_info->feature = 0;
213 break;
214 case AMDGPU_INFO_FW_VCN:
215 fw_info->ver = adev->vcn.fw_version;
216 fw_info->feature = 0;
217 break;
218 case AMDGPU_INFO_FW_GMC:
219 fw_info->ver = adev->gmc.fw_version;
220 fw_info->feature = 0;
221 break;
222 case AMDGPU_INFO_FW_GFX_ME:
223 fw_info->ver = adev->gfx.me_fw_version;
224 fw_info->feature = adev->gfx.me_feature_version;
225 break;
226 case AMDGPU_INFO_FW_GFX_PFP:
227 fw_info->ver = adev->gfx.pfp_fw_version;
228 fw_info->feature = adev->gfx.pfp_feature_version;
229 break;
230 case AMDGPU_INFO_FW_GFX_CE:
231 fw_info->ver = adev->gfx.ce_fw_version;
232 fw_info->feature = adev->gfx.ce_feature_version;
233 break;
234 case AMDGPU_INFO_FW_GFX_RLC:
235 fw_info->ver = adev->gfx.rlc_fw_version;
236 fw_info->feature = adev->gfx.rlc_feature_version;
237 break;
238 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
239 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
240 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
241 break;
242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
243 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
244 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
245 break;
246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
247 fw_info->ver = adev->gfx.rlc_srls_fw_version;
248 fw_info->feature = adev->gfx.rlc_srls_feature_version;
249 break;
250 case AMDGPU_INFO_FW_GFX_RLCP:
251 fw_info->ver = adev->gfx.rlcp_ucode_version;
252 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
253 break;
254 case AMDGPU_INFO_FW_GFX_RLCV:
255 fw_info->ver = adev->gfx.rlcv_ucode_version;
256 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
257 break;
258 case AMDGPU_INFO_FW_GFX_MEC:
259 if (query_fw->index == 0) {
260 fw_info->ver = adev->gfx.mec_fw_version;
261 fw_info->feature = adev->gfx.mec_feature_version;
262 } else if (query_fw->index == 1) {
263 fw_info->ver = adev->gfx.mec2_fw_version;
264 fw_info->feature = adev->gfx.mec2_feature_version;
265 } else
266 return -EINVAL;
267 break;
268 case AMDGPU_INFO_FW_SMC:
269 fw_info->ver = adev->pm.fw_version;
270 fw_info->feature = 0;
271 break;
272 case AMDGPU_INFO_FW_TA:
273 switch (query_fw->index) {
274 case TA_FW_TYPE_PSP_XGMI:
275 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
276 fw_info->feature = adev->psp.xgmi_context.context
277 .bin_desc.feature_version;
278 break;
279 case TA_FW_TYPE_PSP_RAS:
280 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
281 fw_info->feature = adev->psp.ras_context.context
282 .bin_desc.feature_version;
283 break;
284 case TA_FW_TYPE_PSP_HDCP:
285 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
286 fw_info->feature = adev->psp.hdcp_context.context
287 .bin_desc.feature_version;
288 break;
289 case TA_FW_TYPE_PSP_DTM:
290 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
291 fw_info->feature = adev->psp.dtm_context.context
292 .bin_desc.feature_version;
293 break;
294 case TA_FW_TYPE_PSP_RAP:
295 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
296 fw_info->feature = adev->psp.rap_context.context
297 .bin_desc.feature_version;
298 break;
299 case TA_FW_TYPE_PSP_SECUREDISPLAY:
300 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
301 fw_info->feature =
302 adev->psp.securedisplay_context.context.bin_desc
303 .feature_version;
304 break;
305 default:
306 return -EINVAL;
307 }
308 break;
309 case AMDGPU_INFO_FW_SDMA:
310 if (query_fw->index >= adev->sdma.num_instances)
311 return -EINVAL;
312 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
313 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
314 break;
315 case AMDGPU_INFO_FW_SOS:
316 fw_info->ver = adev->psp.sos.fw_version;
317 fw_info->feature = adev->psp.sos.feature_version;
318 break;
319 case AMDGPU_INFO_FW_ASD:
320 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
321 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
322 break;
323 case AMDGPU_INFO_FW_DMCU:
324 fw_info->ver = adev->dm.dmcu_fw_version;
325 fw_info->feature = 0;
326 break;
327 case AMDGPU_INFO_FW_DMCUB:
328 fw_info->ver = adev->dm.dmcub_fw_version;
329 fw_info->feature = 0;
330 break;
331 case AMDGPU_INFO_FW_TOC:
332 fw_info->ver = adev->psp.toc.fw_version;
333 fw_info->feature = adev->psp.toc.feature_version;
334 break;
335 case AMDGPU_INFO_FW_CAP:
336 fw_info->ver = adev->psp.cap_fw_version;
337 fw_info->feature = adev->psp.cap_feature_version;
338 break;
339 case AMDGPU_INFO_FW_MES_KIQ:
340 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
341 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
342 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
343 break;
344 case AMDGPU_INFO_FW_MES:
345 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
346 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
347 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
348 break;
349 case AMDGPU_INFO_FW_IMU:
350 fw_info->ver = adev->gfx.imu_fw_version;
351 fw_info->feature = 0;
352 break;
353 default:
354 return -EINVAL;
355 }
356 return 0;
357 }
358
amdgpu_hw_ip_info(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_hw_ip * result)359 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
360 struct drm_amdgpu_info *info,
361 struct drm_amdgpu_info_hw_ip *result)
362 {
363 uint32_t ib_start_alignment = 0;
364 uint32_t ib_size_alignment = 0;
365 enum amd_ip_block_type type;
366 unsigned int num_rings = 0;
367 unsigned int i, j;
368
369 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
370 return -EINVAL;
371
372 switch (info->query_hw_ip.type) {
373 case AMDGPU_HW_IP_GFX:
374 type = AMD_IP_BLOCK_TYPE_GFX;
375 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
376 if (adev->gfx.gfx_ring[i].sched.ready)
377 ++num_rings;
378 ib_start_alignment = 32;
379 ib_size_alignment = 32;
380 break;
381 case AMDGPU_HW_IP_COMPUTE:
382 type = AMD_IP_BLOCK_TYPE_GFX;
383 for (i = 0; i < adev->gfx.num_compute_rings; i++)
384 if (adev->gfx.compute_ring[i].sched.ready)
385 ++num_rings;
386 ib_start_alignment = 32;
387 ib_size_alignment = 32;
388 break;
389 case AMDGPU_HW_IP_DMA:
390 type = AMD_IP_BLOCK_TYPE_SDMA;
391 for (i = 0; i < adev->sdma.num_instances; i++)
392 if (adev->sdma.instance[i].ring.sched.ready)
393 ++num_rings;
394 ib_start_alignment = 256;
395 ib_size_alignment = 4;
396 break;
397 case AMDGPU_HW_IP_UVD:
398 type = AMD_IP_BLOCK_TYPE_UVD;
399 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
400 if (adev->uvd.harvest_config & (1 << i))
401 continue;
402
403 if (adev->uvd.inst[i].ring.sched.ready)
404 ++num_rings;
405 }
406 ib_start_alignment = 64;
407 ib_size_alignment = 64;
408 break;
409 case AMDGPU_HW_IP_VCE:
410 type = AMD_IP_BLOCK_TYPE_VCE;
411 for (i = 0; i < adev->vce.num_rings; i++)
412 if (adev->vce.ring[i].sched.ready)
413 ++num_rings;
414 ib_start_alignment = 4;
415 ib_size_alignment = 1;
416 break;
417 case AMDGPU_HW_IP_UVD_ENC:
418 type = AMD_IP_BLOCK_TYPE_UVD;
419 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
420 if (adev->uvd.harvest_config & (1 << i))
421 continue;
422
423 for (j = 0; j < adev->uvd.num_enc_rings; j++)
424 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
425 ++num_rings;
426 }
427 ib_start_alignment = 64;
428 ib_size_alignment = 64;
429 break;
430 case AMDGPU_HW_IP_VCN_DEC:
431 type = AMD_IP_BLOCK_TYPE_VCN;
432 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
433 if (adev->uvd.harvest_config & (1 << i))
434 continue;
435
436 if (adev->vcn.inst[i].ring_dec.sched.ready)
437 ++num_rings;
438 }
439 ib_start_alignment = 16;
440 ib_size_alignment = 16;
441 break;
442 case AMDGPU_HW_IP_VCN_ENC:
443 type = AMD_IP_BLOCK_TYPE_VCN;
444 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
445 if (adev->uvd.harvest_config & (1 << i))
446 continue;
447
448 for (j = 0; j < adev->vcn.num_enc_rings; j++)
449 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
450 ++num_rings;
451 }
452 ib_start_alignment = 64;
453 ib_size_alignment = 1;
454 break;
455 case AMDGPU_HW_IP_VCN_JPEG:
456 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
457 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
458
459 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
460 if (adev->jpeg.harvest_config & (1 << i))
461 continue;
462
463 if (adev->jpeg.inst[i].ring_dec.sched.ready)
464 ++num_rings;
465 }
466 ib_start_alignment = 16;
467 ib_size_alignment = 16;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 for (i = 0; i < adev->num_ip_blocks; i++)
474 if (adev->ip_blocks[i].version->type == type &&
475 adev->ip_blocks[i].status.valid)
476 break;
477
478 if (i == adev->num_ip_blocks)
479 return 0;
480
481 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
482 num_rings);
483
484 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
485 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
486
487 if (adev->asic_type >= CHIP_VEGA10) {
488 switch (type) {
489 case AMD_IP_BLOCK_TYPE_GFX:
490 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
491 break;
492 case AMD_IP_BLOCK_TYPE_SDMA:
493 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
494 break;
495 case AMD_IP_BLOCK_TYPE_UVD:
496 case AMD_IP_BLOCK_TYPE_VCN:
497 case AMD_IP_BLOCK_TYPE_JPEG:
498 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
499 break;
500 case AMD_IP_BLOCK_TYPE_VCE:
501 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
502 break;
503 default:
504 result->ip_discovery_version = 0;
505 break;
506 }
507 } else {
508 result->ip_discovery_version = 0;
509 }
510 result->capabilities_flags = 0;
511 result->available_rings = (1 << num_rings) - 1;
512 result->ib_start_alignment = ib_start_alignment;
513 result->ib_size_alignment = ib_size_alignment;
514 return 0;
515 }
516
517 /*
518 * Userspace get information ioctl
519 */
520 /**
521 * amdgpu_info_ioctl - answer a device specific request.
522 *
523 * @dev: drm device pointer
524 * @data: request object
525 * @filp: drm filp
526 *
527 * This function is used to pass device specific parameters to the userspace
528 * drivers. Examples include: pci device id, pipeline parms, tiling params,
529 * etc. (all asics).
530 * Returns 0 on success, -EINVAL on failure.
531 */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)532 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
533 {
534 struct amdgpu_device *adev = drm_to_adev(dev);
535 struct drm_amdgpu_info *info = data;
536 struct amdgpu_mode_info *minfo = &adev->mode_info;
537 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
538 uint32_t size = info->return_size;
539 struct drm_crtc *crtc;
540 uint32_t ui32 = 0;
541 uint64_t ui64 = 0;
542 int i, found;
543 int ui32_size = sizeof(ui32);
544
545 if (!info->return_size || !info->return_pointer)
546 return -EINVAL;
547
548 switch (info->query) {
549 case AMDGPU_INFO_ACCEL_WORKING:
550 ui32 = adev->accel_working;
551 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
552 case AMDGPU_INFO_CRTC_FROM_ID:
553 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
554 crtc = (struct drm_crtc *)minfo->crtcs[i];
555 if (crtc && crtc->base.id == info->mode_crtc.id) {
556 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
557
558 ui32 = amdgpu_crtc->crtc_id;
559 found = 1;
560 break;
561 }
562 }
563 if (!found) {
564 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
565 return -EINVAL;
566 }
567 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
568 case AMDGPU_INFO_HW_IP_INFO: {
569 struct drm_amdgpu_info_hw_ip ip = {};
570 int ret;
571
572 ret = amdgpu_hw_ip_info(adev, info, &ip);
573 if (ret)
574 return ret;
575
576 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
577 return ret ? -EFAULT : 0;
578 }
579 case AMDGPU_INFO_HW_IP_COUNT: {
580 enum amd_ip_block_type type;
581 uint32_t count = 0;
582
583 switch (info->query_hw_ip.type) {
584 case AMDGPU_HW_IP_GFX:
585 type = AMD_IP_BLOCK_TYPE_GFX;
586 break;
587 case AMDGPU_HW_IP_COMPUTE:
588 type = AMD_IP_BLOCK_TYPE_GFX;
589 break;
590 case AMDGPU_HW_IP_DMA:
591 type = AMD_IP_BLOCK_TYPE_SDMA;
592 break;
593 case AMDGPU_HW_IP_UVD:
594 type = AMD_IP_BLOCK_TYPE_UVD;
595 break;
596 case AMDGPU_HW_IP_VCE:
597 type = AMD_IP_BLOCK_TYPE_VCE;
598 break;
599 case AMDGPU_HW_IP_UVD_ENC:
600 type = AMD_IP_BLOCK_TYPE_UVD;
601 break;
602 case AMDGPU_HW_IP_VCN_DEC:
603 case AMDGPU_HW_IP_VCN_ENC:
604 type = AMD_IP_BLOCK_TYPE_VCN;
605 break;
606 case AMDGPU_HW_IP_VCN_JPEG:
607 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
608 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
609 break;
610 default:
611 return -EINVAL;
612 }
613
614 for (i = 0; i < adev->num_ip_blocks; i++)
615 if (adev->ip_blocks[i].version->type == type &&
616 adev->ip_blocks[i].status.valid &&
617 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
618 count++;
619
620 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
621 }
622 case AMDGPU_INFO_TIMESTAMP:
623 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
624 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
625 case AMDGPU_INFO_FW_VERSION: {
626 struct drm_amdgpu_info_firmware fw_info;
627 int ret;
628
629 /* We only support one instance of each IP block right now. */
630 if (info->query_fw.ip_instance != 0)
631 return -EINVAL;
632
633 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
634 if (ret)
635 return ret;
636
637 return copy_to_user(out, &fw_info,
638 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
639 }
640 case AMDGPU_INFO_NUM_BYTES_MOVED:
641 ui64 = atomic64_read(&adev->num_bytes_moved);
642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
643 case AMDGPU_INFO_NUM_EVICTIONS:
644 ui64 = atomic64_read(&adev->num_evictions);
645 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
646 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
647 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
648 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
649 case AMDGPU_INFO_VRAM_USAGE:
650 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
651 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
652 case AMDGPU_INFO_VIS_VRAM_USAGE:
653 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
654 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
655 case AMDGPU_INFO_GTT_USAGE:
656 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
657 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
658 case AMDGPU_INFO_GDS_CONFIG: {
659 struct drm_amdgpu_info_gds gds_info;
660
661 memset(&gds_info, 0, sizeof(gds_info));
662 gds_info.compute_partition_size = adev->gds.gds_size;
663 gds_info.gds_total_size = adev->gds.gds_size;
664 gds_info.gws_per_compute_partition = adev->gds.gws_size;
665 gds_info.oa_per_compute_partition = adev->gds.oa_size;
666 return copy_to_user(out, &gds_info,
667 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
668 }
669 case AMDGPU_INFO_VRAM_GTT: {
670 struct drm_amdgpu_info_vram_gtt vram_gtt;
671
672 vram_gtt.vram_size = adev->gmc.real_vram_size -
673 atomic64_read(&adev->vram_pin_size) -
674 AMDGPU_VM_RESERVED_VRAM;
675 vram_gtt.vram_cpu_accessible_size =
676 min(adev->gmc.visible_vram_size -
677 atomic64_read(&adev->visible_pin_size),
678 vram_gtt.vram_size);
679 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
680 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
681 return copy_to_user(out, &vram_gtt,
682 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
683 }
684 case AMDGPU_INFO_MEMORY: {
685 struct drm_amdgpu_memory_info mem;
686 struct ttm_resource_manager *gtt_man =
687 &adev->mman.gtt_mgr.manager;
688 struct ttm_resource_manager *vram_man =
689 &adev->mman.vram_mgr.manager;
690
691 memset(&mem, 0, sizeof(mem));
692 mem.vram.total_heap_size = adev->gmc.real_vram_size;
693 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
694 atomic64_read(&adev->vram_pin_size) -
695 AMDGPU_VM_RESERVED_VRAM;
696 mem.vram.heap_usage =
697 ttm_resource_manager_usage(vram_man);
698 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
699
700 mem.cpu_accessible_vram.total_heap_size =
701 adev->gmc.visible_vram_size;
702 mem.cpu_accessible_vram.usable_heap_size =
703 min(adev->gmc.visible_vram_size -
704 atomic64_read(&adev->visible_pin_size),
705 mem.vram.usable_heap_size);
706 mem.cpu_accessible_vram.heap_usage =
707 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
708 mem.cpu_accessible_vram.max_allocation =
709 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
710
711 mem.gtt.total_heap_size = gtt_man->size;
712 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
713 atomic64_read(&adev->gart_pin_size);
714 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
715 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
716
717 return copy_to_user(out, &mem,
718 min((size_t)size, sizeof(mem)))
719 ? -EFAULT : 0;
720 }
721 case AMDGPU_INFO_READ_MMR_REG: {
722 unsigned int n, alloc_size;
723 uint32_t *regs;
724 unsigned int se_num = (info->read_mmr_reg.instance >>
725 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
726 AMDGPU_INFO_MMR_SE_INDEX_MASK;
727 unsigned int sh_num = (info->read_mmr_reg.instance >>
728 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
729 AMDGPU_INFO_MMR_SH_INDEX_MASK;
730
731 /* set full masks if the userspace set all bits
732 * in the bitfields
733 */
734 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
735 se_num = 0xffffffff;
736 else if (se_num >= AMDGPU_GFX_MAX_SE)
737 return -EINVAL;
738 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
739 sh_num = 0xffffffff;
740 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
741 return -EINVAL;
742
743 if (info->read_mmr_reg.count > 128)
744 return -EINVAL;
745
746 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
747 if (!regs)
748 return -ENOMEM;
749 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
750
751 amdgpu_gfx_off_ctrl(adev, false);
752 for (i = 0; i < info->read_mmr_reg.count; i++) {
753 if (amdgpu_asic_read_register(adev, se_num, sh_num,
754 info->read_mmr_reg.dword_offset + i,
755 ®s[i])) {
756 DRM_DEBUG_KMS("unallowed offset %#x\n",
757 info->read_mmr_reg.dword_offset + i);
758 kfree(regs);
759 amdgpu_gfx_off_ctrl(adev, true);
760 return -EFAULT;
761 }
762 }
763 amdgpu_gfx_off_ctrl(adev, true);
764 n = copy_to_user(out, regs, min(size, alloc_size));
765 kfree(regs);
766 return n ? -EFAULT : 0;
767 }
768 case AMDGPU_INFO_DEV_INFO: {
769 struct drm_amdgpu_info_device *dev_info;
770 uint64_t vm_size;
771 int ret;
772
773 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
774 if (!dev_info)
775 return -ENOMEM;
776
777 dev_info->device_id = adev->pdev->device;
778 dev_info->chip_rev = adev->rev_id;
779 dev_info->external_rev = adev->external_rev_id;
780 dev_info->pci_rev = adev->pdev->revision;
781 dev_info->family = adev->family;
782 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
783 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
784 /* return all clocks in KHz */
785 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
786 if (adev->pm.dpm_enabled) {
787 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
788 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
789 } else {
790 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
791 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
792 }
793 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
794 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
795 adev->gfx.config.max_shader_engines;
796 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
797 dev_info->_pad = 0;
798 dev_info->ids_flags = 0;
799 if (adev->flags & AMD_IS_APU)
800 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
801 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
802 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
803 if (amdgpu_is_tmz(adev))
804 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
805
806 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
807 vm_size -= AMDGPU_VA_RESERVED_SIZE;
808
809 /* Older VCE FW versions are buggy and can handle only 40bits */
810 if (adev->vce.fw_version &&
811 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
812 vm_size = min(vm_size, 1ULL << 40);
813
814 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
815 dev_info->virtual_address_max =
816 min(vm_size, AMDGPU_GMC_HOLE_START);
817
818 if (vm_size > AMDGPU_GMC_HOLE_START) {
819 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
820 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
821 }
822 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
823 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
824 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
825 dev_info->cu_active_number = adev->gfx.cu_info.number;
826 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
827 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
828 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
829 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
830 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
831 sizeof(adev->gfx.cu_info.bitmap));
832 dev_info->vram_type = adev->gmc.vram_type;
833 dev_info->vram_bit_width = adev->gmc.vram_width;
834 dev_info->vce_harvest_config = adev->vce.harvest_config;
835 dev_info->gc_double_offchip_lds_buf =
836 adev->gfx.config.double_offchip_lds_buf;
837 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
838 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
839 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
840 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
841 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
842 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
843 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
844
845 if (adev->family >= AMDGPU_FAMILY_NV)
846 dev_info->pa_sc_tile_steering_override =
847 adev->gfx.config.pa_sc_tile_steering_override;
848
849 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
850
851 ret = copy_to_user(out, dev_info,
852 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
853 kfree(dev_info);
854 return ret;
855 }
856 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
857 unsigned int i;
858 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
859 struct amd_vce_state *vce_state;
860
861 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
862 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
863 if (vce_state) {
864 vce_clk_table.entries[i].sclk = vce_state->sclk;
865 vce_clk_table.entries[i].mclk = vce_state->mclk;
866 vce_clk_table.entries[i].eclk = vce_state->evclk;
867 vce_clk_table.num_valid_entries++;
868 }
869 }
870
871 return copy_to_user(out, &vce_clk_table,
872 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
873 }
874 case AMDGPU_INFO_VBIOS: {
875 uint32_t bios_size = adev->bios_size;
876
877 switch (info->vbios_info.type) {
878 case AMDGPU_INFO_VBIOS_SIZE:
879 return copy_to_user(out, &bios_size,
880 min((size_t)size, sizeof(bios_size)))
881 ? -EFAULT : 0;
882 case AMDGPU_INFO_VBIOS_IMAGE: {
883 uint8_t *bios;
884 uint32_t bios_offset = info->vbios_info.offset;
885
886 if (bios_offset >= bios_size)
887 return -EINVAL;
888
889 bios = adev->bios + bios_offset;
890 return copy_to_user(out, bios,
891 min((size_t)size, (size_t)(bios_size - bios_offset)))
892 ? -EFAULT : 0;
893 }
894 case AMDGPU_INFO_VBIOS_INFO: {
895 struct drm_amdgpu_info_vbios vbios_info = {};
896 struct atom_context *atom_context;
897
898 atom_context = adev->mode_info.atom_context;
899 if (atom_context) {
900 memcpy(vbios_info.name, atom_context->name,
901 sizeof(atom_context->name));
902 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
903 sizeof(atom_context->vbios_pn));
904 vbios_info.version = atom_context->version;
905 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
906 sizeof(atom_context->vbios_ver_str));
907 memcpy(vbios_info.date, atom_context->date,
908 sizeof(atom_context->date));
909 }
910
911 return copy_to_user(out, &vbios_info,
912 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
913 }
914 default:
915 DRM_DEBUG_KMS("Invalid request %d\n",
916 info->vbios_info.type);
917 return -EINVAL;
918 }
919 }
920 case AMDGPU_INFO_NUM_HANDLES: {
921 struct drm_amdgpu_info_num_handles handle;
922
923 switch (info->query_hw_ip.type) {
924 case AMDGPU_HW_IP_UVD:
925 /* Starting Polaris, we support unlimited UVD handles */
926 if (adev->asic_type < CHIP_POLARIS10) {
927 handle.uvd_max_handles = adev->uvd.max_handles;
928 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
929
930 return copy_to_user(out, &handle,
931 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
932 } else {
933 return -ENODATA;
934 }
935
936 break;
937 default:
938 return -EINVAL;
939 }
940 }
941 case AMDGPU_INFO_SENSOR: {
942 if (!adev->pm.dpm_enabled)
943 return -ENOENT;
944
945 switch (info->sensor_info.type) {
946 case AMDGPU_INFO_SENSOR_GFX_SCLK:
947 /* get sclk in Mhz */
948 if (amdgpu_dpm_read_sensor(adev,
949 AMDGPU_PP_SENSOR_GFX_SCLK,
950 (void *)&ui32, &ui32_size)) {
951 return -EINVAL;
952 }
953 ui32 /= 100;
954 break;
955 case AMDGPU_INFO_SENSOR_GFX_MCLK:
956 /* get mclk in Mhz */
957 if (amdgpu_dpm_read_sensor(adev,
958 AMDGPU_PP_SENSOR_GFX_MCLK,
959 (void *)&ui32, &ui32_size)) {
960 return -EINVAL;
961 }
962 ui32 /= 100;
963 break;
964 case AMDGPU_INFO_SENSOR_GPU_TEMP:
965 /* get temperature in millidegrees C */
966 if (amdgpu_dpm_read_sensor(adev,
967 AMDGPU_PP_SENSOR_GPU_TEMP,
968 (void *)&ui32, &ui32_size)) {
969 return -EINVAL;
970 }
971 break;
972 case AMDGPU_INFO_SENSOR_GPU_LOAD:
973 /* get GPU load */
974 if (amdgpu_dpm_read_sensor(adev,
975 AMDGPU_PP_SENSOR_GPU_LOAD,
976 (void *)&ui32, &ui32_size)) {
977 return -EINVAL;
978 }
979 break;
980 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
981 /* get average GPU power */
982 if (amdgpu_dpm_read_sensor(adev,
983 AMDGPU_PP_SENSOR_GPU_POWER,
984 (void *)&ui32, &ui32_size)) {
985 return -EINVAL;
986 }
987 ui32 >>= 8;
988 break;
989 case AMDGPU_INFO_SENSOR_VDDNB:
990 /* get VDDNB in millivolts */
991 if (amdgpu_dpm_read_sensor(adev,
992 AMDGPU_PP_SENSOR_VDDNB,
993 (void *)&ui32, &ui32_size)) {
994 return -EINVAL;
995 }
996 break;
997 case AMDGPU_INFO_SENSOR_VDDGFX:
998 /* get VDDGFX in millivolts */
999 if (amdgpu_dpm_read_sensor(adev,
1000 AMDGPU_PP_SENSOR_VDDGFX,
1001 (void *)&ui32, &ui32_size)) {
1002 return -EINVAL;
1003 }
1004 break;
1005 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1006 /* get stable pstate sclk in Mhz */
1007 if (amdgpu_dpm_read_sensor(adev,
1008 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1009 (void *)&ui32, &ui32_size)) {
1010 return -EINVAL;
1011 }
1012 ui32 /= 100;
1013 break;
1014 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1015 /* get stable pstate mclk in Mhz */
1016 if (amdgpu_dpm_read_sensor(adev,
1017 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1018 (void *)&ui32, &ui32_size)) {
1019 return -EINVAL;
1020 }
1021 ui32 /= 100;
1022 break;
1023 default:
1024 DRM_DEBUG_KMS("Invalid request %d\n",
1025 info->sensor_info.type);
1026 return -EINVAL;
1027 }
1028 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1029 }
1030 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1031 ui32 = atomic_read(&adev->vram_lost_counter);
1032 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1033 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1034 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1035 uint64_t ras_mask;
1036
1037 if (!ras)
1038 return -EINVAL;
1039 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1040
1041 return copy_to_user(out, &ras_mask,
1042 min_t(u64, size, sizeof(ras_mask))) ?
1043 -EFAULT : 0;
1044 }
1045 case AMDGPU_INFO_VIDEO_CAPS: {
1046 const struct amdgpu_video_codecs *codecs;
1047 struct drm_amdgpu_info_video_caps *caps;
1048 int r;
1049
1050 switch (info->video_cap.type) {
1051 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1052 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1053 if (r)
1054 return -EINVAL;
1055 break;
1056 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1057 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1058 if (r)
1059 return -EINVAL;
1060 break;
1061 default:
1062 DRM_DEBUG_KMS("Invalid request %d\n",
1063 info->video_cap.type);
1064 return -EINVAL;
1065 }
1066
1067 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1068 if (!caps)
1069 return -ENOMEM;
1070
1071 for (i = 0; i < codecs->codec_count; i++) {
1072 int idx = codecs->codec_array[i].codec_type;
1073
1074 switch (idx) {
1075 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1076 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1077 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1078 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1079 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1080 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1081 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1082 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1083 caps->codec_info[idx].valid = 1;
1084 caps->codec_info[idx].max_width =
1085 codecs->codec_array[i].max_width;
1086 caps->codec_info[idx].max_height =
1087 codecs->codec_array[i].max_height;
1088 caps->codec_info[idx].max_pixels_per_frame =
1089 codecs->codec_array[i].max_pixels_per_frame;
1090 caps->codec_info[idx].max_level =
1091 codecs->codec_array[i].max_level;
1092 break;
1093 default:
1094 break;
1095 }
1096 }
1097 r = copy_to_user(out, caps,
1098 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1099 kfree(caps);
1100 return r;
1101 }
1102 default:
1103 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1104 return -EINVAL;
1105 }
1106 return 0;
1107 }
1108
1109
1110 /*
1111 * Outdated mess for old drm with Xorg being in charge (void function now).
1112 */
1113 /**
1114 * amdgpu_driver_lastclose_kms - drm callback for last close
1115 *
1116 * @dev: drm dev pointer
1117 *
1118 * Switch vga_switcheroo state after last close (all asics).
1119 */
amdgpu_driver_lastclose_kms(struct drm_device * dev)1120 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1121 {
1122 drm_fb_helper_lastclose(dev);
1123 vga_switcheroo_process_delayed_switch();
1124 }
1125
1126 /**
1127 * amdgpu_driver_open_kms - drm callback for open
1128 *
1129 * @dev: drm dev pointer
1130 * @file_priv: drm file
1131 *
1132 * On device open, init vm on cayman+ (all asics).
1133 * Returns 0 on success, error on failure.
1134 */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)1135 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1136 {
1137 struct amdgpu_device *adev = drm_to_adev(dev);
1138 struct amdgpu_fpriv *fpriv;
1139 int r, pasid;
1140
1141 /* Ensure IB tests are run on ring */
1142 flush_delayed_work(&adev->delayed_init_work);
1143
1144
1145 if (amdgpu_ras_intr_triggered()) {
1146 DRM_ERROR("RAS Intr triggered, device disabled!!");
1147 return -EHWPOISON;
1148 }
1149
1150 file_priv->driver_priv = NULL;
1151
1152 r = pm_runtime_get_sync(dev->dev);
1153 if (r < 0)
1154 goto pm_put;
1155
1156 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1157 if (unlikely(!fpriv)) {
1158 r = -ENOMEM;
1159 goto out_suspend;
1160 }
1161
1162 pasid = amdgpu_pasid_alloc(16);
1163 if (pasid < 0) {
1164 dev_warn(adev->dev, "No more PASIDs available!");
1165 pasid = 0;
1166 }
1167
1168 r = amdgpu_vm_init(adev, &fpriv->vm);
1169 if (r)
1170 goto error_pasid;
1171
1172 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1173 if (r)
1174 goto error_vm;
1175
1176 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1177 if (!fpriv->prt_va) {
1178 r = -ENOMEM;
1179 goto error_vm;
1180 }
1181
1182 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1183 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1184
1185 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1186 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1187 if (r)
1188 goto error_vm;
1189 }
1190
1191 mutex_init(&fpriv->bo_list_lock);
1192 idr_init_base(&fpriv->bo_list_handles, 1);
1193
1194 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1195
1196 file_priv->driver_priv = fpriv;
1197 goto out_suspend;
1198
1199 error_vm:
1200 amdgpu_vm_fini(adev, &fpriv->vm);
1201
1202 error_pasid:
1203 if (pasid) {
1204 amdgpu_pasid_free(pasid);
1205 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1206 }
1207
1208 kfree(fpriv);
1209
1210 out_suspend:
1211 pm_runtime_mark_last_busy(dev->dev);
1212 pm_put:
1213 pm_runtime_put_autosuspend(dev->dev);
1214
1215 return r;
1216 }
1217
1218 /**
1219 * amdgpu_driver_postclose_kms - drm callback for post close
1220 *
1221 * @dev: drm dev pointer
1222 * @file_priv: drm file
1223 *
1224 * On device post close, tear down vm on cayman+ (all asics).
1225 */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)1226 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1227 struct drm_file *file_priv)
1228 {
1229 struct amdgpu_device *adev = drm_to_adev(dev);
1230 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1231 struct amdgpu_bo_list *list;
1232 struct amdgpu_bo *pd;
1233 u32 pasid;
1234 int handle;
1235
1236 if (!fpriv)
1237 return;
1238
1239 pm_runtime_get_sync(dev->dev);
1240
1241 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1242 amdgpu_uvd_free_handles(adev, file_priv);
1243 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1244 amdgpu_vce_free_handles(adev, file_priv);
1245
1246 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1247 /* TODO: how to handle reserve failure */
1248 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1249 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1250 fpriv->csa_va = NULL;
1251 amdgpu_bo_unreserve(adev->virt.csa_obj);
1252 }
1253
1254 pasid = fpriv->vm.pasid;
1255 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1256 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1257 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1258 amdgpu_bo_unreserve(pd);
1259 }
1260
1261 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1262 amdgpu_vm_fini(adev, &fpriv->vm);
1263
1264 if (pasid)
1265 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1266 amdgpu_bo_unref(&pd);
1267
1268 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1269 amdgpu_bo_list_put(list);
1270
1271 idr_destroy(&fpriv->bo_list_handles);
1272 mutex_destroy(&fpriv->bo_list_lock);
1273
1274 kfree(fpriv);
1275 file_priv->driver_priv = NULL;
1276
1277 pm_runtime_mark_last_busy(dev->dev);
1278 pm_runtime_put_autosuspend(dev->dev);
1279 }
1280
1281
amdgpu_driver_release_kms(struct drm_device * dev)1282 void amdgpu_driver_release_kms(struct drm_device *dev)
1283 {
1284 struct amdgpu_device *adev = drm_to_adev(dev);
1285
1286 amdgpu_device_fini_sw(adev);
1287 pci_set_drvdata(adev->pdev, NULL);
1288 }
1289
1290 /*
1291 * VBlank related functions.
1292 */
1293 /**
1294 * amdgpu_get_vblank_counter_kms - get frame count
1295 *
1296 * @crtc: crtc to get the frame count from
1297 *
1298 * Gets the frame count on the requested crtc (all asics).
1299 * Returns frame count on success, -EINVAL on failure.
1300 */
amdgpu_get_vblank_counter_kms(struct drm_crtc * crtc)1301 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1302 {
1303 struct drm_device *dev = crtc->dev;
1304 unsigned int pipe = crtc->index;
1305 struct amdgpu_device *adev = drm_to_adev(dev);
1306 int vpos, hpos, stat;
1307 u32 count;
1308
1309 if (pipe >= adev->mode_info.num_crtc) {
1310 DRM_ERROR("Invalid crtc %u\n", pipe);
1311 return -EINVAL;
1312 }
1313
1314 /* The hw increments its frame counter at start of vsync, not at start
1315 * of vblank, as is required by DRM core vblank counter handling.
1316 * Cook the hw count here to make it appear to the caller as if it
1317 * incremented at start of vblank. We measure distance to start of
1318 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1319 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1320 * result by 1 to give the proper appearance to caller.
1321 */
1322 if (adev->mode_info.crtcs[pipe]) {
1323 /* Repeat readout if needed to provide stable result if
1324 * we cross start of vsync during the queries.
1325 */
1326 do {
1327 count = amdgpu_display_vblank_get_counter(adev, pipe);
1328 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1329 * vpos as distance to start of vblank, instead of
1330 * regular vertical scanout pos.
1331 */
1332 stat = amdgpu_display_get_crtc_scanoutpos(
1333 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1334 &vpos, &hpos, NULL, NULL,
1335 &adev->mode_info.crtcs[pipe]->base.hwmode);
1336 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1337
1338 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1339 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1340 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1341 } else {
1342 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1343 pipe, vpos);
1344
1345 /* Bump counter if we are at >= leading edge of vblank,
1346 * but before vsync where vpos would turn negative and
1347 * the hw counter really increments.
1348 */
1349 if (vpos >= 0)
1350 count++;
1351 }
1352 } else {
1353 /* Fallback to use value as is. */
1354 count = amdgpu_display_vblank_get_counter(adev, pipe);
1355 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1356 }
1357
1358 return count;
1359 }
1360
1361 /**
1362 * amdgpu_enable_vblank_kms - enable vblank interrupt
1363 *
1364 * @crtc: crtc to enable vblank interrupt for
1365 *
1366 * Enable the interrupt on the requested crtc (all asics).
1367 * Returns 0 on success, -EINVAL on failure.
1368 */
amdgpu_enable_vblank_kms(struct drm_crtc * crtc)1369 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1370 {
1371 struct drm_device *dev = crtc->dev;
1372 unsigned int pipe = crtc->index;
1373 struct amdgpu_device *adev = drm_to_adev(dev);
1374 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1375
1376 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1377 }
1378
1379 /**
1380 * amdgpu_disable_vblank_kms - disable vblank interrupt
1381 *
1382 * @crtc: crtc to disable vblank interrupt for
1383 *
1384 * Disable the interrupt on the requested crtc (all asics).
1385 */
amdgpu_disable_vblank_kms(struct drm_crtc * crtc)1386 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1387 {
1388 struct drm_device *dev = crtc->dev;
1389 unsigned int pipe = crtc->index;
1390 struct amdgpu_device *adev = drm_to_adev(dev);
1391 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1392
1393 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1394 }
1395
1396 /*
1397 * Debugfs info
1398 */
1399 #if defined(CONFIG_DEBUG_FS)
1400
amdgpu_debugfs_firmware_info_show(struct seq_file * m,void * unused)1401 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1402 {
1403 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1404 struct drm_amdgpu_info_firmware fw_info;
1405 struct drm_amdgpu_query_fw query_fw;
1406 struct atom_context *ctx = adev->mode_info.atom_context;
1407 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1408 int ret, i;
1409
1410 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1411 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1412 TA_FW_NAME(XGMI),
1413 TA_FW_NAME(RAS),
1414 TA_FW_NAME(HDCP),
1415 TA_FW_NAME(DTM),
1416 TA_FW_NAME(RAP),
1417 TA_FW_NAME(SECUREDISPLAY),
1418 #undef TA_FW_NAME
1419 };
1420
1421 /* VCE */
1422 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1423 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1424 if (ret)
1425 return ret;
1426 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1427 fw_info.feature, fw_info.ver);
1428
1429 /* UVD */
1430 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1431 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1432 if (ret)
1433 return ret;
1434 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1435 fw_info.feature, fw_info.ver);
1436
1437 /* GMC */
1438 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1439 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1440 if (ret)
1441 return ret;
1442 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1443 fw_info.feature, fw_info.ver);
1444
1445 /* ME */
1446 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1447 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1448 if (ret)
1449 return ret;
1450 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1451 fw_info.feature, fw_info.ver);
1452
1453 /* PFP */
1454 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1455 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1456 if (ret)
1457 return ret;
1458 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1459 fw_info.feature, fw_info.ver);
1460
1461 /* CE */
1462 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1463 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1464 if (ret)
1465 return ret;
1466 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1467 fw_info.feature, fw_info.ver);
1468
1469 /* RLC */
1470 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1471 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1472 if (ret)
1473 return ret;
1474 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1475 fw_info.feature, fw_info.ver);
1476
1477 /* RLC SAVE RESTORE LIST CNTL */
1478 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1479 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1480 if (ret)
1481 return ret;
1482 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1483 fw_info.feature, fw_info.ver);
1484
1485 /* RLC SAVE RESTORE LIST GPM MEM */
1486 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1487 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1488 if (ret)
1489 return ret;
1490 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1491 fw_info.feature, fw_info.ver);
1492
1493 /* RLC SAVE RESTORE LIST SRM MEM */
1494 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1495 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1496 if (ret)
1497 return ret;
1498 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1499 fw_info.feature, fw_info.ver);
1500
1501 /* RLCP */
1502 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1503 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504 if (ret)
1505 return ret;
1506 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1507 fw_info.feature, fw_info.ver);
1508
1509 /* RLCV */
1510 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1511 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512 if (ret)
1513 return ret;
1514 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1515 fw_info.feature, fw_info.ver);
1516
1517 /* MEC */
1518 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1519 query_fw.index = 0;
1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1521 if (ret)
1522 return ret;
1523 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1524 fw_info.feature, fw_info.ver);
1525
1526 /* MEC2 */
1527 if (adev->gfx.mec2_fw) {
1528 query_fw.index = 1;
1529 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1530 if (ret)
1531 return ret;
1532 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1533 fw_info.feature, fw_info.ver);
1534 }
1535
1536 /* IMU */
1537 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1538 query_fw.index = 0;
1539 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1540 if (ret)
1541 return ret;
1542 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1543 fw_info.feature, fw_info.ver);
1544
1545 /* PSP SOS */
1546 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1547 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1548 if (ret)
1549 return ret;
1550 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1551 fw_info.feature, fw_info.ver);
1552
1553
1554 /* PSP ASD */
1555 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1556 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1557 if (ret)
1558 return ret;
1559 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1560 fw_info.feature, fw_info.ver);
1561
1562 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1563 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1564 query_fw.index = i;
1565 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1566 if (ret)
1567 continue;
1568
1569 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1570 ta_fw_name[i], fw_info.feature, fw_info.ver);
1571 }
1572
1573 /* SMC */
1574 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1575 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1576 if (ret)
1577 return ret;
1578 smu_program = (fw_info.ver >> 24) & 0xff;
1579 smu_major = (fw_info.ver >> 16) & 0xff;
1580 smu_minor = (fw_info.ver >> 8) & 0xff;
1581 smu_debug = (fw_info.ver >> 0) & 0xff;
1582 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1583 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1584
1585 /* SDMA */
1586 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1587 for (i = 0; i < adev->sdma.num_instances; i++) {
1588 query_fw.index = i;
1589 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1590 if (ret)
1591 return ret;
1592 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1593 i, fw_info.feature, fw_info.ver);
1594 }
1595
1596 /* VCN */
1597 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1598 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1599 if (ret)
1600 return ret;
1601 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1602 fw_info.feature, fw_info.ver);
1603
1604 /* DMCU */
1605 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1606 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1607 if (ret)
1608 return ret;
1609 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1610 fw_info.feature, fw_info.ver);
1611
1612 /* DMCUB */
1613 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1614 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1615 if (ret)
1616 return ret;
1617 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1618 fw_info.feature, fw_info.ver);
1619
1620 /* TOC */
1621 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1622 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1623 if (ret)
1624 return ret;
1625 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1626 fw_info.feature, fw_info.ver);
1627
1628 /* CAP */
1629 if (adev->psp.cap_fw) {
1630 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1631 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1632 if (ret)
1633 return ret;
1634 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1635 fw_info.feature, fw_info.ver);
1636 }
1637
1638 /* MES_KIQ */
1639 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1640 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1641 if (ret)
1642 return ret;
1643 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1644 fw_info.feature, fw_info.ver);
1645
1646 /* MES */
1647 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1648 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1649 if (ret)
1650 return ret;
1651 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1652 fw_info.feature, fw_info.ver);
1653
1654 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1655
1656 return 0;
1657 }
1658
1659 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1660
1661 #endif
1662
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1663 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1664 {
1665 #if defined(CONFIG_DEBUG_FS)
1666 struct drm_minor *minor = adev_to_drm(adev)->primary;
1667 struct dentry *root = minor->debugfs_root;
1668
1669 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1670 adev, &amdgpu_debugfs_firmware_info_fops);
1671
1672 #endif
1673 }
1674