1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19
20 unsigned int ath11k_debug_mask;
21 EXPORT_SYMBOL(ath11k_debug_mask);
22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
23 MODULE_PARM_DESC(debug_mask, "Debugging mask");
24
25 static unsigned int ath11k_crypto_mode;
26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
28
29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
32 MODULE_PARM_DESC(frame_mode,
33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
34
35 static const struct ath11k_hw_params ath11k_hw_params[] = {
36 {
37 .hw_rev = ATH11K_HW_IPQ8074,
38 .name = "ipq8074 hw2.0",
39 .fw = {
40 .dir = "IPQ8074/hw2.0",
41 .board_size = 256 * 1024,
42 .cal_offset = 128 * 1024,
43 },
44 .max_radios = 3,
45 .bdf_addr = 0x4B0C0000,
46 .hw_ops = &ipq8074_ops,
47 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
48 .internal_sleep_clock = false,
49 .regs = &ipq8074_regs,
50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
51 .host_ce_config = ath11k_host_ce_config_ipq8074,
52 .ce_count = 12,
53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
54 .target_ce_count = 11,
55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
56 .svc_to_ce_map_len = 21,
57 .single_pdev_only = false,
58 .rxdma1_enable = true,
59 .num_rxmda_per_pdev = 1,
60 .rx_mac_buf_ring = false,
61 .vdev_start_delay = false,
62 .htt_peer_map_v2 = true,
63
64 .spectral = {
65 .fft_sz = 2,
66 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
67 * so added pad size as 2 bytes to compensate the BIN size
68 */
69 .fft_pad_sz = 2,
70 .summary_pad_sz = 0,
71 .fft_hdr_len = 16,
72 .max_fft_bins = 512,
73 .fragment_160mhz = true,
74 },
75
76 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
77 BIT(NL80211_IFTYPE_AP) |
78 BIT(NL80211_IFTYPE_MESH_POINT),
79 .supports_monitor = true,
80 .full_monitor_mode = false,
81 .supports_shadow_regs = false,
82 .idle_ps = false,
83 .supports_sta_ps = false,
84 .cold_boot_calib = true,
85 .cbcal_restart_fw = true,
86 .fw_mem_mode = 0,
87 .num_vdevs = 16 + 1,
88 .num_peers = 512,
89 .supports_suspend = false,
90 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
91 .supports_regdb = false,
92 .fix_l1ss = true,
93 .credit_flow = false,
94 .max_tx_ring = DP_TCL_NUM_RING_MAX,
95 .hal_params = &ath11k_hw_hal_params_ipq8074,
96 .supports_dynamic_smps_6ghz = false,
97 .alloc_cacheable_memory = true,
98 .supports_rssi_stats = false,
99 .fw_wmi_diag_event = false,
100 .current_cc_support = false,
101 .dbr_debug_support = true,
102 .global_reset = false,
103 .bios_sar_capa = NULL,
104 .m3_fw_support = false,
105 .fixed_bdf_addr = true,
106 .fixed_mem_region = true,
107 .static_window_map = false,
108 .hybrid_bus_type = false,
109 .fixed_fw_mem = false,
110 .support_off_channel_tx = false,
111 .supports_multi_bssid = false,
112
113 .sram_dump = {},
114
115 .tcl_ring_retry = true,
116 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
117 .smp2p_wow_exit = false,
118 },
119 {
120 .hw_rev = ATH11K_HW_IPQ6018_HW10,
121 .name = "ipq6018 hw1.0",
122 .fw = {
123 .dir = "IPQ6018/hw1.0",
124 .board_size = 256 * 1024,
125 .cal_offset = 128 * 1024,
126 },
127 .max_radios = 2,
128 .bdf_addr = 0x4ABC0000,
129 .hw_ops = &ipq6018_ops,
130 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
131 .internal_sleep_clock = false,
132 .regs = &ipq8074_regs,
133 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
134 .host_ce_config = ath11k_host_ce_config_ipq8074,
135 .ce_count = 12,
136 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
137 .target_ce_count = 11,
138 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
139 .svc_to_ce_map_len = 19,
140 .single_pdev_only = false,
141 .rxdma1_enable = true,
142 .num_rxmda_per_pdev = 1,
143 .rx_mac_buf_ring = false,
144 .vdev_start_delay = false,
145 .htt_peer_map_v2 = true,
146
147 .spectral = {
148 .fft_sz = 4,
149 .fft_pad_sz = 0,
150 .summary_pad_sz = 0,
151 .fft_hdr_len = 16,
152 .max_fft_bins = 512,
153 .fragment_160mhz = true,
154 },
155
156 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
157 BIT(NL80211_IFTYPE_AP) |
158 BIT(NL80211_IFTYPE_MESH_POINT),
159 .supports_monitor = true,
160 .full_monitor_mode = false,
161 .supports_shadow_regs = false,
162 .idle_ps = false,
163 .supports_sta_ps = false,
164 .cold_boot_calib = true,
165 .cbcal_restart_fw = true,
166 .fw_mem_mode = 0,
167 .num_vdevs = 16 + 1,
168 .num_peers = 512,
169 .supports_suspend = false,
170 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
171 .supports_regdb = false,
172 .fix_l1ss = true,
173 .credit_flow = false,
174 .max_tx_ring = DP_TCL_NUM_RING_MAX,
175 .hal_params = &ath11k_hw_hal_params_ipq8074,
176 .supports_dynamic_smps_6ghz = false,
177 .alloc_cacheable_memory = true,
178 .supports_rssi_stats = false,
179 .fw_wmi_diag_event = false,
180 .current_cc_support = false,
181 .dbr_debug_support = true,
182 .global_reset = false,
183 .bios_sar_capa = NULL,
184 .m3_fw_support = false,
185 .fixed_bdf_addr = true,
186 .fixed_mem_region = true,
187 .static_window_map = false,
188 .hybrid_bus_type = false,
189 .fixed_fw_mem = false,
190 .support_off_channel_tx = false,
191 .supports_multi_bssid = false,
192
193 .sram_dump = {},
194
195 .tcl_ring_retry = true,
196 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
197 .smp2p_wow_exit = false,
198 },
199 {
200 .name = "qca6390 hw2.0",
201 .hw_rev = ATH11K_HW_QCA6390_HW20,
202 .fw = {
203 .dir = "QCA6390/hw2.0",
204 .board_size = 256 * 1024,
205 .cal_offset = 128 * 1024,
206 },
207 .max_radios = 3,
208 .bdf_addr = 0x4B0C0000,
209 .hw_ops = &qca6390_ops,
210 .ring_mask = &ath11k_hw_ring_mask_qca6390,
211 .internal_sleep_clock = true,
212 .regs = &qca6390_regs,
213 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
214 .host_ce_config = ath11k_host_ce_config_qca6390,
215 .ce_count = 9,
216 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
217 .target_ce_count = 9,
218 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
219 .svc_to_ce_map_len = 14,
220 .single_pdev_only = true,
221 .rxdma1_enable = false,
222 .num_rxmda_per_pdev = 2,
223 .rx_mac_buf_ring = true,
224 .vdev_start_delay = true,
225 .htt_peer_map_v2 = false,
226
227 .spectral = {
228 .fft_sz = 0,
229 .fft_pad_sz = 0,
230 .summary_pad_sz = 0,
231 .fft_hdr_len = 0,
232 .max_fft_bins = 0,
233 .fragment_160mhz = false,
234 },
235
236 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
237 BIT(NL80211_IFTYPE_AP),
238 .supports_monitor = false,
239 .full_monitor_mode = false,
240 .supports_shadow_regs = true,
241 .idle_ps = true,
242 .supports_sta_ps = true,
243 .cold_boot_calib = false,
244 .cbcal_restart_fw = false,
245 .fw_mem_mode = 0,
246 .num_vdevs = 16 + 1,
247 .num_peers = 512,
248 .supports_suspend = true,
249 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
250 .supports_regdb = false,
251 .fix_l1ss = true,
252 .credit_flow = true,
253 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
254 .hal_params = &ath11k_hw_hal_params_qca6390,
255 .supports_dynamic_smps_6ghz = false,
256 .alloc_cacheable_memory = false,
257 .supports_rssi_stats = true,
258 .fw_wmi_diag_event = true,
259 .current_cc_support = true,
260 .dbr_debug_support = false,
261 .global_reset = true,
262 .bios_sar_capa = NULL,
263 .m3_fw_support = true,
264 .fixed_bdf_addr = false,
265 .fixed_mem_region = false,
266 .static_window_map = false,
267 .hybrid_bus_type = false,
268 .fixed_fw_mem = false,
269 .support_off_channel_tx = true,
270 .supports_multi_bssid = true,
271
272 .sram_dump = {
273 .start = 0x01400000,
274 .end = 0x0171ffff,
275 },
276
277 .tcl_ring_retry = true,
278 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
279 .smp2p_wow_exit = false,
280 },
281 {
282 .name = "qcn9074 hw1.0",
283 .hw_rev = ATH11K_HW_QCN9074_HW10,
284 .fw = {
285 .dir = "QCN9074/hw1.0",
286 .board_size = 256 * 1024,
287 .cal_offset = 128 * 1024,
288 },
289 .max_radios = 1,
290 .single_pdev_only = false,
291 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
292 .hw_ops = &qcn9074_ops,
293 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
294 .internal_sleep_clock = false,
295 .regs = &qcn9074_regs,
296 .host_ce_config = ath11k_host_ce_config_qcn9074,
297 .ce_count = 6,
298 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
299 .target_ce_count = 9,
300 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
301 .svc_to_ce_map_len = 18,
302 .rxdma1_enable = true,
303 .num_rxmda_per_pdev = 1,
304 .rx_mac_buf_ring = false,
305 .vdev_start_delay = false,
306 .htt_peer_map_v2 = true,
307
308 .spectral = {
309 .fft_sz = 2,
310 .fft_pad_sz = 0,
311 .summary_pad_sz = 16,
312 .fft_hdr_len = 24,
313 .max_fft_bins = 1024,
314 .fragment_160mhz = false,
315 },
316
317 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
318 BIT(NL80211_IFTYPE_AP) |
319 BIT(NL80211_IFTYPE_MESH_POINT),
320 .supports_monitor = true,
321 .full_monitor_mode = true,
322 .supports_shadow_regs = false,
323 .idle_ps = false,
324 .supports_sta_ps = false,
325 .cold_boot_calib = false,
326 .cbcal_restart_fw = false,
327 .fw_mem_mode = 2,
328 .num_vdevs = 8,
329 .num_peers = 128,
330 .supports_suspend = false,
331 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
332 .supports_regdb = false,
333 .fix_l1ss = true,
334 .credit_flow = false,
335 .max_tx_ring = DP_TCL_NUM_RING_MAX,
336 .hal_params = &ath11k_hw_hal_params_ipq8074,
337 .supports_dynamic_smps_6ghz = true,
338 .alloc_cacheable_memory = true,
339 .supports_rssi_stats = false,
340 .fw_wmi_diag_event = false,
341 .current_cc_support = false,
342 .dbr_debug_support = true,
343 .global_reset = false,
344 .bios_sar_capa = NULL,
345 .m3_fw_support = true,
346 .fixed_bdf_addr = false,
347 .fixed_mem_region = false,
348 .static_window_map = true,
349 .hybrid_bus_type = false,
350 .fixed_fw_mem = false,
351 .support_off_channel_tx = false,
352 .supports_multi_bssid = false,
353
354 .sram_dump = {},
355
356 .tcl_ring_retry = true,
357 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
358 .smp2p_wow_exit = false,
359 },
360 {
361 .name = "wcn6855 hw2.0",
362 .hw_rev = ATH11K_HW_WCN6855_HW20,
363 .fw = {
364 .dir = "WCN6855/hw2.0",
365 .board_size = 256 * 1024,
366 .cal_offset = 128 * 1024,
367 },
368 .max_radios = 3,
369 .bdf_addr = 0x4B0C0000,
370 .hw_ops = &wcn6855_ops,
371 .ring_mask = &ath11k_hw_ring_mask_qca6390,
372 .internal_sleep_clock = true,
373 .regs = &wcn6855_regs,
374 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
375 .host_ce_config = ath11k_host_ce_config_qca6390,
376 .ce_count = 9,
377 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
378 .target_ce_count = 9,
379 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
380 .svc_to_ce_map_len = 14,
381 .single_pdev_only = true,
382 .rxdma1_enable = false,
383 .num_rxmda_per_pdev = 2,
384 .rx_mac_buf_ring = true,
385 .vdev_start_delay = true,
386 .htt_peer_map_v2 = false,
387
388 .spectral = {
389 .fft_sz = 0,
390 .fft_pad_sz = 0,
391 .summary_pad_sz = 0,
392 .fft_hdr_len = 0,
393 .max_fft_bins = 0,
394 .fragment_160mhz = false,
395 },
396
397 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
398 BIT(NL80211_IFTYPE_AP),
399 .supports_monitor = false,
400 .full_monitor_mode = false,
401 .supports_shadow_regs = true,
402 .idle_ps = true,
403 .supports_sta_ps = true,
404 .cold_boot_calib = false,
405 .cbcal_restart_fw = false,
406 .fw_mem_mode = 0,
407 .num_vdevs = 16 + 1,
408 .num_peers = 512,
409 .supports_suspend = true,
410 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
411 .supports_regdb = true,
412 .fix_l1ss = false,
413 .credit_flow = true,
414 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
415 .hal_params = &ath11k_hw_hal_params_qca6390,
416 .supports_dynamic_smps_6ghz = false,
417 .alloc_cacheable_memory = false,
418 .supports_rssi_stats = true,
419 .fw_wmi_diag_event = true,
420 .current_cc_support = true,
421 .dbr_debug_support = false,
422 .global_reset = true,
423 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
424 .m3_fw_support = true,
425 .fixed_bdf_addr = false,
426 .fixed_mem_region = false,
427 .static_window_map = false,
428 .hybrid_bus_type = false,
429 .fixed_fw_mem = false,
430 .support_off_channel_tx = true,
431 .supports_multi_bssid = true,
432
433 .sram_dump = {
434 .start = 0x01400000,
435 .end = 0x0177ffff,
436 },
437
438 .tcl_ring_retry = true,
439 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
440 .smp2p_wow_exit = false,
441 },
442 {
443 .name = "wcn6855 hw2.1",
444 .hw_rev = ATH11K_HW_WCN6855_HW21,
445 .fw = {
446 .dir = "WCN6855/hw2.1",
447 .board_size = 256 * 1024,
448 .cal_offset = 128 * 1024,
449 },
450 .max_radios = 3,
451 .bdf_addr = 0x4B0C0000,
452 .hw_ops = &wcn6855_ops,
453 .ring_mask = &ath11k_hw_ring_mask_qca6390,
454 .internal_sleep_clock = true,
455 .regs = &wcn6855_regs,
456 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
457 .host_ce_config = ath11k_host_ce_config_qca6390,
458 .ce_count = 9,
459 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
460 .target_ce_count = 9,
461 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
462 .svc_to_ce_map_len = 14,
463 .single_pdev_only = true,
464 .rxdma1_enable = false,
465 .num_rxmda_per_pdev = 2,
466 .rx_mac_buf_ring = true,
467 .vdev_start_delay = true,
468 .htt_peer_map_v2 = false,
469
470 .spectral = {
471 .fft_sz = 0,
472 .fft_pad_sz = 0,
473 .summary_pad_sz = 0,
474 .fft_hdr_len = 0,
475 .max_fft_bins = 0,
476 .fragment_160mhz = false,
477 },
478
479 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
480 BIT(NL80211_IFTYPE_AP),
481 .supports_monitor = false,
482 .supports_shadow_regs = true,
483 .idle_ps = true,
484 .supports_sta_ps = true,
485 .cold_boot_calib = false,
486 .cbcal_restart_fw = false,
487 .fw_mem_mode = 0,
488 .num_vdevs = 16 + 1,
489 .num_peers = 512,
490 .supports_suspend = true,
491 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
492 .supports_regdb = true,
493 .fix_l1ss = false,
494 .credit_flow = true,
495 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
496 .hal_params = &ath11k_hw_hal_params_qca6390,
497 .supports_dynamic_smps_6ghz = false,
498 .alloc_cacheable_memory = false,
499 .supports_rssi_stats = true,
500 .fw_wmi_diag_event = true,
501 .current_cc_support = true,
502 .dbr_debug_support = false,
503 .global_reset = true,
504 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
505 .m3_fw_support = true,
506 .fixed_bdf_addr = false,
507 .fixed_mem_region = false,
508 .static_window_map = false,
509 .hybrid_bus_type = false,
510 .fixed_fw_mem = false,
511 .support_off_channel_tx = true,
512 .supports_multi_bssid = true,
513
514 .sram_dump = {
515 .start = 0x01400000,
516 .end = 0x0177ffff,
517 },
518
519 .tcl_ring_retry = true,
520 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
521 .smp2p_wow_exit = false,
522 },
523 {
524 .name = "wcn6750 hw1.0",
525 .hw_rev = ATH11K_HW_WCN6750_HW10,
526 .fw = {
527 .dir = "WCN6750/hw1.0",
528 .board_size = 256 * 1024,
529 .cal_offset = 128 * 1024,
530 },
531 .max_radios = 1,
532 .bdf_addr = 0x4B0C0000,
533 .hw_ops = &wcn6750_ops,
534 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
535 .internal_sleep_clock = false,
536 .regs = &wcn6750_regs,
537 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
538 .host_ce_config = ath11k_host_ce_config_qca6390,
539 .ce_count = 9,
540 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
541 .target_ce_count = 9,
542 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
543 .svc_to_ce_map_len = 14,
544 .single_pdev_only = true,
545 .rxdma1_enable = false,
546 .num_rxmda_per_pdev = 1,
547 .rx_mac_buf_ring = true,
548 .vdev_start_delay = true,
549 .htt_peer_map_v2 = false,
550
551 .spectral = {
552 .fft_sz = 0,
553 .fft_pad_sz = 0,
554 .summary_pad_sz = 0,
555 .fft_hdr_len = 0,
556 .max_fft_bins = 0,
557 .fragment_160mhz = false,
558 },
559
560 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
561 BIT(NL80211_IFTYPE_AP),
562 .supports_monitor = false,
563 .supports_shadow_regs = true,
564 .idle_ps = true,
565 .supports_sta_ps = true,
566 .cold_boot_calib = true,
567 .cbcal_restart_fw = false,
568 .fw_mem_mode = 0,
569 .num_vdevs = 16 + 1,
570 .num_peers = 512,
571 .supports_suspend = false,
572 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
573 .supports_regdb = true,
574 .fix_l1ss = false,
575 .credit_flow = true,
576 .max_tx_ring = DP_TCL_NUM_RING_MAX,
577 .hal_params = &ath11k_hw_hal_params_wcn6750,
578 .supports_dynamic_smps_6ghz = false,
579 .alloc_cacheable_memory = false,
580 .supports_rssi_stats = true,
581 .fw_wmi_diag_event = false,
582 .current_cc_support = true,
583 .dbr_debug_support = false,
584 .global_reset = false,
585 .bios_sar_capa = NULL,
586 .m3_fw_support = false,
587 .fixed_bdf_addr = false,
588 .fixed_mem_region = false,
589 .static_window_map = true,
590 .hybrid_bus_type = true,
591 .fixed_fw_mem = true,
592 .support_off_channel_tx = true,
593 .supports_multi_bssid = true,
594
595 .sram_dump = {},
596
597 .tcl_ring_retry = false,
598 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
599 .smp2p_wow_exit = true,
600 },
601 };
602
ath11k_core_get_single_pdev(struct ath11k_base * ab)603 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
604 {
605 WARN_ON(!ab->hw_params.single_pdev_only);
606
607 return &ab->pdevs[0];
608 }
609
ath11k_fw_stats_pdevs_free(struct list_head * head)610 void ath11k_fw_stats_pdevs_free(struct list_head *head)
611 {
612 struct ath11k_fw_stats_pdev *i, *tmp;
613
614 list_for_each_entry_safe(i, tmp, head, list) {
615 list_del(&i->list);
616 kfree(i);
617 }
618 }
619
ath11k_fw_stats_vdevs_free(struct list_head * head)620 void ath11k_fw_stats_vdevs_free(struct list_head *head)
621 {
622 struct ath11k_fw_stats_vdev *i, *tmp;
623
624 list_for_each_entry_safe(i, tmp, head, list) {
625 list_del(&i->list);
626 kfree(i);
627 }
628 }
629
ath11k_fw_stats_bcn_free(struct list_head * head)630 void ath11k_fw_stats_bcn_free(struct list_head *head)
631 {
632 struct ath11k_fw_stats_bcn *i, *tmp;
633
634 list_for_each_entry_safe(i, tmp, head, list) {
635 list_del(&i->list);
636 kfree(i);
637 }
638 }
639
ath11k_fw_stats_init(struct ath11k * ar)640 void ath11k_fw_stats_init(struct ath11k *ar)
641 {
642 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
643 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
644 INIT_LIST_HEAD(&ar->fw_stats.bcn);
645
646 init_completion(&ar->fw_stats_complete);
647 }
648
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)649 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
650 {
651 ath11k_fw_stats_pdevs_free(&stats->pdevs);
652 ath11k_fw_stats_vdevs_free(&stats->vdevs);
653 ath11k_fw_stats_bcn_free(&stats->bcn);
654 }
655
ath11k_core_suspend(struct ath11k_base * ab)656 int ath11k_core_suspend(struct ath11k_base *ab)
657 {
658 int ret;
659 struct ath11k_pdev *pdev;
660 struct ath11k *ar;
661
662 if (!ab->hw_params.supports_suspend)
663 return -EOPNOTSUPP;
664
665 /* so far single_pdev_only chips have supports_suspend as true
666 * and only the first pdev is valid.
667 */
668 pdev = ath11k_core_get_single_pdev(ab);
669 ar = pdev->ar;
670 if (!ar || ar->state != ATH11K_STATE_OFF)
671 return 0;
672
673 ret = ath11k_dp_rx_pktlog_stop(ab, true);
674 if (ret) {
675 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
676 ret);
677 return ret;
678 }
679
680 ret = ath11k_mac_wait_tx_complete(ar);
681 if (ret) {
682 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
683 return ret;
684 }
685
686 ret = ath11k_wow_enable(ab);
687 if (ret) {
688 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
689 return ret;
690 }
691
692 ret = ath11k_dp_rx_pktlog_stop(ab, false);
693 if (ret) {
694 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
695 ret);
696 return ret;
697 }
698
699 ath11k_ce_stop_shadow_timers(ab);
700 ath11k_dp_stop_shadow_timers(ab);
701
702 ath11k_hif_irq_disable(ab);
703 ath11k_hif_ce_irq_disable(ab);
704
705 ret = ath11k_hif_suspend(ab);
706 if (ret) {
707 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
708 return ret;
709 }
710
711 return 0;
712 }
713 EXPORT_SYMBOL(ath11k_core_suspend);
714
ath11k_core_resume(struct ath11k_base * ab)715 int ath11k_core_resume(struct ath11k_base *ab)
716 {
717 int ret;
718 struct ath11k_pdev *pdev;
719 struct ath11k *ar;
720
721 if (!ab->hw_params.supports_suspend)
722 return -EOPNOTSUPP;
723
724 /* so far signle_pdev_only chips have supports_suspend as true
725 * and only the first pdev is valid.
726 */
727 pdev = ath11k_core_get_single_pdev(ab);
728 ar = pdev->ar;
729 if (!ar || ar->state != ATH11K_STATE_OFF)
730 return 0;
731
732 ret = ath11k_hif_resume(ab);
733 if (ret) {
734 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
735 return ret;
736 }
737
738 ath11k_hif_ce_irq_enable(ab);
739 ath11k_hif_irq_enable(ab);
740
741 ret = ath11k_dp_rx_pktlog_start(ab);
742 if (ret) {
743 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
744 ret);
745 return ret;
746 }
747
748 ret = ath11k_wow_wakeup(ab);
749 if (ret) {
750 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
751 return ret;
752 }
753
754 return 0;
755 }
756 EXPORT_SYMBOL(ath11k_core_resume);
757
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)758 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
759 {
760 struct ath11k_base *ab = data;
761 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
762 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
763 ssize_t copied;
764 size_t len;
765 int i;
766
767 if (ab->qmi.target.bdf_ext[0] != '\0')
768 return;
769
770 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
771 return;
772
773 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
774 ath11k_dbg(ab, ATH11K_DBG_BOOT,
775 "wrong smbios bdf ext type length (%d).\n",
776 hdr->length);
777 return;
778 }
779
780 spin_lock_bh(&ab->base_lock);
781
782 switch (smbios->country_code_flag) {
783 case ATH11K_SMBIOS_CC_ISO:
784 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
785 ab->new_alpha2[1] = smbios->cc_code & 0xff;
786 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n",
787 ab->new_alpha2[0], ab->new_alpha2[1]);
788 break;
789 case ATH11K_SMBIOS_CC_WW:
790 ab->new_alpha2[0] = '0';
791 ab->new_alpha2[1] = '0';
792 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n");
793 break;
794 default:
795 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n",
796 smbios->country_code_flag);
797 break;
798 }
799
800 spin_unlock_bh(&ab->base_lock);
801
802 if (!smbios->bdf_enabled) {
803 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
804 return;
805 }
806
807 /* Only one string exists (per spec) */
808 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
809 ath11k_dbg(ab, ATH11K_DBG_BOOT,
810 "bdf variant magic does not match.\n");
811 return;
812 }
813
814 len = min_t(size_t,
815 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
816 for (i = 0; i < len; i++) {
817 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
818 ath11k_dbg(ab, ATH11K_DBG_BOOT,
819 "bdf variant name contains non ascii chars.\n");
820 return;
821 }
822 }
823
824 /* Copy extension name without magic prefix */
825 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
826 sizeof(ab->qmi.target.bdf_ext));
827 if (copied < 0) {
828 ath11k_dbg(ab, ATH11K_DBG_BOOT,
829 "bdf variant string is longer than the buffer can accommodate\n");
830 return;
831 }
832
833 ath11k_dbg(ab, ATH11K_DBG_BOOT,
834 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
835 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
836 }
837
ath11k_core_check_smbios(struct ath11k_base * ab)838 int ath11k_core_check_smbios(struct ath11k_base *ab)
839 {
840 ab->qmi.target.bdf_ext[0] = '\0';
841 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
842
843 if (ab->qmi.target.bdf_ext[0] == '\0')
844 return -ENODATA;
845
846 return 0;
847 }
848
ath11k_core_check_dt(struct ath11k_base * ab)849 int ath11k_core_check_dt(struct ath11k_base *ab)
850 {
851 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
852 const char *variant = NULL;
853 struct device_node *node;
854
855 node = ab->dev->of_node;
856 if (!node)
857 return -ENOENT;
858
859 of_property_read_string(node, "qcom,ath11k-calibration-variant",
860 &variant);
861 if (!variant)
862 return -ENODATA;
863
864 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
865 ath11k_dbg(ab, ATH11K_DBG_BOOT,
866 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
867 variant);
868
869 return 0;
870 }
871
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,bool bus_type_mode)872 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
873 size_t name_len, bool with_variant,
874 bool bus_type_mode)
875 {
876 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
877 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
878
879 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
880 scnprintf(variant, sizeof(variant), ",variant=%s",
881 ab->qmi.target.bdf_ext);
882
883 switch (ab->id.bdf_search) {
884 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
885 if (bus_type_mode)
886 scnprintf(name, name_len,
887 "bus=%s",
888 ath11k_bus_str(ab->hif.bus));
889 else
890 scnprintf(name, name_len,
891 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
892 ath11k_bus_str(ab->hif.bus),
893 ab->id.vendor, ab->id.device,
894 ab->id.subsystem_vendor,
895 ab->id.subsystem_device,
896 ab->qmi.target.chip_id,
897 ab->qmi.target.board_id,
898 variant);
899 break;
900 default:
901 scnprintf(name, name_len,
902 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
903 ath11k_bus_str(ab->hif.bus),
904 ab->qmi.target.chip_id,
905 ab->qmi.target.board_id, variant);
906 break;
907 }
908
909 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name);
910
911 return 0;
912 }
913
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)914 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
915 size_t name_len)
916 {
917 return __ath11k_core_create_board_name(ab, name, name_len, true, false);
918 }
919
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)920 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
921 size_t name_len)
922 {
923 return __ath11k_core_create_board_name(ab, name, name_len, false, false);
924 }
925
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)926 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
927 size_t name_len)
928 {
929 return __ath11k_core_create_board_name(ab, name, name_len, false, true);
930 }
931
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)932 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
933 const char *file)
934 {
935 const struct firmware *fw;
936 char path[100];
937 int ret;
938
939 if (file == NULL)
940 return ERR_PTR(-ENOENT);
941
942 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
943
944 ret = firmware_request_nowarn(&fw, path, ab->dev);
945 if (ret)
946 return ERR_PTR(ret);
947
948 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n",
949 path, fw->size);
950
951 return fw;
952 }
953
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)954 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
955 {
956 if (!IS_ERR(bd->fw))
957 release_firmware(bd->fw);
958
959 memset(bd, 0, sizeof(*bd));
960 }
961
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)962 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
963 struct ath11k_board_data *bd,
964 const void *buf, size_t buf_len,
965 const char *boardname,
966 int ie_id,
967 int name_id,
968 int data_id)
969 {
970 const struct ath11k_fw_ie *hdr;
971 bool name_match_found;
972 int ret, board_ie_id;
973 size_t board_ie_len;
974 const void *board_ie_data;
975
976 name_match_found = false;
977
978 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
979 while (buf_len > sizeof(struct ath11k_fw_ie)) {
980 hdr = buf;
981 board_ie_id = le32_to_cpu(hdr->id);
982 board_ie_len = le32_to_cpu(hdr->len);
983 board_ie_data = hdr->data;
984
985 buf_len -= sizeof(*hdr);
986 buf += sizeof(*hdr);
987
988 if (buf_len < ALIGN(board_ie_len, 4)) {
989 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
990 ath11k_bd_ie_type_str(ie_id),
991 buf_len, ALIGN(board_ie_len, 4));
992 ret = -EINVAL;
993 goto out;
994 }
995
996 if (board_ie_id == name_id) {
997 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
998 board_ie_data, board_ie_len);
999
1000 if (board_ie_len != strlen(boardname))
1001 goto next;
1002
1003 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1004 if (ret)
1005 goto next;
1006
1007 name_match_found = true;
1008 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1009 "boot found match %s for name '%s'",
1010 ath11k_bd_ie_type_str(ie_id),
1011 boardname);
1012 } else if (board_ie_id == data_id) {
1013 if (!name_match_found)
1014 /* no match found */
1015 goto next;
1016
1017 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1018 "boot found %s for '%s'",
1019 ath11k_bd_ie_type_str(ie_id),
1020 boardname);
1021
1022 bd->data = board_ie_data;
1023 bd->len = board_ie_len;
1024
1025 ret = 0;
1026 goto out;
1027 } else {
1028 ath11k_warn(ab, "unknown %s id found: %d\n",
1029 ath11k_bd_ie_type_str(ie_id),
1030 board_ie_id);
1031 }
1032 next:
1033 /* jump over the padding */
1034 board_ie_len = ALIGN(board_ie_len, 4);
1035
1036 buf_len -= board_ie_len;
1037 buf += board_ie_len;
1038 }
1039
1040 /* no match found */
1041 ret = -ENOENT;
1042
1043 out:
1044 return ret;
1045 }
1046
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1047 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1048 struct ath11k_board_data *bd,
1049 const char *boardname,
1050 int ie_id_match,
1051 int name_id,
1052 int data_id)
1053 {
1054 size_t len, magic_len;
1055 const u8 *data;
1056 char *filename, filepath[100];
1057 size_t ie_len;
1058 struct ath11k_fw_ie *hdr;
1059 int ret, ie_id;
1060
1061 filename = ATH11K_BOARD_API2_FILE;
1062
1063 if (!bd->fw)
1064 bd->fw = ath11k_core_firmware_request(ab, filename);
1065
1066 if (IS_ERR(bd->fw))
1067 return PTR_ERR(bd->fw);
1068
1069 data = bd->fw->data;
1070 len = bd->fw->size;
1071
1072 ath11k_core_create_firmware_path(ab, filename,
1073 filepath, sizeof(filepath));
1074
1075 /* magic has extra null byte padded */
1076 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1077 if (len < magic_len) {
1078 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1079 filepath, len);
1080 ret = -EINVAL;
1081 goto err;
1082 }
1083
1084 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1085 ath11k_err(ab, "found invalid board magic\n");
1086 ret = -EINVAL;
1087 goto err;
1088 }
1089
1090 /* magic is padded to 4 bytes */
1091 magic_len = ALIGN(magic_len, 4);
1092 if (len < magic_len) {
1093 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1094 filepath, len);
1095 ret = -EINVAL;
1096 goto err;
1097 }
1098
1099 data += magic_len;
1100 len -= magic_len;
1101
1102 while (len > sizeof(struct ath11k_fw_ie)) {
1103 hdr = (struct ath11k_fw_ie *)data;
1104 ie_id = le32_to_cpu(hdr->id);
1105 ie_len = le32_to_cpu(hdr->len);
1106
1107 len -= sizeof(*hdr);
1108 data = hdr->data;
1109
1110 if (len < ALIGN(ie_len, 4)) {
1111 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1112 ie_id, ie_len, len);
1113 ret = -EINVAL;
1114 goto err;
1115 }
1116
1117 if (ie_id == ie_id_match) {
1118 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1119 ie_len,
1120 boardname,
1121 ie_id_match,
1122 name_id,
1123 data_id);
1124 if (ret == -ENOENT)
1125 /* no match found, continue */
1126 goto next;
1127 else if (ret)
1128 /* there was an error, bail out */
1129 goto err;
1130 /* either found or error, so stop searching */
1131 goto out;
1132 }
1133 next:
1134 /* jump over the padding */
1135 ie_len = ALIGN(ie_len, 4);
1136
1137 len -= ie_len;
1138 data += ie_len;
1139 }
1140
1141 out:
1142 if (!bd->data || !bd->len) {
1143 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1144 "failed to fetch %s for %s from %s\n",
1145 ath11k_bd_ie_type_str(ie_id_match),
1146 boardname, filepath);
1147 ret = -ENODATA;
1148 goto err;
1149 }
1150
1151 return 0;
1152
1153 err:
1154 ath11k_core_free_bdf(ab, bd);
1155 return ret;
1156 }
1157
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1158 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1159 struct ath11k_board_data *bd,
1160 const char *name)
1161 {
1162 bd->fw = ath11k_core_firmware_request(ab, name);
1163
1164 if (IS_ERR(bd->fw))
1165 return PTR_ERR(bd->fw);
1166
1167 bd->data = bd->fw->data;
1168 bd->len = bd->fw->size;
1169
1170 return 0;
1171 }
1172
1173 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1174 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1175 {
1176 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE];
1177 char *filename, filepath[100];
1178 int ret;
1179
1180 filename = ATH11K_BOARD_API2_FILE;
1181
1182 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname));
1183 if (ret) {
1184 ath11k_err(ab, "failed to create board name: %d", ret);
1185 return ret;
1186 }
1187
1188 ab->bd_api = 2;
1189 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1190 ATH11K_BD_IE_BOARD,
1191 ATH11K_BD_IE_BOARD_NAME,
1192 ATH11K_BD_IE_BOARD_DATA);
1193 if (!ret)
1194 goto success;
1195
1196 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1197 sizeof(fallback_boardname));
1198 if (ret) {
1199 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1200 return ret;
1201 }
1202
1203 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1204 ATH11K_BD_IE_BOARD,
1205 ATH11K_BD_IE_BOARD_NAME,
1206 ATH11K_BD_IE_BOARD_DATA);
1207 if (!ret)
1208 goto success;
1209
1210 ab->bd_api = 1;
1211 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1212 if (ret) {
1213 ath11k_core_create_firmware_path(ab, filename,
1214 filepath, sizeof(filepath));
1215 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1216 boardname, filepath);
1217 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1218 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1219 fallback_boardname, filepath);
1220
1221 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1222 ab->hw_params.fw.dir);
1223 return ret;
1224 }
1225
1226 success:
1227 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api);
1228 return 0;
1229 }
1230
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1231 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1232 {
1233 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1234 int ret;
1235
1236 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1237 if (ret) {
1238 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1239 "failed to create board name for regdb: %d", ret);
1240 goto exit;
1241 }
1242
1243 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1244 ATH11K_BD_IE_REGDB,
1245 ATH11K_BD_IE_REGDB_NAME,
1246 ATH11K_BD_IE_REGDB_DATA);
1247 if (!ret)
1248 goto exit;
1249
1250 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1251 BOARD_NAME_SIZE);
1252 if (ret) {
1253 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1254 "failed to create default board name for regdb: %d", ret);
1255 goto exit;
1256 }
1257
1258 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1259 ATH11K_BD_IE_REGDB,
1260 ATH11K_BD_IE_REGDB_NAME,
1261 ATH11K_BD_IE_REGDB_DATA);
1262 if (!ret)
1263 goto exit;
1264
1265 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1266 if (ret)
1267 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1268 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1269
1270 exit:
1271 if (!ret)
1272 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1273
1274 return ret;
1275 }
1276
ath11k_core_stop(struct ath11k_base * ab)1277 static void ath11k_core_stop(struct ath11k_base *ab)
1278 {
1279 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1280 ath11k_qmi_firmware_stop(ab);
1281
1282 ath11k_hif_stop(ab);
1283 ath11k_wmi_detach(ab);
1284 ath11k_dp_pdev_reo_cleanup(ab);
1285
1286 /* De-Init of components as needed */
1287 }
1288
ath11k_core_soc_create(struct ath11k_base * ab)1289 static int ath11k_core_soc_create(struct ath11k_base *ab)
1290 {
1291 int ret;
1292
1293 ret = ath11k_qmi_init_service(ab);
1294 if (ret) {
1295 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1296 return ret;
1297 }
1298
1299 ret = ath11k_debugfs_soc_create(ab);
1300 if (ret) {
1301 ath11k_err(ab, "failed to create ath11k debugfs\n");
1302 goto err_qmi_deinit;
1303 }
1304
1305 ret = ath11k_hif_power_up(ab);
1306 if (ret) {
1307 ath11k_err(ab, "failed to power up :%d\n", ret);
1308 goto err_debugfs_reg;
1309 }
1310
1311 return 0;
1312
1313 err_debugfs_reg:
1314 ath11k_debugfs_soc_destroy(ab);
1315 err_qmi_deinit:
1316 ath11k_qmi_deinit_service(ab);
1317 return ret;
1318 }
1319
ath11k_core_soc_destroy(struct ath11k_base * ab)1320 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1321 {
1322 ath11k_debugfs_soc_destroy(ab);
1323 ath11k_dp_free(ab);
1324 ath11k_reg_free(ab);
1325 ath11k_qmi_deinit_service(ab);
1326 }
1327
ath11k_core_pdev_create(struct ath11k_base * ab)1328 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1329 {
1330 int ret;
1331
1332 ret = ath11k_debugfs_pdev_create(ab);
1333 if (ret) {
1334 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1335 return ret;
1336 }
1337
1338 ret = ath11k_dp_pdev_alloc(ab);
1339 if (ret) {
1340 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1341 goto err_pdev_debug;
1342 }
1343
1344 ret = ath11k_mac_register(ab);
1345 if (ret) {
1346 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1347 goto err_dp_pdev_free;
1348 }
1349
1350 ret = ath11k_thermal_register(ab);
1351 if (ret) {
1352 ath11k_err(ab, "could not register thermal device: %d\n",
1353 ret);
1354 goto err_mac_unregister;
1355 }
1356
1357 ret = ath11k_spectral_init(ab);
1358 if (ret) {
1359 ath11k_err(ab, "failed to init spectral %d\n", ret);
1360 goto err_thermal_unregister;
1361 }
1362
1363 return 0;
1364
1365 err_thermal_unregister:
1366 ath11k_thermal_unregister(ab);
1367 err_mac_unregister:
1368 ath11k_mac_unregister(ab);
1369 err_dp_pdev_free:
1370 ath11k_dp_pdev_free(ab);
1371 err_pdev_debug:
1372 ath11k_debugfs_pdev_destroy(ab);
1373
1374 return ret;
1375 }
1376
ath11k_core_pdev_destroy(struct ath11k_base * ab)1377 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1378 {
1379 ath11k_spectral_deinit(ab);
1380 ath11k_thermal_unregister(ab);
1381 ath11k_mac_unregister(ab);
1382 ath11k_hif_irq_disable(ab);
1383 ath11k_dp_pdev_free(ab);
1384 ath11k_debugfs_pdev_destroy(ab);
1385 }
1386
ath11k_core_start(struct ath11k_base * ab)1387 static int ath11k_core_start(struct ath11k_base *ab)
1388 {
1389 int ret;
1390
1391 ret = ath11k_wmi_attach(ab);
1392 if (ret) {
1393 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1394 return ret;
1395 }
1396
1397 ret = ath11k_htc_init(ab);
1398 if (ret) {
1399 ath11k_err(ab, "failed to init htc: %d\n", ret);
1400 goto err_wmi_detach;
1401 }
1402
1403 ret = ath11k_hif_start(ab);
1404 if (ret) {
1405 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1406 goto err_wmi_detach;
1407 }
1408
1409 ret = ath11k_htc_wait_target(&ab->htc);
1410 if (ret) {
1411 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1412 goto err_hif_stop;
1413 }
1414
1415 ret = ath11k_dp_htt_connect(&ab->dp);
1416 if (ret) {
1417 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1418 goto err_hif_stop;
1419 }
1420
1421 ret = ath11k_wmi_connect(ab);
1422 if (ret) {
1423 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1424 goto err_hif_stop;
1425 }
1426
1427 ret = ath11k_htc_start(&ab->htc);
1428 if (ret) {
1429 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1430 goto err_hif_stop;
1431 }
1432
1433 ret = ath11k_wmi_wait_for_service_ready(ab);
1434 if (ret) {
1435 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1436 ret);
1437 goto err_hif_stop;
1438 }
1439
1440 ret = ath11k_mac_allocate(ab);
1441 if (ret) {
1442 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1443 ret);
1444 goto err_hif_stop;
1445 }
1446
1447 ath11k_dp_pdev_pre_alloc(ab);
1448
1449 ret = ath11k_dp_pdev_reo_setup(ab);
1450 if (ret) {
1451 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1452 goto err_mac_destroy;
1453 }
1454
1455 ret = ath11k_wmi_cmd_init(ab);
1456 if (ret) {
1457 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1458 goto err_reo_cleanup;
1459 }
1460
1461 ret = ath11k_wmi_wait_for_unified_ready(ab);
1462 if (ret) {
1463 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1464 ret);
1465 goto err_reo_cleanup;
1466 }
1467
1468 /* put hardware to DBS mode */
1469 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) {
1470 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1471 if (ret) {
1472 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1473 goto err_hif_stop;
1474 }
1475 }
1476
1477 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1478 if (ret) {
1479 ath11k_err(ab, "failed to send htt version request message: %d\n",
1480 ret);
1481 goto err_reo_cleanup;
1482 }
1483
1484 return 0;
1485
1486 err_reo_cleanup:
1487 ath11k_dp_pdev_reo_cleanup(ab);
1488 err_mac_destroy:
1489 ath11k_mac_destroy(ab);
1490 err_hif_stop:
1491 ath11k_hif_stop(ab);
1492 err_wmi_detach:
1493 ath11k_wmi_detach(ab);
1494
1495 return ret;
1496 }
1497
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1498 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1499 enum ath11k_firmware_mode mode)
1500 {
1501 int ret;
1502
1503 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1504 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1505
1506 ret = ath11k_qmi_firmware_start(ab, mode);
1507 if (ret) {
1508 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1509 return ret;
1510 }
1511
1512 return ret;
1513 }
1514
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1515 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1516 {
1517 int ret;
1518
1519 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL);
1520 if (ret) {
1521 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1522 return ret;
1523 }
1524
1525 ret = ath11k_ce_init_pipes(ab);
1526 if (ret) {
1527 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1528 goto err_firmware_stop;
1529 }
1530
1531 ret = ath11k_dp_alloc(ab);
1532 if (ret) {
1533 ath11k_err(ab, "failed to init DP: %d\n", ret);
1534 goto err_firmware_stop;
1535 }
1536
1537 switch (ath11k_crypto_mode) {
1538 case ATH11K_CRYPT_MODE_SW:
1539 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1540 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1541 break;
1542 case ATH11K_CRYPT_MODE_HW:
1543 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1544 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1545 break;
1546 default:
1547 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1548 return -EINVAL;
1549 }
1550
1551 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1552 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1553
1554 mutex_lock(&ab->core_lock);
1555 ret = ath11k_core_start(ab);
1556 if (ret) {
1557 ath11k_err(ab, "failed to start core: %d\n", ret);
1558 goto err_dp_free;
1559 }
1560
1561 ret = ath11k_core_pdev_create(ab);
1562 if (ret) {
1563 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1564 goto err_core_stop;
1565 }
1566 ath11k_hif_irq_enable(ab);
1567 mutex_unlock(&ab->core_lock);
1568
1569 return 0;
1570
1571 err_core_stop:
1572 ath11k_core_stop(ab);
1573 ath11k_mac_destroy(ab);
1574 err_dp_free:
1575 ath11k_dp_free(ab);
1576 mutex_unlock(&ab->core_lock);
1577 err_firmware_stop:
1578 ath11k_qmi_firmware_stop(ab);
1579
1580 return ret;
1581 }
1582
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)1583 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
1584 {
1585 int ret;
1586
1587 mutex_lock(&ab->core_lock);
1588 ath11k_thermal_unregister(ab);
1589 ath11k_hif_irq_disable(ab);
1590 ath11k_dp_pdev_free(ab);
1591 ath11k_spectral_deinit(ab);
1592 ath11k_hif_stop(ab);
1593 ath11k_wmi_detach(ab);
1594 ath11k_dp_pdev_reo_cleanup(ab);
1595 mutex_unlock(&ab->core_lock);
1596
1597 ath11k_dp_free(ab);
1598 ath11k_hal_srng_deinit(ab);
1599
1600 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
1601
1602 ret = ath11k_hal_srng_init(ab);
1603 if (ret)
1604 return ret;
1605
1606 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
1607
1608 ret = ath11k_core_qmi_firmware_ready(ab);
1609 if (ret)
1610 goto err_hal_srng_deinit;
1611
1612 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
1613
1614 return 0;
1615
1616 err_hal_srng_deinit:
1617 ath11k_hal_srng_deinit(ab);
1618 return ret;
1619 }
1620
ath11k_core_halt(struct ath11k * ar)1621 void ath11k_core_halt(struct ath11k *ar)
1622 {
1623 struct ath11k_base *ab = ar->ab;
1624
1625 lockdep_assert_held(&ar->conf_mutex);
1626
1627 ar->num_created_vdevs = 0;
1628 ar->allocated_vdev_map = 0;
1629
1630 ath11k_mac_scan_finish(ar);
1631 ath11k_mac_peer_cleanup_all(ar);
1632 cancel_delayed_work_sync(&ar->scan.timeout);
1633 cancel_work_sync(&ar->regd_update_work);
1634 cancel_work_sync(&ab->update_11d_work);
1635
1636 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
1637 synchronize_rcu();
1638 INIT_LIST_HEAD(&ar->arvifs);
1639 idr_init(&ar->txmgmt_idr);
1640 }
1641
ath11k_update_11d(struct work_struct * work)1642 static void ath11k_update_11d(struct work_struct *work)
1643 {
1644 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
1645 struct ath11k *ar;
1646 struct ath11k_pdev *pdev;
1647 struct wmi_set_current_country_params set_current_param = {};
1648 int ret, i;
1649
1650 spin_lock_bh(&ab->base_lock);
1651 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
1652 spin_unlock_bh(&ab->base_lock);
1653
1654 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
1655 set_current_param.alpha2[0],
1656 set_current_param.alpha2[1]);
1657
1658 for (i = 0; i < ab->num_radios; i++) {
1659 pdev = &ab->pdevs[i];
1660 ar = pdev->ar;
1661
1662 memcpy(&ar->alpha2, &set_current_param.alpha2, 2);
1663 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
1664 if (ret)
1665 ath11k_warn(ar->ab,
1666 "pdev id %d failed set current country code: %d\n",
1667 i, ret);
1668 }
1669 }
1670
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)1671 static void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
1672 {
1673 struct ath11k *ar;
1674 struct ath11k_pdev *pdev;
1675 int i;
1676
1677 spin_lock_bh(&ab->base_lock);
1678 ab->stats.fw_crash_counter++;
1679 spin_unlock_bh(&ab->base_lock);
1680
1681 for (i = 0; i < ab->num_radios; i++) {
1682 pdev = &ab->pdevs[i];
1683 ar = pdev->ar;
1684 if (!ar || ar->state == ATH11K_STATE_OFF)
1685 continue;
1686
1687 ieee80211_stop_queues(ar->hw);
1688 ath11k_mac_drain_tx(ar);
1689 ar->state_11d = ATH11K_11D_IDLE;
1690 complete(&ar->completed_11d_scan);
1691 complete(&ar->scan.started);
1692 complete_all(&ar->scan.completed);
1693 complete(&ar->scan.on_channel);
1694 complete(&ar->peer_assoc_done);
1695 complete(&ar->peer_delete_done);
1696 complete(&ar->install_key_done);
1697 complete(&ar->vdev_setup_done);
1698 complete(&ar->vdev_delete_done);
1699 complete(&ar->bss_survey_done);
1700 complete(&ar->thermal.wmi_sync);
1701
1702 wake_up(&ar->dp.tx_empty_waitq);
1703 idr_for_each(&ar->txmgmt_idr,
1704 ath11k_mac_tx_mgmt_pending_free, ar);
1705 idr_destroy(&ar->txmgmt_idr);
1706 wake_up(&ar->txmgmt_empty_waitq);
1707 }
1708
1709 wake_up(&ab->wmi_ab.tx_credits_wq);
1710 wake_up(&ab->peer_mapping_wq);
1711
1712 reinit_completion(&ab->driver_recovery);
1713 }
1714
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)1715 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
1716 {
1717 struct ath11k *ar;
1718 struct ath11k_pdev *pdev;
1719 int i;
1720
1721 for (i = 0; i < ab->num_radios; i++) {
1722 pdev = &ab->pdevs[i];
1723 ar = pdev->ar;
1724 if (!ar || ar->state == ATH11K_STATE_OFF)
1725 continue;
1726
1727 mutex_lock(&ar->conf_mutex);
1728
1729 switch (ar->state) {
1730 case ATH11K_STATE_ON:
1731 ar->state = ATH11K_STATE_RESTARTING;
1732 ath11k_core_halt(ar);
1733 ieee80211_restart_hw(ar->hw);
1734 break;
1735 case ATH11K_STATE_OFF:
1736 ath11k_warn(ab,
1737 "cannot restart radio %d that hasn't been started\n",
1738 i);
1739 break;
1740 case ATH11K_STATE_RESTARTING:
1741 break;
1742 case ATH11K_STATE_RESTARTED:
1743 ar->state = ATH11K_STATE_WEDGED;
1744 fallthrough;
1745 case ATH11K_STATE_WEDGED:
1746 ath11k_warn(ab,
1747 "device is wedged, will not restart radio %d\n", i);
1748 break;
1749 }
1750 mutex_unlock(&ar->conf_mutex);
1751 }
1752 complete(&ab->driver_recovery);
1753 }
1754
ath11k_core_restart(struct work_struct * work)1755 static void ath11k_core_restart(struct work_struct *work)
1756 {
1757 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
1758 int ret;
1759
1760 if (!ab->is_reset)
1761 ath11k_core_pre_reconfigure_recovery(ab);
1762
1763 ret = ath11k_core_reconfigure_on_crash(ab);
1764 if (ret) {
1765 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
1766 return;
1767 }
1768
1769 if (ab->is_reset)
1770 complete_all(&ab->reconfigure_complete);
1771
1772 if (!ab->is_reset)
1773 ath11k_core_post_reconfigure_recovery(ab);
1774 }
1775
ath11k_core_reset(struct work_struct * work)1776 static void ath11k_core_reset(struct work_struct *work)
1777 {
1778 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
1779 int reset_count, fail_cont_count;
1780 long time_left;
1781
1782 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
1783 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
1784 return;
1785 }
1786
1787 /* Sometimes the recovery will fail and then the next all recovery fail,
1788 * this is to avoid infinite recovery since it can not recovery success.
1789 */
1790 fail_cont_count = atomic_read(&ab->fail_cont_count);
1791
1792 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
1793 return;
1794
1795 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
1796 time_before(jiffies, ab->reset_fail_timeout))
1797 return;
1798
1799 reset_count = atomic_inc_return(&ab->reset_count);
1800
1801 if (reset_count > 1) {
1802 /* Sometimes it happened another reset worker before the previous one
1803 * completed, then the second reset worker will destroy the previous one,
1804 * thus below is to avoid that.
1805 */
1806 ath11k_warn(ab, "already resetting count %d\n", reset_count);
1807
1808 reinit_completion(&ab->reset_complete);
1809 time_left = wait_for_completion_timeout(&ab->reset_complete,
1810 ATH11K_RESET_TIMEOUT_HZ);
1811
1812 if (time_left) {
1813 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
1814 atomic_dec(&ab->reset_count);
1815 return;
1816 }
1817
1818 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
1819 /* Record the continuous recovery fail count when recovery failed*/
1820 atomic_inc(&ab->fail_cont_count);
1821 }
1822
1823 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
1824
1825 ab->is_reset = true;
1826 atomic_set(&ab->recovery_count, 0);
1827 reinit_completion(&ab->recovery_start);
1828 atomic_set(&ab->recovery_start_count, 0);
1829
1830 ath11k_core_pre_reconfigure_recovery(ab);
1831
1832 reinit_completion(&ab->reconfigure_complete);
1833 ath11k_core_post_reconfigure_recovery(ab);
1834
1835 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
1836
1837 time_left = wait_for_completion_timeout(&ab->recovery_start,
1838 ATH11K_RECOVER_START_TIMEOUT_HZ);
1839
1840 ath11k_hif_power_down(ab);
1841 ath11k_hif_power_up(ab);
1842
1843 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
1844 }
1845
ath11k_init_hw_params(struct ath11k_base * ab)1846 static int ath11k_init_hw_params(struct ath11k_base *ab)
1847 {
1848 const struct ath11k_hw_params *hw_params = NULL;
1849 int i;
1850
1851 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
1852 hw_params = &ath11k_hw_params[i];
1853
1854 if (hw_params->hw_rev == ab->hw_rev)
1855 break;
1856 }
1857
1858 if (i == ARRAY_SIZE(ath11k_hw_params)) {
1859 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1860 return -EINVAL;
1861 }
1862
1863 ab->hw_params = *hw_params;
1864
1865 ath11k_info(ab, "%s\n", ab->hw_params.name);
1866
1867 return 0;
1868 }
1869
ath11k_core_pre_init(struct ath11k_base * ab)1870 int ath11k_core_pre_init(struct ath11k_base *ab)
1871 {
1872 int ret;
1873
1874 ret = ath11k_init_hw_params(ab);
1875 if (ret) {
1876 ath11k_err(ab, "failed to get hw params: %d\n", ret);
1877 return ret;
1878 }
1879
1880 return 0;
1881 }
1882 EXPORT_SYMBOL(ath11k_core_pre_init);
1883
ath11k_core_init(struct ath11k_base * ab)1884 int ath11k_core_init(struct ath11k_base *ab)
1885 {
1886 int ret;
1887
1888 ret = ath11k_core_soc_create(ab);
1889 if (ret) {
1890 ath11k_err(ab, "failed to create soc core: %d\n", ret);
1891 return ret;
1892 }
1893
1894 return 0;
1895 }
1896 EXPORT_SYMBOL(ath11k_core_init);
1897
ath11k_core_deinit(struct ath11k_base * ab)1898 void ath11k_core_deinit(struct ath11k_base *ab)
1899 {
1900 mutex_lock(&ab->core_lock);
1901
1902 ath11k_core_pdev_destroy(ab);
1903 ath11k_core_stop(ab);
1904
1905 mutex_unlock(&ab->core_lock);
1906
1907 ath11k_hif_power_down(ab);
1908 ath11k_mac_destroy(ab);
1909 ath11k_core_soc_destroy(ab);
1910 }
1911 EXPORT_SYMBOL(ath11k_core_deinit);
1912
ath11k_core_free(struct ath11k_base * ab)1913 void ath11k_core_free(struct ath11k_base *ab)
1914 {
1915 destroy_workqueue(ab->workqueue_aux);
1916 destroy_workqueue(ab->workqueue);
1917
1918 kfree(ab);
1919 }
1920 EXPORT_SYMBOL(ath11k_core_free);
1921
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)1922 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1923 enum ath11k_bus bus)
1924 {
1925 struct ath11k_base *ab;
1926
1927 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
1928 if (!ab)
1929 return NULL;
1930
1931 init_completion(&ab->driver_recovery);
1932
1933 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
1934 if (!ab->workqueue)
1935 goto err_sc_free;
1936
1937 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
1938 if (!ab->workqueue_aux)
1939 goto err_free_wq;
1940
1941 mutex_init(&ab->core_lock);
1942 mutex_init(&ab->tbl_mtx_lock);
1943 spin_lock_init(&ab->base_lock);
1944 mutex_init(&ab->vdev_id_11d_lock);
1945 init_completion(&ab->reset_complete);
1946 init_completion(&ab->reconfigure_complete);
1947 init_completion(&ab->recovery_start);
1948
1949 INIT_LIST_HEAD(&ab->peers);
1950 init_waitqueue_head(&ab->peer_mapping_wq);
1951 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
1952 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
1953 INIT_WORK(&ab->restart_work, ath11k_core_restart);
1954 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
1955 INIT_WORK(&ab->reset_work, ath11k_core_reset);
1956 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
1957 init_completion(&ab->htc_suspend);
1958 init_completion(&ab->wow.wakeup_completed);
1959
1960 ab->dev = dev;
1961 ab->hif.bus = bus;
1962
1963 return ab;
1964
1965 err_free_wq:
1966 destroy_workqueue(ab->workqueue);
1967 err_sc_free:
1968 kfree(ab);
1969 return NULL;
1970 }
1971 EXPORT_SYMBOL(ath11k_core_alloc);
1972
1973 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
1974 MODULE_LICENSE("Dual BSD/GPL");
1975