1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22
23 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)24 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
25 {
26 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
27 }
28
29 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)30 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
31 struct hal_rx_desc *desc)
32 {
33 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
34 return HAL_ENCRYPT_TYPE_OPEN;
35
36 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
37 }
38
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)39 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
40 struct hal_rx_desc *desc)
41 {
42 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
43 }
44
45 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)46 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
47 struct hal_rx_desc *desc)
48 {
49 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
50 }
51
52 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)53 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
54 struct hal_rx_desc *desc)
55 {
56 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
57 }
58
59 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)60 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
61 struct hal_rx_desc *desc)
62 {
63 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
64 }
65
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)66 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
67 struct hal_rx_desc *desc)
68 {
69 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
70 }
71
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)72 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
73 struct sk_buff *skb)
74 {
75 struct ieee80211_hdr *hdr;
76
77 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
78 return ieee80211_has_morefrags(hdr->frame_control);
79 }
80
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)81 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
82 struct sk_buff *skb)
83 {
84 struct ieee80211_hdr *hdr;
85
86 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
87 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
88 }
89
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)90 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
91 struct hal_rx_desc *desc)
92 {
93 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
94 }
95
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)96 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
97 struct hal_rx_desc *desc)
98 {
99 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
100 }
101
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)102 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
103 {
104 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
105 __le32_to_cpu(attn->info2));
106 }
107
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)108 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
109 {
110 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
111 __le32_to_cpu(attn->info1));
112 }
113
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)114 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
115 {
116 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
117 __le32_to_cpu(attn->info1));
118 }
119
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)120 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
121 {
122 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
123 __le32_to_cpu(attn->info2)) ==
124 RX_DESC_DECRYPT_STATUS_CODE_OK);
125 }
126
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)127 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
128 {
129 u32 info = __le32_to_cpu(attn->info1);
130 u32 errmap = 0;
131
132 if (info & RX_ATTENTION_INFO1_FCS_ERR)
133 errmap |= DP_RX_MPDU_ERR_FCS;
134
135 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
136 errmap |= DP_RX_MPDU_ERR_DECRYPT;
137
138 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
139 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
140
141 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
142 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
143
144 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
145 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
146
147 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
148 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
149
150 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
151 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
152
153 return errmap;
154 }
155
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)156 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
157 struct hal_rx_desc *desc)
158 {
159 struct rx_attention *rx_attention;
160 u32 errmap;
161
162 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
163 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
164
165 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
166 }
167
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)168 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
169 struct hal_rx_desc *desc)
170 {
171 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
172 }
173
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)174 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
175 struct hal_rx_desc *desc)
176 {
177 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
178 }
179
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)180 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
181 struct hal_rx_desc *desc)
182 {
183 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
184 }
185
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)186 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
187 struct hal_rx_desc *desc)
188 {
189 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
190 }
191
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)192 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
193 struct hal_rx_desc *desc)
194 {
195 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
196 }
197
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)198 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
199 struct hal_rx_desc *desc)
200 {
201 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
202 }
203
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)204 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
205 struct hal_rx_desc *desc)
206 {
207 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
208 }
209
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)210 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
211 struct hal_rx_desc *desc)
212 {
213 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
214 }
215
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)216 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
217 struct hal_rx_desc *desc)
218 {
219 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
220 }
221
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)222 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
223 struct hal_rx_desc *desc)
224 {
225 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
226 }
227
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)228 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
229 struct hal_rx_desc *desc)
230 {
231 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
232 }
233
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)234 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
235 struct hal_rx_desc *desc)
236 {
237 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
238 }
239
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)240 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
241 struct hal_rx_desc *fdesc,
242 struct hal_rx_desc *ldesc)
243 {
244 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
245 }
246
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)247 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
248 {
249 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
250 __le32_to_cpu(attn->info1));
251 }
252
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)253 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
254 struct hal_rx_desc *rx_desc)
255 {
256 u8 *rx_pkt_hdr;
257
258 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
259
260 return rx_pkt_hdr;
261 }
262
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)263 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
264 struct hal_rx_desc *rx_desc)
265 {
266 u32 tlv_tag;
267
268 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
269
270 return tlv_tag == HAL_RX_MPDU_START;
271 }
272
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)273 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
274 struct hal_rx_desc *rx_desc)
275 {
276 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
277 }
278
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)279 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
280 struct hal_rx_desc *desc,
281 u16 len)
282 {
283 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
284 }
285
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)286 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
287 struct hal_rx_desc *desc)
288 {
289 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
290
291 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
292 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
293 __le32_to_cpu(attn->info1)));
294 }
295
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)296 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
297 struct hal_rx_desc *desc)
298 {
299 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
300 }
301
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)302 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
303 struct hal_rx_desc *desc)
304 {
305 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
306 }
307
ath11k_dp_service_mon_ring(struct timer_list * t)308 static void ath11k_dp_service_mon_ring(struct timer_list *t)
309 {
310 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
311 int i;
312
313 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
314 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
315
316 mod_timer(&ab->mon_reap_timer, jiffies +
317 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
318 }
319
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)320 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
321 {
322 int i, reaped = 0;
323 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
324
325 do {
326 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
327 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
328 NULL,
329 DP_MON_SERVICE_BUDGET);
330
331 /* nothing more to reap */
332 if (reaped < DP_MON_SERVICE_BUDGET)
333 return 0;
334
335 } while (time_before(jiffies, timeout));
336
337 ath11k_warn(ab, "dp mon ring purge timeout");
338
339 return -ETIMEDOUT;
340 }
341
342 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)343 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
344 struct dp_rxdma_ring *rx_ring,
345 int req_entries,
346 enum hal_rx_buf_return_buf_manager mgr)
347 {
348 struct hal_srng *srng;
349 u32 *desc;
350 struct sk_buff *skb;
351 int num_free;
352 int num_remain;
353 int buf_id;
354 u32 cookie;
355 dma_addr_t paddr;
356
357 req_entries = min(req_entries, rx_ring->bufs_max);
358
359 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
360
361 spin_lock_bh(&srng->lock);
362
363 ath11k_hal_srng_access_begin(ab, srng);
364
365 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
366 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
367 req_entries = num_free;
368
369 req_entries = min(num_free, req_entries);
370 num_remain = req_entries;
371
372 while (num_remain > 0) {
373 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
374 DP_RX_BUFFER_ALIGN_SIZE);
375 if (!skb)
376 break;
377
378 if (!IS_ALIGNED((unsigned long)skb->data,
379 DP_RX_BUFFER_ALIGN_SIZE)) {
380 skb_pull(skb,
381 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
382 skb->data);
383 }
384
385 paddr = dma_map_single(ab->dev, skb->data,
386 skb->len + skb_tailroom(skb),
387 DMA_FROM_DEVICE);
388 if (dma_mapping_error(ab->dev, paddr))
389 goto fail_free_skb;
390
391 spin_lock_bh(&rx_ring->idr_lock);
392 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
393 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
394 spin_unlock_bh(&rx_ring->idr_lock);
395 if (buf_id <= 0)
396 goto fail_dma_unmap;
397
398 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
399 if (!desc)
400 goto fail_idr_remove;
401
402 ATH11K_SKB_RXCB(skb)->paddr = paddr;
403
404 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
405 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
406
407 num_remain--;
408
409 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
410 }
411
412 ath11k_hal_srng_access_end(ab, srng);
413
414 spin_unlock_bh(&srng->lock);
415
416 return req_entries - num_remain;
417
418 fail_idr_remove:
419 spin_lock_bh(&rx_ring->idr_lock);
420 idr_remove(&rx_ring->bufs_idr, buf_id);
421 spin_unlock_bh(&rx_ring->idr_lock);
422 fail_dma_unmap:
423 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
424 DMA_FROM_DEVICE);
425 fail_free_skb:
426 dev_kfree_skb_any(skb);
427
428 ath11k_hal_srng_access_end(ab, srng);
429
430 spin_unlock_bh(&srng->lock);
431
432 return req_entries - num_remain;
433 }
434
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)435 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
436 struct dp_rxdma_ring *rx_ring)
437 {
438 struct ath11k_pdev_dp *dp = &ar->dp;
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 /* if rxdma1_enable is false, mon_status_refill_ring
457 * isn't setup, so don't clean.
458 */
459 if (!ar->ab->hw_params.rxdma1_enable)
460 return 0;
461
462 rx_ring = &dp->rx_mon_status_refill_ring[0];
463
464 spin_lock_bh(&rx_ring->idr_lock);
465 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
466 idr_remove(&rx_ring->bufs_idr, buf_id);
467 /* XXX: Understand where internal driver does this dma_unmap
468 * of rxdma_buffer.
469 */
470 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
471 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
472 dev_kfree_skb_any(skb);
473 }
474
475 idr_destroy(&rx_ring->bufs_idr);
476 spin_unlock_bh(&rx_ring->idr_lock);
477
478 return 0;
479 }
480
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)481 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 struct ath11k_base *ab = ar->ab;
485 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
486 int i;
487
488 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
489
490 rx_ring = &dp->rxdma_mon_buf_ring;
491 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
492
493 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
494 rx_ring = &dp->rx_mon_status_refill_ring[i];
495 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
496 }
497
498 return 0;
499 }
500
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)501 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
502 struct dp_rxdma_ring *rx_ring,
503 u32 ringtype)
504 {
505 struct ath11k_pdev_dp *dp = &ar->dp;
506 int num_entries;
507
508 num_entries = rx_ring->refill_buf_ring.size /
509 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
510
511 rx_ring->bufs_max = num_entries;
512 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
513 ar->ab->hw_params.hal_params->rx_buf_rbm);
514 return 0;
515 }
516
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)517 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
522 int i;
523
524 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
525
526 if (ar->ab->hw_params.rxdma1_enable) {
527 rx_ring = &dp->rxdma_mon_buf_ring;
528 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
529 }
530
531 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
532 rx_ring = &dp->rx_mon_status_refill_ring[i];
533 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
534 }
535
536 return 0;
537 }
538
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)539 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
540 {
541 struct ath11k_pdev_dp *dp = &ar->dp;
542 struct ath11k_base *ab = ar->ab;
543 int i;
544
545 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
546
547 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
548 if (ab->hw_params.rx_mac_buf_ring)
549 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
550
551 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
552 ath11k_dp_srng_cleanup(ab,
553 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
554 }
555
556 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
557 }
558
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)559 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
560 {
561 struct ath11k_dp *dp = &ab->dp;
562 int i;
563
564 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
565 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
566 }
567
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)568 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
569 {
570 struct ath11k_dp *dp = &ab->dp;
571 int ret;
572 int i;
573
574 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
575 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
576 HAL_REO_DST, i, 0,
577 DP_REO_DST_RING_SIZE);
578 if (ret) {
579 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
580 goto err_reo_cleanup;
581 }
582 }
583
584 return 0;
585
586 err_reo_cleanup:
587 ath11k_dp_pdev_reo_cleanup(ab);
588
589 return ret;
590 }
591
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)592 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
593 {
594 struct ath11k_pdev_dp *dp = &ar->dp;
595 struct ath11k_base *ab = ar->ab;
596 struct dp_srng *srng = NULL;
597 int i;
598 int ret;
599
600 ret = ath11k_dp_srng_setup(ar->ab,
601 &dp->rx_refill_buf_ring.refill_buf_ring,
602 HAL_RXDMA_BUF, 0,
603 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
604 if (ret) {
605 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
606 return ret;
607 }
608
609 if (ar->ab->hw_params.rx_mac_buf_ring) {
610 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
611 ret = ath11k_dp_srng_setup(ar->ab,
612 &dp->rx_mac_buf_ring[i],
613 HAL_RXDMA_BUF, 1,
614 dp->mac_id + i, 1024);
615 if (ret) {
616 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
617 i);
618 return ret;
619 }
620 }
621 }
622
623 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
624 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
625 HAL_RXDMA_DST, 0, dp->mac_id + i,
626 DP_RXDMA_ERR_DST_RING_SIZE);
627 if (ret) {
628 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
629 return ret;
630 }
631 }
632
633 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
634 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
635 ret = ath11k_dp_srng_setup(ar->ab,
636 srng,
637 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
638 DP_RXDMA_MON_STATUS_RING_SIZE);
639 if (ret) {
640 ath11k_warn(ar->ab,
641 "failed to setup rx_mon_status_refill_ring %d\n", i);
642 return ret;
643 }
644 }
645
646 /* if rxdma1_enable is false, then it doesn't need
647 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
648 * and rxdma_mon_desc_ring.
649 * init reap timer for QCA6390.
650 */
651 if (!ar->ab->hw_params.rxdma1_enable) {
652 //init mon status buffer reap timer
653 timer_setup(&ar->ab->mon_reap_timer,
654 ath11k_dp_service_mon_ring, 0);
655 return 0;
656 }
657
658 ret = ath11k_dp_srng_setup(ar->ab,
659 &dp->rxdma_mon_buf_ring.refill_buf_ring,
660 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
661 DP_RXDMA_MONITOR_BUF_RING_SIZE);
662 if (ret) {
663 ath11k_warn(ar->ab,
664 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
665 return ret;
666 }
667
668 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
669 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
670 DP_RXDMA_MONITOR_DST_RING_SIZE);
671 if (ret) {
672 ath11k_warn(ar->ab,
673 "failed to setup HAL_RXDMA_MONITOR_DST\n");
674 return ret;
675 }
676
677 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
678 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
679 DP_RXDMA_MONITOR_DESC_RING_SIZE);
680 if (ret) {
681 ath11k_warn(ar->ab,
682 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
683 return ret;
684 }
685
686 return 0;
687 }
688
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)689 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
690 {
691 struct ath11k_dp *dp = &ab->dp;
692 struct dp_reo_cmd *cmd, *tmp;
693 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
694
695 spin_lock_bh(&dp->reo_cmd_lock);
696 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
697 list_del(&cmd->list);
698 dma_unmap_single(ab->dev, cmd->data.paddr,
699 cmd->data.size, DMA_BIDIRECTIONAL);
700 kfree(cmd->data.vaddr);
701 kfree(cmd);
702 }
703
704 list_for_each_entry_safe(cmd_cache, tmp_cache,
705 &dp->reo_cmd_cache_flush_list, list) {
706 list_del(&cmd_cache->list);
707 dp->reo_cmd_cache_flush_count--;
708 dma_unmap_single(ab->dev, cmd_cache->data.paddr,
709 cmd_cache->data.size, DMA_BIDIRECTIONAL);
710 kfree(cmd_cache->data.vaddr);
711 kfree(cmd_cache);
712 }
713 spin_unlock_bh(&dp->reo_cmd_lock);
714 }
715
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)716 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
717 enum hal_reo_cmd_status status)
718 {
719 struct dp_rx_tid *rx_tid = ctx;
720
721 if (status != HAL_REO_CMD_SUCCESS)
722 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
723 rx_tid->tid, status);
724
725 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
726 DMA_BIDIRECTIONAL);
727 kfree(rx_tid->vaddr);
728 }
729
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)730 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
731 struct dp_rx_tid *rx_tid)
732 {
733 struct ath11k_hal_reo_cmd cmd = {0};
734 unsigned long tot_desc_sz, desc_sz;
735 int ret;
736
737 tot_desc_sz = rx_tid->size;
738 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
739
740 while (tot_desc_sz > desc_sz) {
741 tot_desc_sz -= desc_sz;
742 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
743 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
744 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
745 HAL_REO_CMD_FLUSH_CACHE, &cmd,
746 NULL);
747 if (ret)
748 ath11k_warn(ab,
749 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
750 rx_tid->tid, ret);
751 }
752
753 memset(&cmd, 0, sizeof(cmd));
754 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
755 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
756 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
757 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
758 HAL_REO_CMD_FLUSH_CACHE,
759 &cmd, ath11k_dp_reo_cmd_free);
760 if (ret) {
761 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
762 rx_tid->tid, ret);
763 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
764 DMA_BIDIRECTIONAL);
765 kfree(rx_tid->vaddr);
766 }
767 }
768
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)769 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
770 enum hal_reo_cmd_status status)
771 {
772 struct ath11k_base *ab = dp->ab;
773 struct dp_rx_tid *rx_tid = ctx;
774 struct dp_reo_cache_flush_elem *elem, *tmp;
775
776 if (status == HAL_REO_CMD_DRAIN) {
777 goto free_desc;
778 } else if (status != HAL_REO_CMD_SUCCESS) {
779 /* Shouldn't happen! Cleanup in case of other failure? */
780 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
781 rx_tid->tid, status);
782 return;
783 }
784
785 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
786 if (!elem)
787 goto free_desc;
788
789 elem->ts = jiffies;
790 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
791
792 spin_lock_bh(&dp->reo_cmd_lock);
793 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
794 dp->reo_cmd_cache_flush_count++;
795
796 /* Flush and invalidate aged REO desc from HW cache */
797 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
798 list) {
799 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
800 time_after(jiffies, elem->ts +
801 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
802 list_del(&elem->list);
803 dp->reo_cmd_cache_flush_count--;
804 spin_unlock_bh(&dp->reo_cmd_lock);
805
806 ath11k_dp_reo_cache_flush(ab, &elem->data);
807 kfree(elem);
808 spin_lock_bh(&dp->reo_cmd_lock);
809 }
810 }
811 spin_unlock_bh(&dp->reo_cmd_lock);
812
813 return;
814 free_desc:
815 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
816 DMA_BIDIRECTIONAL);
817 kfree(rx_tid->vaddr);
818 }
819
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)820 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
821 struct ath11k_peer *peer, u8 tid)
822 {
823 struct ath11k_hal_reo_cmd cmd = {0};
824 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
825 int ret;
826
827 if (!rx_tid->active)
828 return;
829
830 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
831 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
832 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
833 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
834 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
835 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
836 ath11k_dp_rx_tid_del_func);
837 if (ret) {
838 if (ret != -ESHUTDOWN)
839 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
840 tid, ret);
841 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
842 DMA_BIDIRECTIONAL);
843 kfree(rx_tid->vaddr);
844 }
845
846 rx_tid->active = false;
847 }
848
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)849 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
850 u32 *link_desc,
851 enum hal_wbm_rel_bm_act action)
852 {
853 struct ath11k_dp *dp = &ab->dp;
854 struct hal_srng *srng;
855 u32 *desc;
856 int ret = 0;
857
858 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
859
860 spin_lock_bh(&srng->lock);
861
862 ath11k_hal_srng_access_begin(ab, srng);
863
864 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
865 if (!desc) {
866 ret = -ENOBUFS;
867 goto exit;
868 }
869
870 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
871 action);
872
873 exit:
874 ath11k_hal_srng_access_end(ab, srng);
875
876 spin_unlock_bh(&srng->lock);
877
878 return ret;
879 }
880
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)881 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
882 {
883 struct ath11k_base *ab = rx_tid->ab;
884
885 lockdep_assert_held(&ab->base_lock);
886
887 if (rx_tid->dst_ring_desc) {
888 if (rel_link_desc)
889 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
890 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
891 kfree(rx_tid->dst_ring_desc);
892 rx_tid->dst_ring_desc = NULL;
893 }
894
895 rx_tid->cur_sn = 0;
896 rx_tid->last_frag_no = 0;
897 rx_tid->rx_frag_bitmap = 0;
898 __skb_queue_purge(&rx_tid->rx_frags);
899 }
900
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)901 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
902 {
903 struct dp_rx_tid *rx_tid;
904 int i;
905
906 lockdep_assert_held(&ar->ab->base_lock);
907
908 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
909 rx_tid = &peer->rx_tid[i];
910
911 spin_unlock_bh(&ar->ab->base_lock);
912 del_timer_sync(&rx_tid->frag_timer);
913 spin_lock_bh(&ar->ab->base_lock);
914
915 ath11k_dp_rx_frags_cleanup(rx_tid, true);
916 }
917 }
918
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)919 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
920 {
921 struct dp_rx_tid *rx_tid;
922 int i;
923
924 lockdep_assert_held(&ar->ab->base_lock);
925
926 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
927 rx_tid = &peer->rx_tid[i];
928
929 ath11k_peer_rx_tid_delete(ar, peer, i);
930 ath11k_dp_rx_frags_cleanup(rx_tid, true);
931
932 spin_unlock_bh(&ar->ab->base_lock);
933 del_timer_sync(&rx_tid->frag_timer);
934 spin_lock_bh(&ar->ab->base_lock);
935 }
936 }
937
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)938 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
939 struct ath11k_peer *peer,
940 struct dp_rx_tid *rx_tid,
941 u32 ba_win_sz, u16 ssn,
942 bool update_ssn)
943 {
944 struct ath11k_hal_reo_cmd cmd = {0};
945 int ret;
946
947 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
948 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
949 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
950 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
951 cmd.ba_window_size = ba_win_sz;
952
953 if (update_ssn) {
954 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
955 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
956 }
957
958 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
959 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
960 NULL);
961 if (ret) {
962 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
963 rx_tid->tid, ret);
964 return ret;
965 }
966
967 rx_tid->ba_win_sz = ba_win_sz;
968
969 return 0;
970 }
971
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)972 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
973 const u8 *peer_mac, int vdev_id, u8 tid)
974 {
975 struct ath11k_peer *peer;
976 struct dp_rx_tid *rx_tid;
977
978 spin_lock_bh(&ab->base_lock);
979
980 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
981 if (!peer) {
982 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
983 goto unlock_exit;
984 }
985
986 rx_tid = &peer->rx_tid[tid];
987 if (!rx_tid->active)
988 goto unlock_exit;
989
990 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
991 DMA_BIDIRECTIONAL);
992 kfree(rx_tid->vaddr);
993
994 rx_tid->active = false;
995
996 unlock_exit:
997 spin_unlock_bh(&ab->base_lock);
998 }
999
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)1000 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
1001 u8 tid, u32 ba_win_sz, u16 ssn,
1002 enum hal_pn_type pn_type)
1003 {
1004 struct ath11k_base *ab = ar->ab;
1005 struct ath11k_peer *peer;
1006 struct dp_rx_tid *rx_tid;
1007 u32 hw_desc_sz;
1008 u32 *addr_aligned;
1009 void *vaddr;
1010 dma_addr_t paddr;
1011 int ret;
1012
1013 spin_lock_bh(&ab->base_lock);
1014
1015 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1016 if (!peer) {
1017 ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
1018 spin_unlock_bh(&ab->base_lock);
1019 return -ENOENT;
1020 }
1021
1022 rx_tid = &peer->rx_tid[tid];
1023 /* Update the tid queue if it is already setup */
1024 if (rx_tid->active) {
1025 paddr = rx_tid->paddr;
1026 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1027 ba_win_sz, ssn, true);
1028 spin_unlock_bh(&ab->base_lock);
1029 if (ret) {
1030 ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
1031 return ret;
1032 }
1033
1034 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1035 peer_mac, paddr,
1036 tid, 1, ba_win_sz);
1037 if (ret)
1038 ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
1039 tid, ret);
1040 return ret;
1041 }
1042
1043 rx_tid->tid = tid;
1044
1045 rx_tid->ba_win_sz = ba_win_sz;
1046
1047 /* TODO: Optimize the memory allocation for qos tid based on
1048 * the actual BA window size in REO tid update path.
1049 */
1050 if (tid == HAL_DESC_REO_NON_QOS_TID)
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1052 else
1053 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1054
1055 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1056 if (!vaddr) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1062
1063 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1064 ssn, pn_type);
1065
1066 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1067 DMA_BIDIRECTIONAL);
1068
1069 ret = dma_mapping_error(ab->dev, paddr);
1070 if (ret) {
1071 spin_unlock_bh(&ab->base_lock);
1072 goto err_mem_free;
1073 }
1074
1075 rx_tid->vaddr = vaddr;
1076 rx_tid->paddr = paddr;
1077 rx_tid->size = hw_desc_sz;
1078 rx_tid->active = true;
1079
1080 spin_unlock_bh(&ab->base_lock);
1081
1082 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1083 paddr, tid, 1, ba_win_sz);
1084 if (ret) {
1085 ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1086 tid, ret);
1087 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1088 }
1089
1090 return ret;
1091
1092 err_mem_free:
1093 kfree(vaddr);
1094
1095 return ret;
1096 }
1097
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1098 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1099 struct ieee80211_ampdu_params *params)
1100 {
1101 struct ath11k_base *ab = ar->ab;
1102 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1103 int vdev_id = arsta->arvif->vdev_id;
1104 int ret;
1105
1106 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1107 params->tid, params->buf_size,
1108 params->ssn, arsta->pn_type);
1109 if (ret)
1110 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1111
1112 return ret;
1113 }
1114
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1115 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1116 struct ieee80211_ampdu_params *params)
1117 {
1118 struct ath11k_base *ab = ar->ab;
1119 struct ath11k_peer *peer;
1120 struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1121 int vdev_id = arsta->arvif->vdev_id;
1122 dma_addr_t paddr;
1123 bool active;
1124 int ret;
1125
1126 spin_lock_bh(&ab->base_lock);
1127
1128 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1129 if (!peer) {
1130 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1131 spin_unlock_bh(&ab->base_lock);
1132 return -ENOENT;
1133 }
1134
1135 paddr = peer->rx_tid[params->tid].paddr;
1136 active = peer->rx_tid[params->tid].active;
1137
1138 if (!active) {
1139 spin_unlock_bh(&ab->base_lock);
1140 return 0;
1141 }
1142
1143 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1144 spin_unlock_bh(&ab->base_lock);
1145 if (ret) {
1146 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1147 params->tid, ret);
1148 return ret;
1149 }
1150
1151 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1152 params->sta->addr, paddr,
1153 params->tid, 1, 1);
1154 if (ret)
1155 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1156 ret);
1157
1158 return ret;
1159 }
1160
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1161 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1162 const u8 *peer_addr,
1163 enum set_key_cmd key_cmd,
1164 struct ieee80211_key_conf *key)
1165 {
1166 struct ath11k *ar = arvif->ar;
1167 struct ath11k_base *ab = ar->ab;
1168 struct ath11k_hal_reo_cmd cmd = {0};
1169 struct ath11k_peer *peer;
1170 struct dp_rx_tid *rx_tid;
1171 u8 tid;
1172 int ret = 0;
1173
1174 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1175 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1176 * for now.
1177 */
1178 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1179 return 0;
1180
1181 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1182 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1183 HAL_REO_CMD_UPD0_PN_SIZE |
1184 HAL_REO_CMD_UPD0_PN_VALID |
1185 HAL_REO_CMD_UPD0_PN_CHECK |
1186 HAL_REO_CMD_UPD0_SVLD;
1187
1188 switch (key->cipher) {
1189 case WLAN_CIPHER_SUITE_TKIP:
1190 case WLAN_CIPHER_SUITE_CCMP:
1191 case WLAN_CIPHER_SUITE_CCMP_256:
1192 case WLAN_CIPHER_SUITE_GCMP:
1193 case WLAN_CIPHER_SUITE_GCMP_256:
1194 if (key_cmd == SET_KEY) {
1195 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1196 cmd.pn_size = 48;
1197 }
1198 break;
1199 default:
1200 break;
1201 }
1202
1203 spin_lock_bh(&ab->base_lock);
1204
1205 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1206 if (!peer) {
1207 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1208 spin_unlock_bh(&ab->base_lock);
1209 return -ENOENT;
1210 }
1211
1212 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1213 rx_tid = &peer->rx_tid[tid];
1214 if (!rx_tid->active)
1215 continue;
1216 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1217 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1218 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1219 HAL_REO_CMD_UPDATE_RX_QUEUE,
1220 &cmd, NULL);
1221 if (ret) {
1222 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1223 tid, ret);
1224 break;
1225 }
1226 }
1227
1228 spin_unlock_bh(&ab->base_lock);
1229
1230 return ret;
1231 }
1232
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1233 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1234 u16 peer_id)
1235 {
1236 int i;
1237
1238 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1239 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1240 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1241 return i;
1242 } else {
1243 return i;
1244 }
1245 }
1246
1247 return -EINVAL;
1248 }
1249
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1250 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1251 u16 tag, u16 len, const void *ptr,
1252 void *data)
1253 {
1254 struct htt_ppdu_stats_info *ppdu_info;
1255 struct htt_ppdu_user_stats *user_stats;
1256 int cur_user;
1257 u16 peer_id;
1258
1259 ppdu_info = (struct htt_ppdu_stats_info *)data;
1260
1261 switch (tag) {
1262 case HTT_PPDU_STATS_TAG_COMMON:
1263 if (len < sizeof(struct htt_ppdu_stats_common)) {
1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1265 len, tag);
1266 return -EINVAL;
1267 }
1268 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1269 sizeof(struct htt_ppdu_stats_common));
1270 break;
1271 case HTT_PPDU_STATS_TAG_USR_RATE:
1272 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1273 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1274 len, tag);
1275 return -EINVAL;
1276 }
1277
1278 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1279 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1280 peer_id);
1281 if (cur_user < 0)
1282 return -EINVAL;
1283 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1284 user_stats->peer_id = peer_id;
1285 user_stats->is_valid_peer_id = true;
1286 memcpy((void *)&user_stats->rate, ptr,
1287 sizeof(struct htt_ppdu_stats_user_rate));
1288 user_stats->tlv_flags |= BIT(tag);
1289 break;
1290 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1291 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1292 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1293 len, tag);
1294 return -EINVAL;
1295 }
1296
1297 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1298 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1299 peer_id);
1300 if (cur_user < 0)
1301 return -EINVAL;
1302 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1303 user_stats->peer_id = peer_id;
1304 user_stats->is_valid_peer_id = true;
1305 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1306 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1307 user_stats->tlv_flags |= BIT(tag);
1308 break;
1309 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1310 if (len <
1311 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1312 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1313 len, tag);
1314 return -EINVAL;
1315 }
1316
1317 peer_id =
1318 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1319 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1320 peer_id);
1321 if (cur_user < 0)
1322 return -EINVAL;
1323 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1324 user_stats->peer_id = peer_id;
1325 user_stats->is_valid_peer_id = true;
1326 memcpy((void *)&user_stats->ack_ba, ptr,
1327 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1328 user_stats->tlv_flags |= BIT(tag);
1329 break;
1330 }
1331 return 0;
1332 }
1333
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1334 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1335 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1336 const void *ptr, void *data),
1337 void *data)
1338 {
1339 const struct htt_tlv *tlv;
1340 const void *begin = ptr;
1341 u16 tlv_tag, tlv_len;
1342 int ret = -EINVAL;
1343
1344 while (len > 0) {
1345 if (len < sizeof(*tlv)) {
1346 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1347 ptr - begin, len, sizeof(*tlv));
1348 return -EINVAL;
1349 }
1350 tlv = (struct htt_tlv *)ptr;
1351 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1352 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1353 ptr += sizeof(*tlv);
1354 len -= sizeof(*tlv);
1355
1356 if (tlv_len > len) {
1357 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1358 tlv_tag, ptr - begin, len, tlv_len);
1359 return -EINVAL;
1360 }
1361 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1362 if (ret == -ENOMEM)
1363 return ret;
1364
1365 ptr += tlv_len;
1366 len -= tlv_len;
1367 }
1368 return 0;
1369 }
1370
1371 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1372 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1373 struct htt_ppdu_stats *ppdu_stats, u8 user)
1374 {
1375 struct ath11k_base *ab = ar->ab;
1376 struct ath11k_peer *peer;
1377 struct ieee80211_sta *sta;
1378 struct ath11k_sta *arsta;
1379 struct htt_ppdu_stats_user_rate *user_rate;
1380 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1381 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1382 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1383 int ret;
1384 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1385 u32 succ_bytes = 0;
1386 u16 rate = 0, succ_pkts = 0;
1387 u32 tx_duration = 0;
1388 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1389 bool is_ampdu = false;
1390
1391 if (!usr_stats)
1392 return;
1393
1394 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1395 return;
1396
1397 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1398 is_ampdu =
1399 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1400
1401 if (usr_stats->tlv_flags &
1402 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1403 succ_bytes = usr_stats->ack_ba.success_bytes;
1404 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1405 usr_stats->ack_ba.info);
1406 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1407 usr_stats->ack_ba.info);
1408 }
1409
1410 if (common->fes_duration_us)
1411 tx_duration = common->fes_duration_us;
1412
1413 user_rate = &usr_stats->rate;
1414 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1415 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1416 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1417 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1418 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1419 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1420
1421 /* Note: If host configured fixed rates and in some other special
1422 * cases, the broadcast/management frames are sent in different rates.
1423 * Firmware rate's control to be skipped for this?
1424 */
1425
1426 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1427 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1428 return;
1429 }
1430
1431 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1432 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1433 return;
1434 }
1435
1436 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1437 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1438 mcs, nss);
1439 return;
1440 }
1441
1442 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1443 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1444 flags,
1445 &rate_idx,
1446 &rate);
1447 if (ret < 0)
1448 return;
1449 }
1450
1451 rcu_read_lock();
1452 spin_lock_bh(&ab->base_lock);
1453 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1454
1455 if (!peer || !peer->sta) {
1456 spin_unlock_bh(&ab->base_lock);
1457 rcu_read_unlock();
1458 return;
1459 }
1460
1461 sta = peer->sta;
1462 arsta = (struct ath11k_sta *)sta->drv_priv;
1463
1464 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1465
1466 switch (flags) {
1467 case WMI_RATE_PREAMBLE_OFDM:
1468 arsta->txrate.legacy = rate;
1469 break;
1470 case WMI_RATE_PREAMBLE_CCK:
1471 arsta->txrate.legacy = rate;
1472 break;
1473 case WMI_RATE_PREAMBLE_HT:
1474 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1475 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1476 if (sgi)
1477 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1478 break;
1479 case WMI_RATE_PREAMBLE_VHT:
1480 arsta->txrate.mcs = mcs;
1481 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1482 if (sgi)
1483 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1484 break;
1485 case WMI_RATE_PREAMBLE_HE:
1486 arsta->txrate.mcs = mcs;
1487 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1488 arsta->txrate.he_dcm = dcm;
1489 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1490 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1491 ((user_rate->ru_end -
1492 user_rate->ru_start) + 1);
1493 break;
1494 }
1495
1496 arsta->txrate.nss = nss;
1497
1498 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1499 arsta->tx_duration += tx_duration;
1500 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1501
1502 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1503 * So skip peer stats update for mgmt packets.
1504 */
1505 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1506 memset(peer_stats, 0, sizeof(*peer_stats));
1507 peer_stats->succ_pkts = succ_pkts;
1508 peer_stats->succ_bytes = succ_bytes;
1509 peer_stats->is_ampdu = is_ampdu;
1510 peer_stats->duration = tx_duration;
1511 peer_stats->ba_fails =
1512 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1513 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1514
1515 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1516 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1517 }
1518
1519 spin_unlock_bh(&ab->base_lock);
1520 rcu_read_unlock();
1521 }
1522
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1523 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1524 struct htt_ppdu_stats *ppdu_stats)
1525 {
1526 u8 user;
1527
1528 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1529 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1530 }
1531
1532 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1533 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1534 u32 ppdu_id)
1535 {
1536 struct htt_ppdu_stats_info *ppdu_info;
1537
1538 spin_lock_bh(&ar->data_lock);
1539 if (!list_empty(&ar->ppdu_stats_info)) {
1540 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1541 if (ppdu_info->ppdu_id == ppdu_id) {
1542 spin_unlock_bh(&ar->data_lock);
1543 return ppdu_info;
1544 }
1545 }
1546
1547 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1548 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1549 typeof(*ppdu_info), list);
1550 list_del(&ppdu_info->list);
1551 ar->ppdu_stat_list_depth--;
1552 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1553 kfree(ppdu_info);
1554 }
1555 }
1556 spin_unlock_bh(&ar->data_lock);
1557
1558 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1559 if (!ppdu_info)
1560 return NULL;
1561
1562 spin_lock_bh(&ar->data_lock);
1563 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1564 ar->ppdu_stat_list_depth++;
1565 spin_unlock_bh(&ar->data_lock);
1566
1567 return ppdu_info;
1568 }
1569
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1570 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1571 struct sk_buff *skb)
1572 {
1573 struct ath11k_htt_ppdu_stats_msg *msg;
1574 struct htt_ppdu_stats_info *ppdu_info;
1575 struct ath11k *ar;
1576 int ret;
1577 u8 pdev_id;
1578 u32 ppdu_id, len;
1579
1580 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1581 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1582 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1583 ppdu_id = msg->ppdu_id;
1584
1585 rcu_read_lock();
1586 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1587 if (!ar) {
1588 ret = -EINVAL;
1589 goto exit;
1590 }
1591
1592 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1593 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1594
1595 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1596 if (!ppdu_info) {
1597 ret = -EINVAL;
1598 goto exit;
1599 }
1600
1601 ppdu_info->ppdu_id = ppdu_id;
1602 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1603 ath11k_htt_tlv_ppdu_stats_parse,
1604 (void *)ppdu_info);
1605 if (ret) {
1606 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1607 goto exit;
1608 }
1609
1610 exit:
1611 rcu_read_unlock();
1612
1613 return ret;
1614 }
1615
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1616 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1617 {
1618 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1619 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1620 struct ath11k *ar;
1621 u8 pdev_id;
1622
1623 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1624
1625 rcu_read_lock();
1626
1627 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1628 if (!ar) {
1629 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1630 goto out;
1631 }
1632
1633 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1634 ar->ab->pktlog_defs_checksum);
1635
1636 out:
1637 rcu_read_unlock();
1638 }
1639
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1640 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1641 struct sk_buff *skb)
1642 {
1643 u32 *data = (u32 *)skb->data;
1644 u8 pdev_id, ring_type, ring_id, pdev_idx;
1645 u16 hp, tp;
1646 u32 backpressure_time;
1647 struct ath11k_bp_stats *bp_stats;
1648
1649 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1650 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1651 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1652 ++data;
1653
1654 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1655 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1656 ++data;
1657
1658 backpressure_time = *data;
1659
1660 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1661 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1662
1663 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1664 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1665 return;
1666
1667 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1668 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1669 pdev_idx = DP_HW2SW_MACID(pdev_id);
1670
1671 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1672 return;
1673
1674 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1675 } else {
1676 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1677 ring_type);
1678 return;
1679 }
1680
1681 spin_lock_bh(&ab->base_lock);
1682 bp_stats->hp = hp;
1683 bp_stats->tp = tp;
1684 bp_stats->count++;
1685 bp_stats->jiffies = jiffies;
1686 spin_unlock_bh(&ab->base_lock);
1687 }
1688
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1689 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1690 struct sk_buff *skb)
1691 {
1692 struct ath11k_dp *dp = &ab->dp;
1693 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1694 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1695 u16 peer_id;
1696 u8 vdev_id;
1697 u8 mac_addr[ETH_ALEN];
1698 u16 peer_mac_h16;
1699 u16 ast_hash;
1700 u16 hw_peer_id;
1701
1702 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1703
1704 switch (type) {
1705 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1706 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1707 resp->version_msg.version);
1708 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1709 resp->version_msg.version);
1710 complete(&dp->htt_tgt_version_received);
1711 break;
1712 case HTT_T2H_MSG_TYPE_PEER_MAP:
1713 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1714 resp->peer_map_ev.info);
1715 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1716 resp->peer_map_ev.info);
1717 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1718 resp->peer_map_ev.info1);
1719 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1720 peer_mac_h16, mac_addr);
1721 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1722 break;
1723 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1724 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1725 resp->peer_map_ev.info);
1726 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1727 resp->peer_map_ev.info);
1728 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1729 resp->peer_map_ev.info1);
1730 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1731 peer_mac_h16, mac_addr);
1732 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1733 resp->peer_map_ev.info2);
1734 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1735 resp->peer_map_ev.info1);
1736 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1737 hw_peer_id);
1738 break;
1739 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1740 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1741 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1742 resp->peer_unmap_ev.info);
1743 ath11k_peer_unmap_event(ab, peer_id);
1744 break;
1745 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1746 ath11k_htt_pull_ppdu_stats(ab, skb);
1747 break;
1748 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1749 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1750 break;
1751 case HTT_T2H_MSG_TYPE_PKTLOG:
1752 ath11k_htt_pktlog(ab, skb);
1753 break;
1754 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1755 ath11k_htt_backpressure_event_handler(ab, skb);
1756 break;
1757 default:
1758 ath11k_warn(ab, "htt event %d not handled\n", type);
1759 break;
1760 }
1761
1762 dev_kfree_skb_any(skb);
1763 }
1764
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1765 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1766 struct sk_buff_head *msdu_list,
1767 struct sk_buff *first, struct sk_buff *last,
1768 u8 l3pad_bytes, int msdu_len)
1769 {
1770 struct ath11k_base *ab = ar->ab;
1771 struct sk_buff *skb;
1772 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1773 int buf_first_hdr_len, buf_first_len;
1774 struct hal_rx_desc *ldesc;
1775 int space_extra, rem_len, buf_len;
1776 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1777
1778 /* As the msdu is spread across multiple rx buffers,
1779 * find the offset to the start of msdu for computing
1780 * the length of the msdu in the first buffer.
1781 */
1782 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1783 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1784
1785 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1786 skb_put(first, buf_first_hdr_len + msdu_len);
1787 skb_pull(first, buf_first_hdr_len);
1788 return 0;
1789 }
1790
1791 ldesc = (struct hal_rx_desc *)last->data;
1792 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1793 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1794
1795 /* MSDU spans over multiple buffers because the length of the MSDU
1796 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1797 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1798 */
1799 skb_put(first, DP_RX_BUFFER_SIZE);
1800 skb_pull(first, buf_first_hdr_len);
1801
1802 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1803 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1804 */
1805 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1806
1807 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1808 if (space_extra > 0 &&
1809 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1810 /* Free up all buffers of the MSDU */
1811 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1812 rxcb = ATH11K_SKB_RXCB(skb);
1813 if (!rxcb->is_continuation) {
1814 dev_kfree_skb_any(skb);
1815 break;
1816 }
1817 dev_kfree_skb_any(skb);
1818 }
1819 return -ENOMEM;
1820 }
1821
1822 rem_len = msdu_len - buf_first_len;
1823 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1824 rxcb = ATH11K_SKB_RXCB(skb);
1825 if (rxcb->is_continuation)
1826 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1827 else
1828 buf_len = rem_len;
1829
1830 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1831 WARN_ON_ONCE(1);
1832 dev_kfree_skb_any(skb);
1833 return -EINVAL;
1834 }
1835
1836 skb_put(skb, buf_len + hal_rx_desc_sz);
1837 skb_pull(skb, hal_rx_desc_sz);
1838 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1839 buf_len);
1840 dev_kfree_skb_any(skb);
1841
1842 rem_len -= buf_len;
1843 if (!rxcb->is_continuation)
1844 break;
1845 }
1846
1847 return 0;
1848 }
1849
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1850 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1851 struct sk_buff *first)
1852 {
1853 struct sk_buff *skb;
1854 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1855
1856 if (!rxcb->is_continuation)
1857 return first;
1858
1859 skb_queue_walk(msdu_list, skb) {
1860 rxcb = ATH11K_SKB_RXCB(skb);
1861 if (!rxcb->is_continuation)
1862 return skb;
1863 }
1864
1865 return NULL;
1866 }
1867
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1868 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1869 {
1870 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1871 struct rx_attention *rx_attention;
1872 bool ip_csum_fail, l4_csum_fail;
1873
1874 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1875 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1876 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1877
1878 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1879 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1880 }
1881
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1882 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1883 enum hal_encrypt_type enctype)
1884 {
1885 switch (enctype) {
1886 case HAL_ENCRYPT_TYPE_OPEN:
1887 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1888 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1889 return 0;
1890 case HAL_ENCRYPT_TYPE_CCMP_128:
1891 return IEEE80211_CCMP_MIC_LEN;
1892 case HAL_ENCRYPT_TYPE_CCMP_256:
1893 return IEEE80211_CCMP_256_MIC_LEN;
1894 case HAL_ENCRYPT_TYPE_GCMP_128:
1895 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1896 return IEEE80211_GCMP_MIC_LEN;
1897 case HAL_ENCRYPT_TYPE_WEP_40:
1898 case HAL_ENCRYPT_TYPE_WEP_104:
1899 case HAL_ENCRYPT_TYPE_WEP_128:
1900 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1901 case HAL_ENCRYPT_TYPE_WAPI:
1902 break;
1903 }
1904
1905 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1906 return 0;
1907 }
1908
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1909 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1910 enum hal_encrypt_type enctype)
1911 {
1912 switch (enctype) {
1913 case HAL_ENCRYPT_TYPE_OPEN:
1914 return 0;
1915 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1916 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1917 return IEEE80211_TKIP_IV_LEN;
1918 case HAL_ENCRYPT_TYPE_CCMP_128:
1919 return IEEE80211_CCMP_HDR_LEN;
1920 case HAL_ENCRYPT_TYPE_CCMP_256:
1921 return IEEE80211_CCMP_256_HDR_LEN;
1922 case HAL_ENCRYPT_TYPE_GCMP_128:
1923 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1924 return IEEE80211_GCMP_HDR_LEN;
1925 case HAL_ENCRYPT_TYPE_WEP_40:
1926 case HAL_ENCRYPT_TYPE_WEP_104:
1927 case HAL_ENCRYPT_TYPE_WEP_128:
1928 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1929 case HAL_ENCRYPT_TYPE_WAPI:
1930 break;
1931 }
1932
1933 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1934 return 0;
1935 }
1936
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1937 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1938 enum hal_encrypt_type enctype)
1939 {
1940 switch (enctype) {
1941 case HAL_ENCRYPT_TYPE_OPEN:
1942 case HAL_ENCRYPT_TYPE_CCMP_128:
1943 case HAL_ENCRYPT_TYPE_CCMP_256:
1944 case HAL_ENCRYPT_TYPE_GCMP_128:
1945 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1946 return 0;
1947 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1948 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1949 return IEEE80211_TKIP_ICV_LEN;
1950 case HAL_ENCRYPT_TYPE_WEP_40:
1951 case HAL_ENCRYPT_TYPE_WEP_104:
1952 case HAL_ENCRYPT_TYPE_WEP_128:
1953 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1954 case HAL_ENCRYPT_TYPE_WAPI:
1955 break;
1956 }
1957
1958 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1959 return 0;
1960 }
1961
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1962 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1963 struct sk_buff *msdu,
1964 u8 *first_hdr,
1965 enum hal_encrypt_type enctype,
1966 struct ieee80211_rx_status *status)
1967 {
1968 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1969 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1970 struct ieee80211_hdr *hdr;
1971 size_t hdr_len;
1972 u8 da[ETH_ALEN];
1973 u8 sa[ETH_ALEN];
1974 u16 qos_ctl = 0;
1975 u8 *qos;
1976
1977 /* copy SA & DA and pull decapped header */
1978 hdr = (struct ieee80211_hdr *)msdu->data;
1979 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1980 ether_addr_copy(da, ieee80211_get_DA(hdr));
1981 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1982 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1983
1984 if (rxcb->is_first_msdu) {
1985 /* original 802.11 header is valid for the first msdu
1986 * hence we can reuse the same header
1987 */
1988 hdr = (struct ieee80211_hdr *)first_hdr;
1989 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1990
1991 /* Each A-MSDU subframe will be reported as a separate MSDU,
1992 * so strip the A-MSDU bit from QoS Ctl.
1993 */
1994 if (ieee80211_is_data_qos(hdr->frame_control)) {
1995 qos = ieee80211_get_qos_ctl(hdr);
1996 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1997 }
1998 } else {
1999 /* Rebuild qos header if this is a middle/last msdu */
2000 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2001
2002 /* Reset the order bit as the HT_Control header is stripped */
2003 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2004
2005 qos_ctl = rxcb->tid;
2006
2007 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2008 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2009
2010 /* TODO Add other QoS ctl fields when required */
2011
2012 /* copy decap header before overwriting for reuse below */
2013 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2014 }
2015
2016 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2017 memcpy(skb_push(msdu,
2018 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2019 (void *)hdr + hdr_len,
2020 ath11k_dp_rx_crypto_param_len(ar, enctype));
2021 }
2022
2023 if (!rxcb->is_first_msdu) {
2024 memcpy(skb_push(msdu,
2025 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2026 IEEE80211_QOS_CTL_LEN);
2027 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2028 return;
2029 }
2030
2031 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2032
2033 /* original 802.11 header has a different DA and in
2034 * case of 4addr it may also have different SA
2035 */
2036 hdr = (struct ieee80211_hdr *)msdu->data;
2037 ether_addr_copy(ieee80211_get_DA(hdr), da);
2038 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2039 }
2040
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2041 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2042 enum hal_encrypt_type enctype,
2043 struct ieee80211_rx_status *status,
2044 bool decrypted)
2045 {
2046 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2047 struct ieee80211_hdr *hdr;
2048 size_t hdr_len;
2049 size_t crypto_len;
2050
2051 if (!rxcb->is_first_msdu ||
2052 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2053 WARN_ON_ONCE(1);
2054 return;
2055 }
2056
2057 skb_trim(msdu, msdu->len - FCS_LEN);
2058
2059 if (!decrypted)
2060 return;
2061
2062 hdr = (void *)msdu->data;
2063
2064 /* Tail */
2065 if (status->flag & RX_FLAG_IV_STRIPPED) {
2066 skb_trim(msdu, msdu->len -
2067 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2068
2069 skb_trim(msdu, msdu->len -
2070 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2071 } else {
2072 /* MIC */
2073 if (status->flag & RX_FLAG_MIC_STRIPPED)
2074 skb_trim(msdu, msdu->len -
2075 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2076
2077 /* ICV */
2078 if (status->flag & RX_FLAG_ICV_STRIPPED)
2079 skb_trim(msdu, msdu->len -
2080 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2081 }
2082
2083 /* MMIC */
2084 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2085 !ieee80211_has_morefrags(hdr->frame_control) &&
2086 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2087 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2088
2089 /* Head */
2090 if (status->flag & RX_FLAG_IV_STRIPPED) {
2091 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2092 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2093
2094 memmove((void *)msdu->data + crypto_len,
2095 (void *)msdu->data, hdr_len);
2096 skb_pull(msdu, crypto_len);
2097 }
2098 }
2099
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2100 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2101 struct sk_buff *msdu,
2102 enum hal_encrypt_type enctype)
2103 {
2104 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2105 struct ieee80211_hdr *hdr;
2106 size_t hdr_len, crypto_len;
2107 void *rfc1042;
2108 bool is_amsdu;
2109
2110 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2111 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2112 rfc1042 = hdr;
2113
2114 if (rxcb->is_first_msdu) {
2115 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2116 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2117
2118 rfc1042 += hdr_len + crypto_len;
2119 }
2120
2121 if (is_amsdu)
2122 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2123
2124 return rfc1042;
2125 }
2126
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2127 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2128 struct sk_buff *msdu,
2129 u8 *first_hdr,
2130 enum hal_encrypt_type enctype,
2131 struct ieee80211_rx_status *status)
2132 {
2133 struct ieee80211_hdr *hdr;
2134 struct ethhdr *eth;
2135 size_t hdr_len;
2136 u8 da[ETH_ALEN];
2137 u8 sa[ETH_ALEN];
2138 void *rfc1042;
2139
2140 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2141 if (WARN_ON_ONCE(!rfc1042))
2142 return;
2143
2144 /* pull decapped header and copy SA & DA */
2145 eth = (struct ethhdr *)msdu->data;
2146 ether_addr_copy(da, eth->h_dest);
2147 ether_addr_copy(sa, eth->h_source);
2148 skb_pull(msdu, sizeof(struct ethhdr));
2149
2150 /* push rfc1042/llc/snap */
2151 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2152 sizeof(struct ath11k_dp_rfc1042_hdr));
2153
2154 /* push original 802.11 header */
2155 hdr = (struct ieee80211_hdr *)first_hdr;
2156 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2157
2158 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2159 memcpy(skb_push(msdu,
2160 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2161 (void *)hdr + hdr_len,
2162 ath11k_dp_rx_crypto_param_len(ar, enctype));
2163 }
2164
2165 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2166
2167 /* original 802.11 header has a different DA and in
2168 * case of 4addr it may also have different SA
2169 */
2170 hdr = (struct ieee80211_hdr *)msdu->data;
2171 ether_addr_copy(ieee80211_get_DA(hdr), da);
2172 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2173 }
2174
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2175 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2176 struct hal_rx_desc *rx_desc,
2177 enum hal_encrypt_type enctype,
2178 struct ieee80211_rx_status *status,
2179 bool decrypted)
2180 {
2181 u8 *first_hdr;
2182 u8 decap;
2183 struct ethhdr *ehdr;
2184
2185 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2186 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2187
2188 switch (decap) {
2189 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2190 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2191 enctype, status);
2192 break;
2193 case DP_RX_DECAP_TYPE_RAW:
2194 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2195 decrypted);
2196 break;
2197 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2198 ehdr = (struct ethhdr *)msdu->data;
2199
2200 /* mac80211 allows fast path only for authorized STA */
2201 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2202 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2203 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2204 enctype, status);
2205 break;
2206 }
2207
2208 /* PN for mcast packets will be validated in mac80211;
2209 * remove eth header and add 802.11 header.
2210 */
2211 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2212 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2213 enctype, status);
2214 break;
2215 case DP_RX_DECAP_TYPE_8023:
2216 /* TODO: Handle undecap for these formats */
2217 break;
2218 }
2219 }
2220
2221 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2222 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2223 {
2224 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2225 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2226 struct ath11k_peer *peer = NULL;
2227
2228 lockdep_assert_held(&ab->base_lock);
2229
2230 if (rxcb->peer_id)
2231 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2232
2233 if (peer)
2234 return peer;
2235
2236 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2237 return NULL;
2238
2239 peer = ath11k_peer_find_by_addr(ab,
2240 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2241 return peer;
2242 }
2243
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2244 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2245 struct sk_buff *msdu,
2246 struct hal_rx_desc *rx_desc,
2247 struct ieee80211_rx_status *rx_status)
2248 {
2249 bool fill_crypto_hdr;
2250 enum hal_encrypt_type enctype;
2251 bool is_decrypted = false;
2252 struct ath11k_skb_rxcb *rxcb;
2253 struct ieee80211_hdr *hdr;
2254 struct ath11k_peer *peer;
2255 struct rx_attention *rx_attention;
2256 u32 err_bitmap;
2257
2258 /* PN for multicast packets will be checked in mac80211 */
2259 rxcb = ATH11K_SKB_RXCB(msdu);
2260 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2261 rxcb->is_mcbc = fill_crypto_hdr;
2262
2263 if (rxcb->is_mcbc) {
2264 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2265 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2266 }
2267
2268 spin_lock_bh(&ar->ab->base_lock);
2269 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2270 if (peer) {
2271 if (rxcb->is_mcbc)
2272 enctype = peer->sec_type_grp;
2273 else
2274 enctype = peer->sec_type;
2275 } else {
2276 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2277 }
2278 spin_unlock_bh(&ar->ab->base_lock);
2279
2280 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2281 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2282 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2283 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2284
2285 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2286 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2287 RX_FLAG_MMIC_ERROR |
2288 RX_FLAG_DECRYPTED |
2289 RX_FLAG_IV_STRIPPED |
2290 RX_FLAG_MMIC_STRIPPED);
2291
2292 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2293 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2294 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2295 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2296
2297 if (is_decrypted) {
2298 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2299
2300 if (fill_crypto_hdr)
2301 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2302 RX_FLAG_ICV_STRIPPED;
2303 else
2304 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2305 RX_FLAG_PN_VALIDATED;
2306 }
2307
2308 ath11k_dp_rx_h_csum_offload(ar, msdu);
2309 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2310 enctype, rx_status, is_decrypted);
2311
2312 if (!is_decrypted || fill_crypto_hdr)
2313 return;
2314
2315 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2316 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2317 hdr = (void *)msdu->data;
2318 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2319 }
2320 }
2321
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2322 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2323 struct ieee80211_rx_status *rx_status)
2324 {
2325 struct ieee80211_supported_band *sband;
2326 enum rx_msdu_start_pkt_type pkt_type;
2327 u8 bw;
2328 u8 rate_mcs, nss;
2329 u8 sgi;
2330 bool is_cck, is_ldpc;
2331
2332 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2333 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2334 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2335 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2336 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2337
2338 switch (pkt_type) {
2339 case RX_MSDU_START_PKT_TYPE_11A:
2340 case RX_MSDU_START_PKT_TYPE_11B:
2341 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2342 sband = &ar->mac.sbands[rx_status->band];
2343 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2344 is_cck);
2345 break;
2346 case RX_MSDU_START_PKT_TYPE_11N:
2347 rx_status->encoding = RX_ENC_HT;
2348 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2349 ath11k_warn(ar->ab,
2350 "Received with invalid mcs in HT mode %d\n",
2351 rate_mcs);
2352 break;
2353 }
2354 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2355 if (sgi)
2356 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2357 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2358 break;
2359 case RX_MSDU_START_PKT_TYPE_11AC:
2360 rx_status->encoding = RX_ENC_VHT;
2361 rx_status->rate_idx = rate_mcs;
2362 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2363 ath11k_warn(ar->ab,
2364 "Received with invalid mcs in VHT mode %d\n",
2365 rate_mcs);
2366 break;
2367 }
2368 rx_status->nss = nss;
2369 if (sgi)
2370 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2371 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2372 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2373 if (is_ldpc)
2374 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2375 break;
2376 case RX_MSDU_START_PKT_TYPE_11AX:
2377 rx_status->rate_idx = rate_mcs;
2378 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2379 ath11k_warn(ar->ab,
2380 "Received with invalid mcs in HE mode %d\n",
2381 rate_mcs);
2382 break;
2383 }
2384 rx_status->encoding = RX_ENC_HE;
2385 rx_status->nss = nss;
2386 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2387 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2388 break;
2389 }
2390 }
2391
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2392 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2393 struct ieee80211_rx_status *rx_status)
2394 {
2395 u8 channel_num;
2396 u32 center_freq, meta_data;
2397 struct ieee80211_channel *channel;
2398
2399 rx_status->freq = 0;
2400 rx_status->rate_idx = 0;
2401 rx_status->nss = 0;
2402 rx_status->encoding = RX_ENC_LEGACY;
2403 rx_status->bw = RATE_INFO_BW_20;
2404
2405 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2406
2407 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2408 channel_num = meta_data;
2409 center_freq = meta_data >> 16;
2410
2411 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2412 center_freq <= ATH11K_MAX_6G_FREQ) {
2413 rx_status->band = NL80211_BAND_6GHZ;
2414 rx_status->freq = center_freq;
2415 } else if (channel_num >= 1 && channel_num <= 14) {
2416 rx_status->band = NL80211_BAND_2GHZ;
2417 } else if (channel_num >= 36 && channel_num <= 173) {
2418 rx_status->band = NL80211_BAND_5GHZ;
2419 } else {
2420 spin_lock_bh(&ar->data_lock);
2421 channel = ar->rx_channel;
2422 if (channel) {
2423 rx_status->band = channel->band;
2424 channel_num =
2425 ieee80211_frequency_to_channel(channel->center_freq);
2426 }
2427 spin_unlock_bh(&ar->data_lock);
2428 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2429 rx_desc, sizeof(struct hal_rx_desc));
2430 }
2431
2432 if (rx_status->band != NL80211_BAND_6GHZ)
2433 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2434 rx_status->band);
2435
2436 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2437 }
2438
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2439 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2440 struct sk_buff *msdu,
2441 struct ieee80211_rx_status *status)
2442 {
2443 static const struct ieee80211_radiotap_he known = {
2444 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2445 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2446 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2447 };
2448 struct ieee80211_rx_status *rx_status;
2449 struct ieee80211_radiotap_he *he = NULL;
2450 struct ieee80211_sta *pubsta = NULL;
2451 struct ath11k_peer *peer;
2452 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2453 u8 decap = DP_RX_DECAP_TYPE_RAW;
2454 bool is_mcbc = rxcb->is_mcbc;
2455 bool is_eapol = rxcb->is_eapol;
2456
2457 if (status->encoding == RX_ENC_HE &&
2458 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2459 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2460 he = skb_push(msdu, sizeof(known));
2461 memcpy(he, &known, sizeof(known));
2462 status->flag |= RX_FLAG_RADIOTAP_HE;
2463 }
2464
2465 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2466 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2467
2468 spin_lock_bh(&ar->ab->base_lock);
2469 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2470 if (peer && peer->sta)
2471 pubsta = peer->sta;
2472 spin_unlock_bh(&ar->ab->base_lock);
2473
2474 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2475 "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2476 msdu,
2477 msdu->len,
2478 peer ? peer->addr : NULL,
2479 rxcb->tid,
2480 is_mcbc ? "mcast" : "ucast",
2481 rxcb->seq_no,
2482 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2483 (status->encoding == RX_ENC_HT) ? "ht" : "",
2484 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2485 (status->encoding == RX_ENC_HE) ? "he" : "",
2486 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2487 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2488 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2489 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2490 status->rate_idx,
2491 status->nss,
2492 status->freq,
2493 status->band, status->flag,
2494 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2495 !!(status->flag & RX_FLAG_MMIC_ERROR),
2496 !!(status->flag & RX_FLAG_AMSDU_MORE));
2497
2498 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2499 msdu->data, msdu->len);
2500
2501 rx_status = IEEE80211_SKB_RXCB(msdu);
2502 *rx_status = *status;
2503
2504 /* TODO: trace rx packet */
2505
2506 /* PN for multicast packets are not validate in HW,
2507 * so skip 802.3 rx path
2508 * Also, fast_rx expects the STA to be authorized, hence
2509 * eapol packets are sent in slow path.
2510 */
2511 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2512 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2513 rx_status->flag |= RX_FLAG_8023;
2514
2515 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2516 }
2517
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2518 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2519 struct sk_buff *msdu,
2520 struct sk_buff_head *msdu_list,
2521 struct ieee80211_rx_status *rx_status)
2522 {
2523 struct ath11k_base *ab = ar->ab;
2524 struct hal_rx_desc *rx_desc, *lrx_desc;
2525 struct rx_attention *rx_attention;
2526 struct ath11k_skb_rxcb *rxcb;
2527 struct sk_buff *last_buf;
2528 u8 l3_pad_bytes;
2529 u8 *hdr_status;
2530 u16 msdu_len;
2531 int ret;
2532 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2533
2534 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2535 if (!last_buf) {
2536 ath11k_warn(ab,
2537 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2538 ret = -EIO;
2539 goto free_out;
2540 }
2541
2542 rx_desc = (struct hal_rx_desc *)msdu->data;
2543 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2544 ath11k_warn(ar->ab, "msdu len not valid\n");
2545 ret = -EIO;
2546 goto free_out;
2547 }
2548
2549 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2550 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2551 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2552 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2553 ret = -EIO;
2554 goto free_out;
2555 }
2556
2557 rxcb = ATH11K_SKB_RXCB(msdu);
2558 rxcb->rx_desc = rx_desc;
2559 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2560 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2561
2562 if (rxcb->is_frag) {
2563 skb_pull(msdu, hal_rx_desc_sz);
2564 } else if (!rxcb->is_continuation) {
2565 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2566 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2567 ret = -EINVAL;
2568 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2569 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2570 sizeof(struct ieee80211_hdr));
2571 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2572 sizeof(struct hal_rx_desc));
2573 goto free_out;
2574 }
2575 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2576 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2577 } else {
2578 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2579 msdu, last_buf,
2580 l3_pad_bytes, msdu_len);
2581 if (ret) {
2582 ath11k_warn(ab,
2583 "failed to coalesce msdu rx buffer%d\n", ret);
2584 goto free_out;
2585 }
2586 }
2587
2588 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2589 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2590
2591 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2592
2593 return 0;
2594
2595 free_out:
2596 return ret;
2597 }
2598
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2599 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2600 struct napi_struct *napi,
2601 struct sk_buff_head *msdu_list,
2602 int mac_id)
2603 {
2604 struct sk_buff *msdu;
2605 struct ath11k *ar;
2606 struct ieee80211_rx_status rx_status = {0};
2607 int ret;
2608
2609 if (skb_queue_empty(msdu_list))
2610 return;
2611
2612 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2613 __skb_queue_purge(msdu_list);
2614 return;
2615 }
2616
2617 ar = ab->pdevs[mac_id].ar;
2618 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2619 __skb_queue_purge(msdu_list);
2620 return;
2621 }
2622
2623 while ((msdu = __skb_dequeue(msdu_list))) {
2624 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2625 if (unlikely(ret)) {
2626 ath11k_dbg(ab, ATH11K_DBG_DATA,
2627 "Unable to process msdu %d", ret);
2628 dev_kfree_skb_any(msdu);
2629 continue;
2630 }
2631
2632 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2633 }
2634 }
2635
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2636 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2637 struct napi_struct *napi, int budget)
2638 {
2639 struct ath11k_dp *dp = &ab->dp;
2640 struct dp_rxdma_ring *rx_ring;
2641 int num_buffs_reaped[MAX_RADIOS] = {0};
2642 struct sk_buff_head msdu_list[MAX_RADIOS];
2643 struct ath11k_skb_rxcb *rxcb;
2644 int total_msdu_reaped = 0;
2645 struct hal_srng *srng;
2646 struct sk_buff *msdu;
2647 bool done = false;
2648 int buf_id, mac_id;
2649 struct ath11k *ar;
2650 struct hal_reo_dest_ring *desc;
2651 enum hal_reo_dest_ring_push_reason push_reason;
2652 u32 cookie;
2653 int i;
2654
2655 for (i = 0; i < MAX_RADIOS; i++)
2656 __skb_queue_head_init(&msdu_list[i]);
2657
2658 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2659
2660 spin_lock_bh(&srng->lock);
2661
2662 try_again:
2663 ath11k_hal_srng_access_begin(ab, srng);
2664
2665 while (likely(desc =
2666 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2667 srng))) {
2668 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2669 desc->buf_addr_info.info1);
2670 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2671 cookie);
2672 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2673
2674 if (unlikely(buf_id == 0))
2675 continue;
2676
2677 ar = ab->pdevs[mac_id].ar;
2678 rx_ring = &ar->dp.rx_refill_buf_ring;
2679 spin_lock_bh(&rx_ring->idr_lock);
2680 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2681 if (unlikely(!msdu)) {
2682 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2683 buf_id);
2684 spin_unlock_bh(&rx_ring->idr_lock);
2685 continue;
2686 }
2687
2688 idr_remove(&rx_ring->bufs_idr, buf_id);
2689 spin_unlock_bh(&rx_ring->idr_lock);
2690
2691 rxcb = ATH11K_SKB_RXCB(msdu);
2692 dma_unmap_single(ab->dev, rxcb->paddr,
2693 msdu->len + skb_tailroom(msdu),
2694 DMA_FROM_DEVICE);
2695
2696 num_buffs_reaped[mac_id]++;
2697
2698 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2699 desc->info0);
2700 if (unlikely(push_reason !=
2701 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2702 dev_kfree_skb_any(msdu);
2703 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2704 continue;
2705 }
2706
2707 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2708 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2709 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2710 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2711 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2712 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2713 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2714 desc->rx_mpdu_info.meta_data);
2715 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2716 desc->rx_mpdu_info.info0);
2717 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2718 desc->info0);
2719
2720 rxcb->mac_id = mac_id;
2721 __skb_queue_tail(&msdu_list[mac_id], msdu);
2722
2723 if (rxcb->is_continuation) {
2724 done = false;
2725 } else {
2726 total_msdu_reaped++;
2727 done = true;
2728 }
2729
2730 if (total_msdu_reaped >= budget)
2731 break;
2732 }
2733
2734 /* Hw might have updated the head pointer after we cached it.
2735 * In this case, even though there are entries in the ring we'll
2736 * get rx_desc NULL. Give the read another try with updated cached
2737 * head pointer so that we can reap complete MPDU in the current
2738 * rx processing.
2739 */
2740 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2741 ath11k_hal_srng_access_end(ab, srng);
2742 goto try_again;
2743 }
2744
2745 ath11k_hal_srng_access_end(ab, srng);
2746
2747 spin_unlock_bh(&srng->lock);
2748
2749 if (unlikely(!total_msdu_reaped))
2750 goto exit;
2751
2752 for (i = 0; i < ab->num_radios; i++) {
2753 if (!num_buffs_reaped[i])
2754 continue;
2755
2756 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2757
2758 ar = ab->pdevs[i].ar;
2759 rx_ring = &ar->dp.rx_refill_buf_ring;
2760
2761 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2762 ab->hw_params.hal_params->rx_buf_rbm);
2763 }
2764 exit:
2765 return total_msdu_reaped;
2766 }
2767
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2768 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2769 struct hal_rx_mon_ppdu_info *ppdu_info)
2770 {
2771 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2772 u32 num_msdu;
2773 int i;
2774
2775 if (!rx_stats)
2776 return;
2777
2778 arsta->rssi_comb = ppdu_info->rssi_comb;
2779 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2780
2781 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2782 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2783
2784 rx_stats->num_msdu += num_msdu;
2785 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2786 ppdu_info->tcp_ack_msdu_count;
2787 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2788 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2789
2790 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2791 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2792 ppdu_info->nss = 1;
2793 ppdu_info->mcs = HAL_RX_MAX_MCS;
2794 ppdu_info->tid = IEEE80211_NUM_TIDS;
2795 }
2796
2797 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2798 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2799
2800 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2801 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2802
2803 if (ppdu_info->gi < HAL_RX_GI_MAX)
2804 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2805
2806 if (ppdu_info->bw < HAL_RX_BW_MAX)
2807 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2808
2809 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2810 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2811
2812 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2813 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2814
2815 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2816 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2817
2818 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2819 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2820
2821 if (ppdu_info->is_stbc)
2822 rx_stats->stbc_count += num_msdu;
2823
2824 if (ppdu_info->beamformed)
2825 rx_stats->beamformed_count += num_msdu;
2826
2827 if (ppdu_info->num_mpdu_fcs_ok > 1)
2828 rx_stats->ampdu_msdu_count += num_msdu;
2829 else
2830 rx_stats->non_ampdu_msdu_count += num_msdu;
2831
2832 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2833 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2834 rx_stats->dcm_count += ppdu_info->dcm;
2835 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2836
2837 arsta->rssi_comb = ppdu_info->rssi_comb;
2838
2839 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2840 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2841
2842 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2843 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2844
2845 rx_stats->rx_duration += ppdu_info->rx_duration;
2846 arsta->rx_duration = rx_stats->rx_duration;
2847 }
2848
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2849 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2850 struct dp_rxdma_ring *rx_ring,
2851 int *buf_id)
2852 {
2853 struct sk_buff *skb;
2854 dma_addr_t paddr;
2855
2856 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2857 DP_RX_BUFFER_ALIGN_SIZE);
2858
2859 if (!skb)
2860 goto fail_alloc_skb;
2861
2862 if (!IS_ALIGNED((unsigned long)skb->data,
2863 DP_RX_BUFFER_ALIGN_SIZE)) {
2864 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2865 skb->data);
2866 }
2867
2868 paddr = dma_map_single(ab->dev, skb->data,
2869 skb->len + skb_tailroom(skb),
2870 DMA_FROM_DEVICE);
2871 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2872 goto fail_free_skb;
2873
2874 spin_lock_bh(&rx_ring->idr_lock);
2875 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2876 rx_ring->bufs_max, GFP_ATOMIC);
2877 spin_unlock_bh(&rx_ring->idr_lock);
2878 if (*buf_id < 0)
2879 goto fail_dma_unmap;
2880
2881 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2882 return skb;
2883
2884 fail_dma_unmap:
2885 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2886 DMA_FROM_DEVICE);
2887 fail_free_skb:
2888 dev_kfree_skb_any(skb);
2889 fail_alloc_skb:
2890 return NULL;
2891 }
2892
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2893 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2894 struct dp_rxdma_ring *rx_ring,
2895 int req_entries,
2896 enum hal_rx_buf_return_buf_manager mgr)
2897 {
2898 struct hal_srng *srng;
2899 u32 *desc;
2900 struct sk_buff *skb;
2901 int num_free;
2902 int num_remain;
2903 int buf_id;
2904 u32 cookie;
2905 dma_addr_t paddr;
2906
2907 req_entries = min(req_entries, rx_ring->bufs_max);
2908
2909 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2910
2911 spin_lock_bh(&srng->lock);
2912
2913 ath11k_hal_srng_access_begin(ab, srng);
2914
2915 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2916
2917 req_entries = min(num_free, req_entries);
2918 num_remain = req_entries;
2919
2920 while (num_remain > 0) {
2921 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2922 &buf_id);
2923 if (!skb)
2924 break;
2925 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2926
2927 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2928 if (!desc)
2929 goto fail_desc_get;
2930
2931 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2932 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2933
2934 num_remain--;
2935
2936 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2937 }
2938
2939 ath11k_hal_srng_access_end(ab, srng);
2940
2941 spin_unlock_bh(&srng->lock);
2942
2943 return req_entries - num_remain;
2944
2945 fail_desc_get:
2946 spin_lock_bh(&rx_ring->idr_lock);
2947 idr_remove(&rx_ring->bufs_idr, buf_id);
2948 spin_unlock_bh(&rx_ring->idr_lock);
2949 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2950 DMA_FROM_DEVICE);
2951 dev_kfree_skb_any(skb);
2952 ath11k_hal_srng_access_end(ab, srng);
2953 spin_unlock_bh(&srng->lock);
2954
2955 return req_entries - num_remain;
2956 }
2957
2958 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2959
2960 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2961 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2962 struct hal_tlv_hdr *tlv)
2963 {
2964 struct hal_rx_ppdu_start *ppdu_start;
2965 u16 ppdu_id_diff, ppdu_id, tlv_len;
2966 u8 *ptr;
2967
2968 /* PPDU id is part of second tlv, move ptr to second tlv */
2969 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2970 ptr = (u8 *)tlv;
2971 ptr += sizeof(*tlv) + tlv_len;
2972 tlv = (struct hal_tlv_hdr *)ptr;
2973
2974 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2975 return;
2976
2977 ptr += sizeof(*tlv);
2978 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2979 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2980 __le32_to_cpu(ppdu_start->info0));
2981
2982 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2983 pmon->buf_state = DP_MON_STATUS_LEAD;
2984 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2985 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2986 pmon->buf_state = DP_MON_STATUS_LAG;
2987 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2988 pmon->buf_state = DP_MON_STATUS_LAG;
2989 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2990 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2991 pmon->buf_state = DP_MON_STATUS_LEAD;
2992 }
2993 }
2994
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2995 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2996 int *budget, struct sk_buff_head *skb_list)
2997 {
2998 struct ath11k *ar;
2999 const struct ath11k_hw_hal_params *hal_params;
3000 struct ath11k_pdev_dp *dp;
3001 struct dp_rxdma_ring *rx_ring;
3002 struct ath11k_mon_data *pmon;
3003 struct hal_srng *srng;
3004 void *rx_mon_status_desc;
3005 struct sk_buff *skb;
3006 struct ath11k_skb_rxcb *rxcb;
3007 struct hal_tlv_hdr *tlv;
3008 u32 cookie;
3009 int buf_id, srng_id;
3010 dma_addr_t paddr;
3011 u8 rbm;
3012 int num_buffs_reaped = 0;
3013
3014 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3015 dp = &ar->dp;
3016 pmon = &dp->mon_data;
3017 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3018 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3019
3020 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3021
3022 spin_lock_bh(&srng->lock);
3023
3024 ath11k_hal_srng_access_begin(ab, srng);
3025 while (*budget) {
3026 *budget -= 1;
3027 rx_mon_status_desc =
3028 ath11k_hal_srng_src_peek(ab, srng);
3029 if (!rx_mon_status_desc) {
3030 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3031 break;
3032 }
3033
3034 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3035 &cookie, &rbm);
3036 if (paddr) {
3037 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3038
3039 spin_lock_bh(&rx_ring->idr_lock);
3040 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3041 if (!skb) {
3042 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3043 buf_id);
3044 spin_unlock_bh(&rx_ring->idr_lock);
3045 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3046 goto move_next;
3047 }
3048
3049 idr_remove(&rx_ring->bufs_idr, buf_id);
3050 spin_unlock_bh(&rx_ring->idr_lock);
3051
3052 rxcb = ATH11K_SKB_RXCB(skb);
3053
3054 dma_unmap_single(ab->dev, rxcb->paddr,
3055 skb->len + skb_tailroom(skb),
3056 DMA_FROM_DEVICE);
3057
3058 tlv = (struct hal_tlv_hdr *)skb->data;
3059 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3060 HAL_RX_STATUS_BUFFER_DONE) {
3061 ath11k_warn(ab, "mon status DONE not set %lx\n",
3062 FIELD_GET(HAL_TLV_HDR_TAG,
3063 tlv->tl));
3064 dev_kfree_skb_any(skb);
3065 pmon->buf_state = DP_MON_STATUS_NO_DMA;
3066 goto move_next;
3067 }
3068
3069 if (ab->hw_params.full_monitor_mode) {
3070 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3071 if (paddr == pmon->mon_status_paddr)
3072 pmon->buf_state = DP_MON_STATUS_MATCH;
3073 }
3074 __skb_queue_tail(skb_list, skb);
3075 } else {
3076 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3077 }
3078 move_next:
3079 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3080 &buf_id);
3081
3082 if (!skb) {
3083 hal_params = ab->hw_params.hal_params;
3084 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3085 hal_params->rx_buf_rbm);
3086 num_buffs_reaped++;
3087 break;
3088 }
3089 rxcb = ATH11K_SKB_RXCB(skb);
3090
3091 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3092 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3093
3094 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3095 cookie,
3096 ab->hw_params.hal_params->rx_buf_rbm);
3097 ath11k_hal_srng_src_get_next_entry(ab, srng);
3098 num_buffs_reaped++;
3099 }
3100 ath11k_hal_srng_access_end(ab, srng);
3101 spin_unlock_bh(&srng->lock);
3102
3103 return num_buffs_reaped;
3104 }
3105
ath11k_dp_rx_frag_timer(struct timer_list * timer)3106 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3107 {
3108 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3109
3110 spin_lock_bh(&rx_tid->ab->base_lock);
3111 if (rx_tid->last_frag_no &&
3112 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3113 spin_unlock_bh(&rx_tid->ab->base_lock);
3114 return;
3115 }
3116 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3117 spin_unlock_bh(&rx_tid->ab->base_lock);
3118 }
3119
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3120 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3121 {
3122 struct ath11k_base *ab = ar->ab;
3123 struct crypto_shash *tfm;
3124 struct ath11k_peer *peer;
3125 struct dp_rx_tid *rx_tid;
3126 int i;
3127
3128 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3129 if (IS_ERR(tfm))
3130 return PTR_ERR(tfm);
3131
3132 spin_lock_bh(&ab->base_lock);
3133
3134 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3135 if (!peer) {
3136 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3137 spin_unlock_bh(&ab->base_lock);
3138 crypto_free_shash(tfm);
3139 return -ENOENT;
3140 }
3141
3142 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3143 rx_tid = &peer->rx_tid[i];
3144 rx_tid->ab = ab;
3145 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3146 skb_queue_head_init(&rx_tid->rx_frags);
3147 }
3148
3149 peer->tfm_mmic = tfm;
3150 peer->dp_setup_done = true;
3151 spin_unlock_bh(&ab->base_lock);
3152
3153 return 0;
3154 }
3155
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3156 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3157 struct ieee80211_hdr *hdr, u8 *data,
3158 size_t data_len, u8 *mic)
3159 {
3160 SHASH_DESC_ON_STACK(desc, tfm);
3161 u8 mic_hdr[16] = {0};
3162 u8 tid = 0;
3163 int ret;
3164
3165 if (!tfm)
3166 return -EINVAL;
3167
3168 desc->tfm = tfm;
3169
3170 ret = crypto_shash_setkey(tfm, key, 8);
3171 if (ret)
3172 goto out;
3173
3174 ret = crypto_shash_init(desc);
3175 if (ret)
3176 goto out;
3177
3178 /* TKIP MIC header */
3179 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3180 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3181 if (ieee80211_is_data_qos(hdr->frame_control))
3182 tid = ieee80211_get_tid(hdr);
3183 mic_hdr[12] = tid;
3184
3185 ret = crypto_shash_update(desc, mic_hdr, 16);
3186 if (ret)
3187 goto out;
3188 ret = crypto_shash_update(desc, data, data_len);
3189 if (ret)
3190 goto out;
3191 ret = crypto_shash_final(desc, mic);
3192 out:
3193 shash_desc_zero(desc);
3194 return ret;
3195 }
3196
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3197 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3198 struct sk_buff *msdu)
3199 {
3200 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3201 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3202 struct ieee80211_key_conf *key_conf;
3203 struct ieee80211_hdr *hdr;
3204 u8 mic[IEEE80211_CCMP_MIC_LEN];
3205 int head_len, tail_len, ret;
3206 size_t data_len;
3207 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3208 u8 *key, *data;
3209 u8 key_idx;
3210
3211 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3212 HAL_ENCRYPT_TYPE_TKIP_MIC)
3213 return 0;
3214
3215 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3216 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3217 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3218 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3219
3220 if (!is_multicast_ether_addr(hdr->addr1))
3221 key_idx = peer->ucast_keyidx;
3222 else
3223 key_idx = peer->mcast_keyidx;
3224
3225 key_conf = peer->keys[key_idx];
3226
3227 data = msdu->data + head_len;
3228 data_len = msdu->len - head_len - tail_len;
3229 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3230
3231 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3232 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3233 goto mic_fail;
3234
3235 return 0;
3236
3237 mic_fail:
3238 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3239 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3240
3241 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3242 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3243 skb_pull(msdu, hal_rx_desc_sz);
3244
3245 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3246 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3247 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3248 ieee80211_rx(ar->hw, msdu);
3249 return -EINVAL;
3250 }
3251
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3252 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3253 enum hal_encrypt_type enctype, u32 flags)
3254 {
3255 struct ieee80211_hdr *hdr;
3256 size_t hdr_len;
3257 size_t crypto_len;
3258 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3259
3260 if (!flags)
3261 return;
3262
3263 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3264
3265 if (flags & RX_FLAG_MIC_STRIPPED)
3266 skb_trim(msdu, msdu->len -
3267 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3268
3269 if (flags & RX_FLAG_ICV_STRIPPED)
3270 skb_trim(msdu, msdu->len -
3271 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3272
3273 if (flags & RX_FLAG_IV_STRIPPED) {
3274 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3275 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3276
3277 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3278 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3279 skb_pull(msdu, crypto_len);
3280 }
3281 }
3282
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3283 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3284 struct ath11k_peer *peer,
3285 struct dp_rx_tid *rx_tid,
3286 struct sk_buff **defrag_skb)
3287 {
3288 struct hal_rx_desc *rx_desc;
3289 struct sk_buff *skb, *first_frag, *last_frag;
3290 struct ieee80211_hdr *hdr;
3291 struct rx_attention *rx_attention;
3292 enum hal_encrypt_type enctype;
3293 bool is_decrypted = false;
3294 int msdu_len = 0;
3295 int extra_space;
3296 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3297
3298 first_frag = skb_peek(&rx_tid->rx_frags);
3299 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3300
3301 skb_queue_walk(&rx_tid->rx_frags, skb) {
3302 flags = 0;
3303 rx_desc = (struct hal_rx_desc *)skb->data;
3304 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3305
3306 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3307 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3308 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3309 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3310 }
3311
3312 if (is_decrypted) {
3313 if (skb != first_frag)
3314 flags |= RX_FLAG_IV_STRIPPED;
3315 if (skb != last_frag)
3316 flags |= RX_FLAG_ICV_STRIPPED |
3317 RX_FLAG_MIC_STRIPPED;
3318 }
3319
3320 /* RX fragments are always raw packets */
3321 if (skb != last_frag)
3322 skb_trim(skb, skb->len - FCS_LEN);
3323 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3324
3325 if (skb != first_frag)
3326 skb_pull(skb, hal_rx_desc_sz +
3327 ieee80211_hdrlen(hdr->frame_control));
3328 msdu_len += skb->len;
3329 }
3330
3331 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3332 if (extra_space > 0 &&
3333 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3334 return -ENOMEM;
3335
3336 __skb_unlink(first_frag, &rx_tid->rx_frags);
3337 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3338 skb_put_data(first_frag, skb->data, skb->len);
3339 dev_kfree_skb_any(skb);
3340 }
3341
3342 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3343 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3344 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3345
3346 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3347 first_frag = NULL;
3348
3349 *defrag_skb = first_frag;
3350 return 0;
3351 }
3352
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3353 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3354 struct sk_buff *defrag_skb)
3355 {
3356 struct ath11k_base *ab = ar->ab;
3357 struct ath11k_pdev_dp *dp = &ar->dp;
3358 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3359 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3360 struct hal_reo_entrance_ring *reo_ent_ring;
3361 struct hal_reo_dest_ring *reo_dest_ring;
3362 struct dp_link_desc_bank *link_desc_banks;
3363 struct hal_rx_msdu_link *msdu_link;
3364 struct hal_rx_msdu_details *msdu0;
3365 struct hal_srng *srng;
3366 dma_addr_t paddr;
3367 u32 desc_bank, msdu_info, mpdu_info;
3368 u32 dst_idx, cookie, hal_rx_desc_sz;
3369 int ret, buf_id;
3370
3371 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3372 link_desc_banks = ab->dp.link_desc_banks;
3373 reo_dest_ring = rx_tid->dst_ring_desc;
3374
3375 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3376 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3377 (paddr - link_desc_banks[desc_bank].paddr));
3378 msdu0 = &msdu_link->msdu_link[0];
3379 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3380 memset(msdu0, 0, sizeof(*msdu0));
3381
3382 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3383 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3384 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3385 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3386 defrag_skb->len - hal_rx_desc_sz) |
3387 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3388 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3389 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3390 msdu0->rx_msdu_info.info0 = msdu_info;
3391
3392 /* change msdu len in hal rx desc */
3393 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3394
3395 paddr = dma_map_single(ab->dev, defrag_skb->data,
3396 defrag_skb->len + skb_tailroom(defrag_skb),
3397 DMA_TO_DEVICE);
3398 if (dma_mapping_error(ab->dev, paddr))
3399 return -ENOMEM;
3400
3401 spin_lock_bh(&rx_refill_ring->idr_lock);
3402 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3403 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3404 spin_unlock_bh(&rx_refill_ring->idr_lock);
3405 if (buf_id < 0) {
3406 ret = -ENOMEM;
3407 goto err_unmap_dma;
3408 }
3409
3410 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3411 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3412 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3413
3414 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3415 ab->hw_params.hal_params->rx_buf_rbm);
3416
3417 /* Fill mpdu details into reo entrace ring */
3418 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3419
3420 spin_lock_bh(&srng->lock);
3421 ath11k_hal_srng_access_begin(ab, srng);
3422
3423 reo_ent_ring = (struct hal_reo_entrance_ring *)
3424 ath11k_hal_srng_src_get_next_entry(ab, srng);
3425 if (!reo_ent_ring) {
3426 ath11k_hal_srng_access_end(ab, srng);
3427 spin_unlock_bh(&srng->lock);
3428 ret = -ENOSPC;
3429 goto err_free_idr;
3430 }
3431 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3432
3433 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3434 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3435 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3436
3437 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3438 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3439 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3440 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3441 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3442 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3443 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3444
3445 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3446 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3447 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3448 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3449 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3450 reo_dest_ring->info0)) |
3451 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3452 ath11k_hal_srng_access_end(ab, srng);
3453 spin_unlock_bh(&srng->lock);
3454
3455 return 0;
3456
3457 err_free_idr:
3458 spin_lock_bh(&rx_refill_ring->idr_lock);
3459 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3460 spin_unlock_bh(&rx_refill_ring->idr_lock);
3461 err_unmap_dma:
3462 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3463 DMA_TO_DEVICE);
3464 return ret;
3465 }
3466
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3467 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3468 struct sk_buff *a, struct sk_buff *b)
3469 {
3470 int frag1, frag2;
3471
3472 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3473 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3474
3475 return frag1 - frag2;
3476 }
3477
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3478 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3479 struct sk_buff_head *frag_list,
3480 struct sk_buff *cur_frag)
3481 {
3482 struct sk_buff *skb;
3483 int cmp;
3484
3485 skb_queue_walk(frag_list, skb) {
3486 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3487 if (cmp < 0)
3488 continue;
3489 __skb_queue_before(frag_list, skb, cur_frag);
3490 return;
3491 }
3492 __skb_queue_tail(frag_list, cur_frag);
3493 }
3494
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3495 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3496 {
3497 struct ieee80211_hdr *hdr;
3498 u64 pn = 0;
3499 u8 *ehdr;
3500 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3501
3502 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3503 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3504
3505 pn = ehdr[0];
3506 pn |= (u64)ehdr[1] << 8;
3507 pn |= (u64)ehdr[4] << 16;
3508 pn |= (u64)ehdr[5] << 24;
3509 pn |= (u64)ehdr[6] << 32;
3510 pn |= (u64)ehdr[7] << 40;
3511
3512 return pn;
3513 }
3514
3515 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3516 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3517 {
3518 enum hal_encrypt_type encrypt_type;
3519 struct sk_buff *first_frag, *skb;
3520 struct hal_rx_desc *desc;
3521 u64 last_pn;
3522 u64 cur_pn;
3523
3524 first_frag = skb_peek(&rx_tid->rx_frags);
3525 desc = (struct hal_rx_desc *)first_frag->data;
3526
3527 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3528 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3529 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3530 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3531 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3532 return true;
3533
3534 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3535 skb_queue_walk(&rx_tid->rx_frags, skb) {
3536 if (skb == first_frag)
3537 continue;
3538
3539 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3540 if (cur_pn != last_pn + 1)
3541 return false;
3542 last_pn = cur_pn;
3543 }
3544 return true;
3545 }
3546
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3547 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3548 struct sk_buff *msdu,
3549 u32 *ring_desc)
3550 {
3551 struct ath11k_base *ab = ar->ab;
3552 struct hal_rx_desc *rx_desc;
3553 struct ath11k_peer *peer;
3554 struct dp_rx_tid *rx_tid;
3555 struct sk_buff *defrag_skb = NULL;
3556 u32 peer_id;
3557 u16 seqno, frag_no;
3558 u8 tid;
3559 int ret = 0;
3560 bool more_frags;
3561 bool is_mcbc;
3562
3563 rx_desc = (struct hal_rx_desc *)msdu->data;
3564 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3565 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3566 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3567 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3568 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3569 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3570
3571 /* Multicast/Broadcast fragments are not expected */
3572 if (is_mcbc)
3573 return -EINVAL;
3574
3575 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3576 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3577 tid > IEEE80211_NUM_TIDS)
3578 return -EINVAL;
3579
3580 /* received unfragmented packet in reo
3581 * exception ring, this shouldn't happen
3582 * as these packets typically come from
3583 * reo2sw srngs.
3584 */
3585 if (WARN_ON_ONCE(!frag_no && !more_frags))
3586 return -EINVAL;
3587
3588 spin_lock_bh(&ab->base_lock);
3589 peer = ath11k_peer_find_by_id(ab, peer_id);
3590 if (!peer) {
3591 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3592 peer_id);
3593 ret = -ENOENT;
3594 goto out_unlock;
3595 }
3596 if (!peer->dp_setup_done) {
3597 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3598 peer->addr, peer_id);
3599 ret = -ENOENT;
3600 goto out_unlock;
3601 }
3602
3603 rx_tid = &peer->rx_tid[tid];
3604
3605 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3606 skb_queue_empty(&rx_tid->rx_frags)) {
3607 /* Flush stored fragments and start a new sequence */
3608 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3609 rx_tid->cur_sn = seqno;
3610 }
3611
3612 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3613 /* Fragment already present */
3614 ret = -EINVAL;
3615 goto out_unlock;
3616 }
3617
3618 if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3619 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3620 else
3621 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3622
3623 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3624 if (!more_frags)
3625 rx_tid->last_frag_no = frag_no;
3626
3627 if (frag_no == 0) {
3628 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3629 sizeof(*rx_tid->dst_ring_desc),
3630 GFP_ATOMIC);
3631 if (!rx_tid->dst_ring_desc) {
3632 ret = -ENOMEM;
3633 goto out_unlock;
3634 }
3635 } else {
3636 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3637 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3638 }
3639
3640 if (!rx_tid->last_frag_no ||
3641 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3642 mod_timer(&rx_tid->frag_timer, jiffies +
3643 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3644 goto out_unlock;
3645 }
3646
3647 spin_unlock_bh(&ab->base_lock);
3648 del_timer_sync(&rx_tid->frag_timer);
3649 spin_lock_bh(&ab->base_lock);
3650
3651 peer = ath11k_peer_find_by_id(ab, peer_id);
3652 if (!peer)
3653 goto err_frags_cleanup;
3654
3655 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3656 goto err_frags_cleanup;
3657
3658 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3659 goto err_frags_cleanup;
3660
3661 if (!defrag_skb)
3662 goto err_frags_cleanup;
3663
3664 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3665 goto err_frags_cleanup;
3666
3667 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3668 goto out_unlock;
3669
3670 err_frags_cleanup:
3671 dev_kfree_skb_any(defrag_skb);
3672 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3673 out_unlock:
3674 spin_unlock_bh(&ab->base_lock);
3675 return ret;
3676 }
3677
3678 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3679 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3680 {
3681 struct ath11k_pdev_dp *dp = &ar->dp;
3682 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3683 struct sk_buff *msdu;
3684 struct ath11k_skb_rxcb *rxcb;
3685 struct hal_rx_desc *rx_desc;
3686 u8 *hdr_status;
3687 u16 msdu_len;
3688 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3689
3690 spin_lock_bh(&rx_ring->idr_lock);
3691 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3692 if (!msdu) {
3693 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3694 buf_id);
3695 spin_unlock_bh(&rx_ring->idr_lock);
3696 return -EINVAL;
3697 }
3698
3699 idr_remove(&rx_ring->bufs_idr, buf_id);
3700 spin_unlock_bh(&rx_ring->idr_lock);
3701
3702 rxcb = ATH11K_SKB_RXCB(msdu);
3703 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3704 msdu->len + skb_tailroom(msdu),
3705 DMA_FROM_DEVICE);
3706
3707 if (drop) {
3708 dev_kfree_skb_any(msdu);
3709 return 0;
3710 }
3711
3712 rcu_read_lock();
3713 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3714 dev_kfree_skb_any(msdu);
3715 goto exit;
3716 }
3717
3718 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3719 dev_kfree_skb_any(msdu);
3720 goto exit;
3721 }
3722
3723 rx_desc = (struct hal_rx_desc *)msdu->data;
3724 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3725 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3726 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3727 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3728 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3729 sizeof(struct ieee80211_hdr));
3730 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3731 sizeof(struct hal_rx_desc));
3732 dev_kfree_skb_any(msdu);
3733 goto exit;
3734 }
3735
3736 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3737
3738 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3739 dev_kfree_skb_any(msdu);
3740 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3741 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3742 }
3743 exit:
3744 rcu_read_unlock();
3745 return 0;
3746 }
3747
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3748 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3749 int budget)
3750 {
3751 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3752 struct dp_link_desc_bank *link_desc_banks;
3753 enum hal_rx_buf_return_buf_manager rbm;
3754 int tot_n_bufs_reaped, quota, ret, i;
3755 int n_bufs_reaped[MAX_RADIOS] = {0};
3756 struct dp_rxdma_ring *rx_ring;
3757 struct dp_srng *reo_except;
3758 u32 desc_bank, num_msdus;
3759 struct hal_srng *srng;
3760 struct ath11k_dp *dp;
3761 void *link_desc_va;
3762 int buf_id, mac_id;
3763 struct ath11k *ar;
3764 dma_addr_t paddr;
3765 u32 *desc;
3766 bool is_frag;
3767 u8 drop = 0;
3768
3769 tot_n_bufs_reaped = 0;
3770 quota = budget;
3771
3772 dp = &ab->dp;
3773 reo_except = &dp->reo_except_ring;
3774 link_desc_banks = dp->link_desc_banks;
3775
3776 srng = &ab->hal.srng_list[reo_except->ring_id];
3777
3778 spin_lock_bh(&srng->lock);
3779
3780 ath11k_hal_srng_access_begin(ab, srng);
3781
3782 while (budget &&
3783 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3784 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3785
3786 ab->soc_stats.err_ring_pkts++;
3787 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3788 &desc_bank);
3789 if (ret) {
3790 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3791 ret);
3792 continue;
3793 }
3794 link_desc_va = link_desc_banks[desc_bank].vaddr +
3795 (paddr - link_desc_banks[desc_bank].paddr);
3796 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3797 &rbm);
3798 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3799 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3800 ab->soc_stats.invalid_rbm++;
3801 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3802 ath11k_dp_rx_link_desc_return(ab, desc,
3803 HAL_WBM_REL_BM_ACT_REL_MSDU);
3804 continue;
3805 }
3806
3807 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3808
3809 /* Process only rx fragments with one msdu per link desc below, and drop
3810 * msdu's indicated due to error reasons.
3811 */
3812 if (!is_frag || num_msdus > 1) {
3813 drop = 1;
3814 /* Return the link desc back to wbm idle list */
3815 ath11k_dp_rx_link_desc_return(ab, desc,
3816 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3817 }
3818
3819 for (i = 0; i < num_msdus; i++) {
3820 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3821 msdu_cookies[i]);
3822
3823 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3824 msdu_cookies[i]);
3825
3826 ar = ab->pdevs[mac_id].ar;
3827
3828 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3829 n_bufs_reaped[mac_id]++;
3830 tot_n_bufs_reaped++;
3831 }
3832 }
3833
3834 if (tot_n_bufs_reaped >= quota) {
3835 tot_n_bufs_reaped = quota;
3836 goto exit;
3837 }
3838
3839 budget = quota - tot_n_bufs_reaped;
3840 }
3841
3842 exit:
3843 ath11k_hal_srng_access_end(ab, srng);
3844
3845 spin_unlock_bh(&srng->lock);
3846
3847 for (i = 0; i < ab->num_radios; i++) {
3848 if (!n_bufs_reaped[i])
3849 continue;
3850
3851 ar = ab->pdevs[i].ar;
3852 rx_ring = &ar->dp.rx_refill_buf_ring;
3853
3854 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3855 ab->hw_params.hal_params->rx_buf_rbm);
3856 }
3857
3858 return tot_n_bufs_reaped;
3859 }
3860
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3861 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3862 int msdu_len,
3863 struct sk_buff_head *msdu_list)
3864 {
3865 struct sk_buff *skb, *tmp;
3866 struct ath11k_skb_rxcb *rxcb;
3867 int n_buffs;
3868
3869 n_buffs = DIV_ROUND_UP(msdu_len,
3870 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3871
3872 skb_queue_walk_safe(msdu_list, skb, tmp) {
3873 rxcb = ATH11K_SKB_RXCB(skb);
3874 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3875 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3876 if (!n_buffs)
3877 break;
3878 __skb_unlink(skb, msdu_list);
3879 dev_kfree_skb_any(skb);
3880 n_buffs--;
3881 }
3882 }
3883 }
3884
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3885 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3886 struct ieee80211_rx_status *status,
3887 struct sk_buff_head *msdu_list)
3888 {
3889 u16 msdu_len;
3890 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3891 struct rx_attention *rx_attention;
3892 u8 l3pad_bytes;
3893 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3894 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3895
3896 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3897
3898 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3899 /* First buffer will be freed by the caller, so deduct it's length */
3900 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3901 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3902 return -EINVAL;
3903 }
3904
3905 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3906 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3907 ath11k_warn(ar->ab,
3908 "msdu_done bit not set in null_q_des processing\n");
3909 __skb_queue_purge(msdu_list);
3910 return -EIO;
3911 }
3912
3913 /* Handle NULL queue descriptor violations arising out a missing
3914 * REO queue for a given peer or a given TID. This typically
3915 * may happen if a packet is received on a QOS enabled TID before the
3916 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3917 * it may also happen for MC/BC frames if they are not routed to the
3918 * non-QOS TID queue, in the absence of any other default TID queue.
3919 * This error can show up both in a REO destination or WBM release ring.
3920 */
3921
3922 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3923 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3924
3925 if (rxcb->is_frag) {
3926 skb_pull(msdu, hal_rx_desc_sz);
3927 } else {
3928 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3929
3930 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3931 return -EINVAL;
3932
3933 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3934 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3935 }
3936 ath11k_dp_rx_h_ppdu(ar, desc, status);
3937
3938 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3939
3940 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3941
3942 /* Please note that caller will having the access to msdu and completing
3943 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3944 */
3945
3946 return 0;
3947 }
3948
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3949 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3950 struct ieee80211_rx_status *status,
3951 struct sk_buff_head *msdu_list)
3952 {
3953 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3954 bool drop = false;
3955
3956 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3957
3958 switch (rxcb->err_code) {
3959 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3960 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3961 drop = true;
3962 break;
3963 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3964 /* TODO: Do not drop PN failed packets in the driver;
3965 * instead, it is good to drop such packets in mac80211
3966 * after incrementing the replay counters.
3967 */
3968 fallthrough;
3969 default:
3970 /* TODO: Review other errors and process them to mac80211
3971 * as appropriate.
3972 */
3973 drop = true;
3974 break;
3975 }
3976
3977 return drop;
3978 }
3979
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3980 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3981 struct ieee80211_rx_status *status)
3982 {
3983 u16 msdu_len;
3984 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3985 u8 l3pad_bytes;
3986 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3987 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3988
3989 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3990 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3991
3992 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3993 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3994 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3995 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3996
3997 ath11k_dp_rx_h_ppdu(ar, desc, status);
3998
3999 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4000 RX_FLAG_DECRYPTED);
4001
4002 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4003 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4004 }
4005
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4006 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4007 struct ieee80211_rx_status *status)
4008 {
4009 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4010 bool drop = false;
4011
4012 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4013
4014 switch (rxcb->err_code) {
4015 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4016 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4017 break;
4018 default:
4019 /* TODO: Review other rxdma error code to check if anything is
4020 * worth reporting to mac80211
4021 */
4022 drop = true;
4023 break;
4024 }
4025
4026 return drop;
4027 }
4028
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4029 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4030 struct napi_struct *napi,
4031 struct sk_buff *msdu,
4032 struct sk_buff_head *msdu_list)
4033 {
4034 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4035 struct ieee80211_rx_status rxs = {0};
4036 bool drop = true;
4037
4038 switch (rxcb->err_rel_src) {
4039 case HAL_WBM_REL_SRC_MODULE_REO:
4040 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4041 break;
4042 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4043 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4044 break;
4045 default:
4046 /* msdu will get freed */
4047 break;
4048 }
4049
4050 if (drop) {
4051 dev_kfree_skb_any(msdu);
4052 return;
4053 }
4054
4055 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4056 }
4057
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4058 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4059 struct napi_struct *napi, int budget)
4060 {
4061 struct ath11k *ar;
4062 struct ath11k_dp *dp = &ab->dp;
4063 struct dp_rxdma_ring *rx_ring;
4064 struct hal_rx_wbm_rel_info err_info;
4065 struct hal_srng *srng;
4066 struct sk_buff *msdu;
4067 struct sk_buff_head msdu_list[MAX_RADIOS];
4068 struct ath11k_skb_rxcb *rxcb;
4069 u32 *rx_desc;
4070 int buf_id, mac_id;
4071 int num_buffs_reaped[MAX_RADIOS] = {0};
4072 int total_num_buffs_reaped = 0;
4073 int ret, i;
4074
4075 for (i = 0; i < ab->num_radios; i++)
4076 __skb_queue_head_init(&msdu_list[i]);
4077
4078 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4079
4080 spin_lock_bh(&srng->lock);
4081
4082 ath11k_hal_srng_access_begin(ab, srng);
4083
4084 while (budget) {
4085 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4086 if (!rx_desc)
4087 break;
4088
4089 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4090 if (ret) {
4091 ath11k_warn(ab,
4092 "failed to parse rx error in wbm_rel ring desc %d\n",
4093 ret);
4094 continue;
4095 }
4096
4097 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4098 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4099
4100 ar = ab->pdevs[mac_id].ar;
4101 rx_ring = &ar->dp.rx_refill_buf_ring;
4102
4103 spin_lock_bh(&rx_ring->idr_lock);
4104 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4105 if (!msdu) {
4106 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4107 buf_id, mac_id);
4108 spin_unlock_bh(&rx_ring->idr_lock);
4109 continue;
4110 }
4111
4112 idr_remove(&rx_ring->bufs_idr, buf_id);
4113 spin_unlock_bh(&rx_ring->idr_lock);
4114
4115 rxcb = ATH11K_SKB_RXCB(msdu);
4116 dma_unmap_single(ab->dev, rxcb->paddr,
4117 msdu->len + skb_tailroom(msdu),
4118 DMA_FROM_DEVICE);
4119
4120 num_buffs_reaped[mac_id]++;
4121 total_num_buffs_reaped++;
4122 budget--;
4123
4124 if (err_info.push_reason !=
4125 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4126 dev_kfree_skb_any(msdu);
4127 continue;
4128 }
4129
4130 rxcb->err_rel_src = err_info.err_rel_src;
4131 rxcb->err_code = err_info.err_code;
4132 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4133 __skb_queue_tail(&msdu_list[mac_id], msdu);
4134 }
4135
4136 ath11k_hal_srng_access_end(ab, srng);
4137
4138 spin_unlock_bh(&srng->lock);
4139
4140 if (!total_num_buffs_reaped)
4141 goto done;
4142
4143 for (i = 0; i < ab->num_radios; i++) {
4144 if (!num_buffs_reaped[i])
4145 continue;
4146
4147 ar = ab->pdevs[i].ar;
4148 rx_ring = &ar->dp.rx_refill_buf_ring;
4149
4150 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4151 ab->hw_params.hal_params->rx_buf_rbm);
4152 }
4153
4154 rcu_read_lock();
4155 for (i = 0; i < ab->num_radios; i++) {
4156 if (!rcu_dereference(ab->pdevs_active[i])) {
4157 __skb_queue_purge(&msdu_list[i]);
4158 continue;
4159 }
4160
4161 ar = ab->pdevs[i].ar;
4162
4163 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4164 __skb_queue_purge(&msdu_list[i]);
4165 continue;
4166 }
4167
4168 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4169 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4170 }
4171 rcu_read_unlock();
4172 done:
4173 return total_num_buffs_reaped;
4174 }
4175
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4176 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4177 {
4178 struct ath11k *ar;
4179 struct dp_srng *err_ring;
4180 struct dp_rxdma_ring *rx_ring;
4181 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4182 struct hal_srng *srng;
4183 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4184 enum hal_rx_buf_return_buf_manager rbm;
4185 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4186 struct ath11k_skb_rxcb *rxcb;
4187 struct sk_buff *skb;
4188 struct hal_reo_entrance_ring *entr_ring;
4189 void *desc;
4190 int num_buf_freed = 0;
4191 int quota = budget;
4192 dma_addr_t paddr;
4193 u32 desc_bank;
4194 void *link_desc_va;
4195 int num_msdus;
4196 int i;
4197 int buf_id;
4198
4199 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4200 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4201 mac_id)];
4202 rx_ring = &ar->dp.rx_refill_buf_ring;
4203
4204 srng = &ab->hal.srng_list[err_ring->ring_id];
4205
4206 spin_lock_bh(&srng->lock);
4207
4208 ath11k_hal_srng_access_begin(ab, srng);
4209
4210 while (quota-- &&
4211 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4212 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4213
4214 entr_ring = (struct hal_reo_entrance_ring *)desc;
4215 rxdma_err_code =
4216 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4217 entr_ring->info1);
4218 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4219
4220 link_desc_va = link_desc_banks[desc_bank].vaddr +
4221 (paddr - link_desc_banks[desc_bank].paddr);
4222 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4223 msdu_cookies, &rbm);
4224
4225 for (i = 0; i < num_msdus; i++) {
4226 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4227 msdu_cookies[i]);
4228
4229 spin_lock_bh(&rx_ring->idr_lock);
4230 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4231 if (!skb) {
4232 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4233 buf_id);
4234 spin_unlock_bh(&rx_ring->idr_lock);
4235 continue;
4236 }
4237
4238 idr_remove(&rx_ring->bufs_idr, buf_id);
4239 spin_unlock_bh(&rx_ring->idr_lock);
4240
4241 rxcb = ATH11K_SKB_RXCB(skb);
4242 dma_unmap_single(ab->dev, rxcb->paddr,
4243 skb->len + skb_tailroom(skb),
4244 DMA_FROM_DEVICE);
4245 dev_kfree_skb_any(skb);
4246
4247 num_buf_freed++;
4248 }
4249
4250 ath11k_dp_rx_link_desc_return(ab, desc,
4251 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4252 }
4253
4254 ath11k_hal_srng_access_end(ab, srng);
4255
4256 spin_unlock_bh(&srng->lock);
4257
4258 if (num_buf_freed)
4259 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4260 ab->hw_params.hal_params->rx_buf_rbm);
4261
4262 return budget - quota;
4263 }
4264
ath11k_dp_process_reo_status(struct ath11k_base * ab)4265 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4266 {
4267 struct ath11k_dp *dp = &ab->dp;
4268 struct hal_srng *srng;
4269 struct dp_reo_cmd *cmd, *tmp;
4270 bool found = false;
4271 u32 *reo_desc;
4272 u16 tag;
4273 struct hal_reo_status reo_status;
4274
4275 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4276
4277 memset(&reo_status, 0, sizeof(reo_status));
4278
4279 spin_lock_bh(&srng->lock);
4280
4281 ath11k_hal_srng_access_begin(ab, srng);
4282
4283 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4284 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4285
4286 switch (tag) {
4287 case HAL_REO_GET_QUEUE_STATS_STATUS:
4288 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4289 &reo_status);
4290 break;
4291 case HAL_REO_FLUSH_QUEUE_STATUS:
4292 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4293 &reo_status);
4294 break;
4295 case HAL_REO_FLUSH_CACHE_STATUS:
4296 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4297 &reo_status);
4298 break;
4299 case HAL_REO_UNBLOCK_CACHE_STATUS:
4300 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4301 &reo_status);
4302 break;
4303 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4304 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4305 &reo_status);
4306 break;
4307 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4308 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4309 &reo_status);
4310 break;
4311 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4312 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4313 &reo_status);
4314 break;
4315 default:
4316 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4317 continue;
4318 }
4319
4320 spin_lock_bh(&dp->reo_cmd_lock);
4321 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4322 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4323 found = true;
4324 list_del(&cmd->list);
4325 break;
4326 }
4327 }
4328 spin_unlock_bh(&dp->reo_cmd_lock);
4329
4330 if (found) {
4331 cmd->handler(dp, (void *)&cmd->data,
4332 reo_status.uniform_hdr.cmd_status);
4333 kfree(cmd);
4334 }
4335
4336 found = false;
4337 }
4338
4339 ath11k_hal_srng_access_end(ab, srng);
4340
4341 spin_unlock_bh(&srng->lock);
4342 }
4343
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4344 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4345 {
4346 struct ath11k *ar = ab->pdevs[mac_id].ar;
4347
4348 ath11k_dp_rx_pdev_srng_free(ar);
4349 ath11k_dp_rxdma_pdev_buf_free(ar);
4350 }
4351
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4352 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4353 {
4354 struct ath11k *ar = ab->pdevs[mac_id].ar;
4355 struct ath11k_pdev_dp *dp = &ar->dp;
4356 u32 ring_id;
4357 int i;
4358 int ret;
4359
4360 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4361 if (ret) {
4362 ath11k_warn(ab, "failed to setup rx srngs\n");
4363 return ret;
4364 }
4365
4366 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4367 if (ret) {
4368 ath11k_warn(ab, "failed to setup rxdma ring\n");
4369 return ret;
4370 }
4371
4372 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4373 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4374 if (ret) {
4375 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4376 ret);
4377 return ret;
4378 }
4379
4380 if (ab->hw_params.rx_mac_buf_ring) {
4381 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4382 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4383 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4384 mac_id + i, HAL_RXDMA_BUF);
4385 if (ret) {
4386 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4387 i, ret);
4388 return ret;
4389 }
4390 }
4391 }
4392
4393 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4394 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4395 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4396 mac_id + i, HAL_RXDMA_DST);
4397 if (ret) {
4398 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4399 i, ret);
4400 return ret;
4401 }
4402 }
4403
4404 if (!ab->hw_params.rxdma1_enable)
4405 goto config_refill_ring;
4406
4407 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4408 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4409 mac_id, HAL_RXDMA_MONITOR_BUF);
4410 if (ret) {
4411 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4412 ret);
4413 return ret;
4414 }
4415 ret = ath11k_dp_tx_htt_srng_setup(ab,
4416 dp->rxdma_mon_dst_ring.ring_id,
4417 mac_id, HAL_RXDMA_MONITOR_DST);
4418 if (ret) {
4419 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4420 ret);
4421 return ret;
4422 }
4423 ret = ath11k_dp_tx_htt_srng_setup(ab,
4424 dp->rxdma_mon_desc_ring.ring_id,
4425 mac_id, HAL_RXDMA_MONITOR_DESC);
4426 if (ret) {
4427 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4428 ret);
4429 return ret;
4430 }
4431
4432 config_refill_ring:
4433 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4434 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4435 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4436 HAL_RXDMA_MONITOR_STATUS);
4437 if (ret) {
4438 ath11k_warn(ab,
4439 "failed to configure mon_status_refill_ring%d %d\n",
4440 i, ret);
4441 return ret;
4442 }
4443 }
4444
4445 return 0;
4446 }
4447
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4448 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4449 {
4450 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4451 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4452 *total_len -= *frag_len;
4453 } else {
4454 *frag_len = *total_len;
4455 *total_len = 0;
4456 }
4457 }
4458
4459 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4460 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4461 void *p_last_buf_addr_info,
4462 u8 mac_id)
4463 {
4464 struct ath11k_pdev_dp *dp = &ar->dp;
4465 struct dp_srng *dp_srng;
4466 void *hal_srng;
4467 void *src_srng_desc;
4468 int ret = 0;
4469
4470 if (ar->ab->hw_params.rxdma1_enable) {
4471 dp_srng = &dp->rxdma_mon_desc_ring;
4472 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4473 } else {
4474 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4475 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4476 }
4477
4478 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4479
4480 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4481
4482 if (src_srng_desc) {
4483 struct ath11k_buffer_addr *src_desc =
4484 (struct ath11k_buffer_addr *)src_srng_desc;
4485
4486 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4487 } else {
4488 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4489 "Monitor Link Desc Ring %d Full", mac_id);
4490 ret = -ENOMEM;
4491 }
4492
4493 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4494 return ret;
4495 }
4496
4497 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4498 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4499 dma_addr_t *paddr, u32 *sw_cookie,
4500 u8 *rbm,
4501 void **pp_buf_addr_info)
4502 {
4503 struct hal_rx_msdu_link *msdu_link =
4504 (struct hal_rx_msdu_link *)rx_msdu_link_desc;
4505 struct ath11k_buffer_addr *buf_addr_info;
4506
4507 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4508
4509 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4510
4511 *pp_buf_addr_info = (void *)buf_addr_info;
4512 }
4513
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4514 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4515 {
4516 if (skb->len > len) {
4517 skb_trim(skb, len);
4518 } else {
4519 if (skb_tailroom(skb) < len - skb->len) {
4520 if ((pskb_expand_head(skb, 0,
4521 len - skb->len - skb_tailroom(skb),
4522 GFP_ATOMIC))) {
4523 dev_kfree_skb_any(skb);
4524 return -ENOMEM;
4525 }
4526 }
4527 skb_put(skb, (len - skb->len));
4528 }
4529 return 0;
4530 }
4531
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4532 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4533 void *msdu_link_desc,
4534 struct hal_rx_msdu_list *msdu_list,
4535 u16 *num_msdus)
4536 {
4537 struct hal_rx_msdu_details *msdu_details = NULL;
4538 struct rx_msdu_desc *msdu_desc_info = NULL;
4539 struct hal_rx_msdu_link *msdu_link = NULL;
4540 int i;
4541 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4542 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4543 u8 tmp = 0;
4544
4545 msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4546 msdu_details = &msdu_link->msdu_link[0];
4547
4548 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4549 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4550 msdu_details[i].buf_addr_info.info0) == 0) {
4551 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4552 msdu_desc_info->info0 |= last;
4553 ;
4554 break;
4555 }
4556 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4557
4558 if (!i)
4559 msdu_desc_info->info0 |= first;
4560 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4561 msdu_desc_info->info0 |= last;
4562 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4563 msdu_list->msdu_info[i].msdu_len =
4564 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4565 msdu_list->sw_cookie[i] =
4566 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4567 msdu_details[i].buf_addr_info.info1);
4568 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4569 msdu_details[i].buf_addr_info.info1);
4570 msdu_list->rbm[i] = tmp;
4571 }
4572 *num_msdus = i;
4573 }
4574
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4575 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4576 u32 *rx_bufs_used)
4577 {
4578 u32 ret = 0;
4579
4580 if ((*ppdu_id < msdu_ppdu_id) &&
4581 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4582 *ppdu_id = msdu_ppdu_id;
4583 ret = msdu_ppdu_id;
4584 } else if ((*ppdu_id > msdu_ppdu_id) &&
4585 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4586 /* mon_dst is behind than mon_status
4587 * skip dst_ring and free it
4588 */
4589 *rx_bufs_used += 1;
4590 *ppdu_id = msdu_ppdu_id;
4591 ret = msdu_ppdu_id;
4592 }
4593 return ret;
4594 }
4595
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4596 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4597 bool *is_frag, u32 *total_len,
4598 u32 *frag_len, u32 *msdu_cnt)
4599 {
4600 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4601 if (!*is_frag) {
4602 *total_len = info->msdu_len;
4603 *is_frag = true;
4604 }
4605 ath11k_dp_mon_set_frag_len(total_len,
4606 frag_len);
4607 } else {
4608 if (*is_frag) {
4609 ath11k_dp_mon_set_frag_len(total_len,
4610 frag_len);
4611 } else {
4612 *frag_len = info->msdu_len;
4613 }
4614 *is_frag = false;
4615 *msdu_cnt -= 1;
4616 }
4617 }
4618
4619 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4620 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4621 void *ring_entry, struct sk_buff **head_msdu,
4622 struct sk_buff **tail_msdu, u32 *npackets,
4623 u32 *ppdu_id)
4624 {
4625 struct ath11k_pdev_dp *dp = &ar->dp;
4626 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4627 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4628 struct sk_buff *msdu = NULL, *last = NULL;
4629 struct hal_rx_msdu_list msdu_list;
4630 void *p_buf_addr_info, *p_last_buf_addr_info;
4631 struct hal_rx_desc *rx_desc;
4632 void *rx_msdu_link_desc;
4633 dma_addr_t paddr;
4634 u16 num_msdus = 0;
4635 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4636 u32 rx_bufs_used = 0, i = 0;
4637 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4638 u32 total_len = 0, frag_len = 0;
4639 bool is_frag, is_first_msdu;
4640 bool drop_mpdu = false;
4641 struct ath11k_skb_rxcb *rxcb;
4642 struct hal_reo_entrance_ring *ent_desc =
4643 (struct hal_reo_entrance_ring *)ring_entry;
4644 int buf_id;
4645 u32 rx_link_buf_info[2];
4646 u8 rbm;
4647
4648 if (!ar->ab->hw_params.rxdma1_enable)
4649 rx_ring = &dp->rx_refill_buf_ring;
4650
4651 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4652 &sw_cookie,
4653 &p_last_buf_addr_info, &rbm,
4654 &msdu_cnt);
4655
4656 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4657 ent_desc->info1) ==
4658 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4659 u8 rxdma_err =
4660 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4661 ent_desc->info1);
4662 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4663 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4664 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4665 drop_mpdu = true;
4666 pmon->rx_mon_stats.dest_mpdu_drop++;
4667 }
4668 }
4669
4670 is_frag = false;
4671 is_first_msdu = true;
4672
4673 do {
4674 if (pmon->mon_last_linkdesc_paddr == paddr) {
4675 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4676 return rx_bufs_used;
4677 }
4678
4679 if (ar->ab->hw_params.rxdma1_enable)
4680 rx_msdu_link_desc =
4681 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4682 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4683 else
4684 rx_msdu_link_desc =
4685 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4686 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4687
4688 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4689 &num_msdus);
4690
4691 for (i = 0; i < num_msdus; i++) {
4692 u32 l2_hdr_offset;
4693
4694 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4695 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4696 "i %d last_cookie %d is same\n",
4697 i, pmon->mon_last_buf_cookie);
4698 drop_mpdu = true;
4699 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4700 continue;
4701 }
4702 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4703 msdu_list.sw_cookie[i]);
4704
4705 spin_lock_bh(&rx_ring->idr_lock);
4706 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4707 spin_unlock_bh(&rx_ring->idr_lock);
4708 if (!msdu) {
4709 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4710 "msdu_pop: invalid buf_id %d\n", buf_id);
4711 break;
4712 }
4713 rxcb = ATH11K_SKB_RXCB(msdu);
4714 if (!rxcb->unmapped) {
4715 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4716 msdu->len +
4717 skb_tailroom(msdu),
4718 DMA_FROM_DEVICE);
4719 rxcb->unmapped = 1;
4720 }
4721 if (drop_mpdu) {
4722 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4723 "i %d drop msdu %p *ppdu_id %x\n",
4724 i, msdu, *ppdu_id);
4725 dev_kfree_skb_any(msdu);
4726 msdu = NULL;
4727 goto next_msdu;
4728 }
4729
4730 rx_desc = (struct hal_rx_desc *)msdu->data;
4731
4732 rx_pkt_offset = sizeof(struct hal_rx_desc);
4733 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4734
4735 if (is_first_msdu) {
4736 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4737 drop_mpdu = true;
4738 dev_kfree_skb_any(msdu);
4739 msdu = NULL;
4740 pmon->mon_last_linkdesc_paddr = paddr;
4741 goto next_msdu;
4742 }
4743
4744 msdu_ppdu_id =
4745 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4746
4747 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4748 ppdu_id,
4749 &rx_bufs_used)) {
4750 if (rx_bufs_used) {
4751 drop_mpdu = true;
4752 dev_kfree_skb_any(msdu);
4753 msdu = NULL;
4754 goto next_msdu;
4755 }
4756 return rx_bufs_used;
4757 }
4758 pmon->mon_last_linkdesc_paddr = paddr;
4759 is_first_msdu = false;
4760 }
4761 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4762 &is_frag, &total_len,
4763 &frag_len, &msdu_cnt);
4764 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4765
4766 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4767
4768 if (!(*head_msdu))
4769 *head_msdu = msdu;
4770 else if (last)
4771 last->next = msdu;
4772
4773 last = msdu;
4774 next_msdu:
4775 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4776 rx_bufs_used++;
4777 spin_lock_bh(&rx_ring->idr_lock);
4778 idr_remove(&rx_ring->bufs_idr, buf_id);
4779 spin_unlock_bh(&rx_ring->idr_lock);
4780 }
4781
4782 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4783
4784 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4785 &sw_cookie, &rbm,
4786 &p_buf_addr_info);
4787
4788 if (ar->ab->hw_params.rxdma1_enable) {
4789 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4790 p_last_buf_addr_info,
4791 dp->mac_id))
4792 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4793 "dp_rx_monitor_link_desc_return failed");
4794 } else {
4795 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4796 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4797 }
4798
4799 p_last_buf_addr_info = p_buf_addr_info;
4800
4801 } while (paddr && msdu_cnt);
4802
4803 if (last)
4804 last->next = NULL;
4805
4806 *tail_msdu = msdu;
4807
4808 if (msdu_cnt == 0)
4809 *npackets = 1;
4810
4811 return rx_bufs_used;
4812 }
4813
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4814 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4815 {
4816 u32 rx_pkt_offset, l2_hdr_offset;
4817
4818 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4819 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4820 (struct hal_rx_desc *)msdu->data);
4821 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4822 }
4823
4824 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4825 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4826 u32 mac_id, struct sk_buff *head_msdu,
4827 struct sk_buff *last_msdu,
4828 struct ieee80211_rx_status *rxs, bool *fcs_err)
4829 {
4830 struct ath11k_base *ab = ar->ab;
4831 struct sk_buff *msdu, *prev_buf;
4832 struct hal_rx_desc *rx_desc;
4833 char *hdr_desc;
4834 u8 *dest, decap_format;
4835 struct ieee80211_hdr_3addr *wh;
4836 struct rx_attention *rx_attention;
4837 u32 err_bitmap;
4838
4839 if (!head_msdu)
4840 goto err_merge_fail;
4841
4842 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4843 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4844 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4845
4846 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4847 *fcs_err = true;
4848
4849 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4850 return NULL;
4851
4852 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4853
4854 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4855
4856 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4857 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4858
4859 prev_buf = head_msdu;
4860 msdu = head_msdu->next;
4861
4862 while (msdu) {
4863 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4864
4865 prev_buf = msdu;
4866 msdu = msdu->next;
4867 }
4868
4869 prev_buf->next = NULL;
4870
4871 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4872 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4873 u8 qos_pkt = 0;
4874
4875 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4876 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4877
4878 /* Base size */
4879 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4880
4881 if (ieee80211_is_data_qos(wh->frame_control))
4882 qos_pkt = 1;
4883
4884 msdu = head_msdu;
4885
4886 while (msdu) {
4887 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4888 if (qos_pkt) {
4889 dest = skb_push(msdu, sizeof(__le16));
4890 if (!dest)
4891 goto err_merge_fail;
4892 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4893 }
4894 prev_buf = msdu;
4895 msdu = msdu->next;
4896 }
4897 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4898 if (!dest)
4899 goto err_merge_fail;
4900
4901 ath11k_dbg(ab, ATH11K_DBG_DATA,
4902 "mpdu_buf %pK mpdu_buf->len %u",
4903 prev_buf, prev_buf->len);
4904 } else {
4905 ath11k_dbg(ab, ATH11K_DBG_DATA,
4906 "decap format %d is not supported!\n",
4907 decap_format);
4908 goto err_merge_fail;
4909 }
4910
4911 return head_msdu;
4912
4913 err_merge_fail:
4914 return NULL;
4915 }
4916
4917 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4918 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4919 u8 *rtap_buf)
4920 {
4921 u32 rtap_len = 0;
4922
4923 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4924 rtap_len += 2;
4925
4926 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4927 rtap_len += 2;
4928
4929 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4930 rtap_len += 2;
4931
4932 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
4933 rtap_len += 2;
4934
4935 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
4936 rtap_len += 2;
4937
4938 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
4939 }
4940
4941 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4942 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
4943 u8 *rtap_buf)
4944 {
4945 u32 rtap_len = 0;
4946
4947 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
4948 rtap_len += 2;
4949
4950 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
4951 rtap_len += 2;
4952
4953 rtap_buf[rtap_len] = rx_status->he_RU[0];
4954 rtap_len += 1;
4955
4956 rtap_buf[rtap_len] = rx_status->he_RU[1];
4957 rtap_len += 1;
4958
4959 rtap_buf[rtap_len] = rx_status->he_RU[2];
4960 rtap_len += 1;
4961
4962 rtap_buf[rtap_len] = rx_status->he_RU[3];
4963 }
4964
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)4965 static void ath11k_update_radiotap(struct ath11k *ar,
4966 struct hal_rx_mon_ppdu_info *ppduinfo,
4967 struct sk_buff *mon_skb,
4968 struct ieee80211_rx_status *rxs)
4969 {
4970 struct ieee80211_supported_band *sband;
4971 u8 *ptr = NULL;
4972
4973 rxs->flag |= RX_FLAG_MACTIME_START;
4974 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
4975
4976 if (ppduinfo->nss)
4977 rxs->nss = ppduinfo->nss;
4978
4979 if (ppduinfo->he_mu_flags) {
4980 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
4981 rxs->encoding = RX_ENC_HE;
4982 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
4983 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
4984 } else if (ppduinfo->he_flags) {
4985 rxs->flag |= RX_FLAG_RADIOTAP_HE;
4986 rxs->encoding = RX_ENC_HE;
4987 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
4988 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
4989 rxs->rate_idx = ppduinfo->rate;
4990 } else if (ppduinfo->vht_flags) {
4991 rxs->encoding = RX_ENC_VHT;
4992 rxs->rate_idx = ppduinfo->rate;
4993 } else if (ppduinfo->ht_flags) {
4994 rxs->encoding = RX_ENC_HT;
4995 rxs->rate_idx = ppduinfo->rate;
4996 } else {
4997 rxs->encoding = RX_ENC_LEGACY;
4998 sband = &ar->mac.sbands[rxs->band];
4999 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5000 ppduinfo->cck_flag);
5001 }
5002
5003 rxs->mactime = ppduinfo->tsft;
5004 }
5005
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5006 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5007 struct sk_buff *head_msdu,
5008 struct hal_rx_mon_ppdu_info *ppduinfo,
5009 struct sk_buff *tail_msdu,
5010 struct napi_struct *napi)
5011 {
5012 struct ath11k_pdev_dp *dp = &ar->dp;
5013 struct sk_buff *mon_skb, *skb_next, *header;
5014 struct ieee80211_rx_status *rxs = &dp->rx_status;
5015 bool fcs_err = false;
5016
5017 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5018 tail_msdu, rxs, &fcs_err);
5019
5020 if (!mon_skb)
5021 goto mon_deliver_fail;
5022
5023 header = mon_skb;
5024
5025 rxs->flag = 0;
5026
5027 if (fcs_err)
5028 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5029
5030 do {
5031 skb_next = mon_skb->next;
5032 if (!skb_next)
5033 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5034 else
5035 rxs->flag |= RX_FLAG_AMSDU_MORE;
5036
5037 if (mon_skb == header) {
5038 header = NULL;
5039 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5040 } else {
5041 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5042 }
5043 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5044 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5045
5046 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5047 mon_skb = skb_next;
5048 } while (mon_skb);
5049 rxs->flag = 0;
5050
5051 return 0;
5052
5053 mon_deliver_fail:
5054 mon_skb = head_msdu;
5055 while (mon_skb) {
5056 skb_next = mon_skb->next;
5057 dev_kfree_skb_any(mon_skb);
5058 mon_skb = skb_next;
5059 }
5060 return -EINVAL;
5061 }
5062
5063 /* The destination ring processing is stuck if the destination is not
5064 * moving while status ring moves 16 PPDU. The destination ring processing
5065 * skips this destination ring PPDU as a workaround.
5066 */
5067 #define MON_DEST_RING_STUCK_MAX_CNT 16
5068
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5069 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5070 u32 quota, struct napi_struct *napi)
5071 {
5072 struct ath11k_pdev_dp *dp = &ar->dp;
5073 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5074 const struct ath11k_hw_hal_params *hal_params;
5075 void *ring_entry;
5076 void *mon_dst_srng;
5077 u32 ppdu_id;
5078 u32 rx_bufs_used;
5079 u32 ring_id;
5080 struct ath11k_pdev_mon_stats *rx_mon_stats;
5081 u32 npackets = 0;
5082 u32 mpdu_rx_bufs_used;
5083
5084 if (ar->ab->hw_params.rxdma1_enable)
5085 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5086 else
5087 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5088
5089 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5090
5091 if (!mon_dst_srng) {
5092 ath11k_warn(ar->ab,
5093 "HAL Monitor Destination Ring Init Failed -- %pK",
5094 mon_dst_srng);
5095 return;
5096 }
5097
5098 spin_lock_bh(&pmon->mon_lock);
5099
5100 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5101
5102 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5103 rx_bufs_used = 0;
5104 rx_mon_stats = &pmon->rx_mon_stats;
5105
5106 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5107 struct sk_buff *head_msdu, *tail_msdu;
5108
5109 head_msdu = NULL;
5110 tail_msdu = NULL;
5111
5112 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5113 &head_msdu,
5114 &tail_msdu,
5115 &npackets, &ppdu_id);
5116
5117 rx_bufs_used += mpdu_rx_bufs_used;
5118
5119 if (mpdu_rx_bufs_used) {
5120 dp->mon_dest_ring_stuck_cnt = 0;
5121 } else {
5122 dp->mon_dest_ring_stuck_cnt++;
5123 rx_mon_stats->dest_mon_not_reaped++;
5124 }
5125
5126 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5127 rx_mon_stats->dest_mon_stuck++;
5128 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5129 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5130 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5131 dp->mon_dest_ring_stuck_cnt,
5132 rx_mon_stats->dest_mon_not_reaped,
5133 rx_mon_stats->dest_mon_stuck);
5134 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5135 continue;
5136 }
5137
5138 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5139 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5140 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5141 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5142 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5143 rx_mon_stats->dest_mon_not_reaped,
5144 rx_mon_stats->dest_mon_stuck);
5145 break;
5146 }
5147 if (head_msdu && tail_msdu) {
5148 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5149 &pmon->mon_ppdu_info,
5150 tail_msdu, napi);
5151 rx_mon_stats->dest_mpdu_done++;
5152 }
5153
5154 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5155 mon_dst_srng);
5156 }
5157 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5158
5159 spin_unlock_bh(&pmon->mon_lock);
5160
5161 if (rx_bufs_used) {
5162 rx_mon_stats->dest_ppdu_done++;
5163 hal_params = ar->ab->hw_params.hal_params;
5164
5165 if (ar->ab->hw_params.rxdma1_enable)
5166 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5167 &dp->rxdma_mon_buf_ring,
5168 rx_bufs_used,
5169 hal_params->rx_buf_rbm);
5170 else
5171 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5172 &dp->rx_refill_buf_ring,
5173 rx_bufs_used,
5174 hal_params->rx_buf_rbm);
5175 }
5176 }
5177
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5178 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5179 struct napi_struct *napi, int budget)
5180 {
5181 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5182 enum hal_rx_mon_status hal_status;
5183 struct sk_buff *skb;
5184 struct sk_buff_head skb_list;
5185 struct ath11k_peer *peer;
5186 struct ath11k_sta *arsta;
5187 int num_buffs_reaped = 0;
5188 u32 rx_buf_sz;
5189 u16 log_type;
5190 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5191 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5192 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5193
5194 __skb_queue_head_init(&skb_list);
5195
5196 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5197 &skb_list);
5198 if (!num_buffs_reaped)
5199 goto exit;
5200
5201 memset(ppdu_info, 0, sizeof(*ppdu_info));
5202 ppdu_info->peer_id = HAL_INVALID_PEERID;
5203
5204 while ((skb = __skb_dequeue(&skb_list))) {
5205 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5206 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5207 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5208 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5209 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5210 rx_buf_sz = DP_RX_BUFFER_SIZE;
5211 } else {
5212 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5213 rx_buf_sz = 0;
5214 }
5215
5216 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5217 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5218
5219 memset(ppdu_info, 0, sizeof(*ppdu_info));
5220 ppdu_info->peer_id = HAL_INVALID_PEERID;
5221 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5222
5223 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5224 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5225 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5226 rx_mon_stats->status_ppdu_done++;
5227 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5228 ath11k_dp_rx_mon_dest_process(ar, mac_id, budget, napi);
5229 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5230 }
5231
5232 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5233 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5234 dev_kfree_skb_any(skb);
5235 continue;
5236 }
5237
5238 rcu_read_lock();
5239 spin_lock_bh(&ab->base_lock);
5240 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5241
5242 if (!peer || !peer->sta) {
5243 ath11k_dbg(ab, ATH11K_DBG_DATA,
5244 "failed to find the peer with peer_id %d\n",
5245 ppdu_info->peer_id);
5246 goto next_skb;
5247 }
5248
5249 arsta = (struct ath11k_sta *)peer->sta->drv_priv;
5250 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5251
5252 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5253 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5254
5255 next_skb:
5256 spin_unlock_bh(&ab->base_lock);
5257 rcu_read_unlock();
5258
5259 dev_kfree_skb_any(skb);
5260 memset(ppdu_info, 0, sizeof(*ppdu_info));
5261 ppdu_info->peer_id = HAL_INVALID_PEERID;
5262 }
5263 exit:
5264 return num_buffs_reaped;
5265 }
5266
5267 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5268 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5269 void *ring_entry, struct sk_buff **head_msdu,
5270 struct sk_buff **tail_msdu,
5271 struct hal_sw_mon_ring_entries *sw_mon_entries)
5272 {
5273 struct ath11k_pdev_dp *dp = &ar->dp;
5274 struct ath11k_mon_data *pmon = &dp->mon_data;
5275 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5276 struct sk_buff *msdu = NULL, *last = NULL;
5277 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5278 struct hal_rx_msdu_list msdu_list;
5279 struct hal_rx_desc *rx_desc;
5280 struct ath11k_skb_rxcb *rxcb;
5281 void *rx_msdu_link_desc;
5282 void *p_buf_addr_info, *p_last_buf_addr_info;
5283 int buf_id, i = 0;
5284 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5285 u32 rx_bufs_used = 0, msdu_cnt = 0;
5286 u32 total_len = 0, frag_len = 0, sw_cookie;
5287 u16 num_msdus = 0;
5288 u8 rxdma_err, rbm;
5289 bool is_frag, is_first_msdu;
5290 bool drop_mpdu = false;
5291
5292 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5293
5294 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5295 sw_mon_entries->end_of_ppdu = false;
5296 sw_mon_entries->drop_ppdu = false;
5297 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5298 msdu_cnt = sw_mon_entries->msdu_cnt;
5299
5300 sw_mon_entries->end_of_ppdu =
5301 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5302 if (sw_mon_entries->end_of_ppdu)
5303 return rx_bufs_used;
5304
5305 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5306 sw_desc->info0) ==
5307 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5308 rxdma_err =
5309 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5310 sw_desc->info0);
5311 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5312 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5313 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5314 pmon->rx_mon_stats.dest_mpdu_drop++;
5315 drop_mpdu = true;
5316 }
5317 }
5318
5319 is_frag = false;
5320 is_first_msdu = true;
5321
5322 do {
5323 rx_msdu_link_desc =
5324 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5325 (sw_mon_entries->mon_dst_paddr -
5326 pmon->link_desc_banks[sw_cookie].paddr);
5327
5328 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5329 &num_msdus);
5330
5331 for (i = 0; i < num_msdus; i++) {
5332 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5333 msdu_list.sw_cookie[i]);
5334
5335 spin_lock_bh(&rx_ring->idr_lock);
5336 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5337 if (!msdu) {
5338 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5339 "full mon msdu_pop: invalid buf_id %d\n",
5340 buf_id);
5341 spin_unlock_bh(&rx_ring->idr_lock);
5342 break;
5343 }
5344 idr_remove(&rx_ring->bufs_idr, buf_id);
5345 spin_unlock_bh(&rx_ring->idr_lock);
5346
5347 rxcb = ATH11K_SKB_RXCB(msdu);
5348 if (!rxcb->unmapped) {
5349 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5350 msdu->len +
5351 skb_tailroom(msdu),
5352 DMA_FROM_DEVICE);
5353 rxcb->unmapped = 1;
5354 }
5355 if (drop_mpdu) {
5356 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5357 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5358 i, msdu, sw_mon_entries->ppdu_id);
5359 dev_kfree_skb_any(msdu);
5360 msdu_cnt--;
5361 goto next_msdu;
5362 }
5363
5364 rx_desc = (struct hal_rx_desc *)msdu->data;
5365
5366 rx_pkt_offset = sizeof(struct hal_rx_desc);
5367 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5368
5369 if (is_first_msdu) {
5370 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5371 drop_mpdu = true;
5372 dev_kfree_skb_any(msdu);
5373 msdu = NULL;
5374 goto next_msdu;
5375 }
5376 is_first_msdu = false;
5377 }
5378
5379 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5380 &is_frag, &total_len,
5381 &frag_len, &msdu_cnt);
5382
5383 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5384
5385 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5386
5387 if (!(*head_msdu))
5388 *head_msdu = msdu;
5389 else if (last)
5390 last->next = msdu;
5391
5392 last = msdu;
5393 next_msdu:
5394 rx_bufs_used++;
5395 }
5396
5397 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5398 &sw_mon_entries->mon_dst_paddr,
5399 &sw_mon_entries->mon_dst_sw_cookie,
5400 &rbm,
5401 &p_buf_addr_info);
5402
5403 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5404 p_last_buf_addr_info,
5405 dp->mac_id))
5406 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5407 "full mon: dp_rx_monitor_link_desc_return failed\n");
5408
5409 p_last_buf_addr_info = p_buf_addr_info;
5410
5411 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5412
5413 if (last)
5414 last->next = NULL;
5415
5416 *tail_msdu = msdu;
5417
5418 return rx_bufs_used;
5419 }
5420
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5421 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5422 struct dp_full_mon_mpdu *mon_mpdu,
5423 struct sk_buff *head,
5424 struct sk_buff *tail)
5425 {
5426 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5427 if (!mon_mpdu)
5428 return -ENOMEM;
5429
5430 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5431 mon_mpdu->head = head;
5432 mon_mpdu->tail = tail;
5433
5434 return 0;
5435 }
5436
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5437 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5438 struct dp_full_mon_mpdu *mon_mpdu)
5439 {
5440 struct dp_full_mon_mpdu *tmp;
5441 struct sk_buff *tmp_msdu, *skb_next;
5442
5443 if (list_empty(&dp->dp_full_mon_mpdu_list))
5444 return;
5445
5446 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5447 list_del(&mon_mpdu->list);
5448
5449 tmp_msdu = mon_mpdu->head;
5450 while (tmp_msdu) {
5451 skb_next = tmp_msdu->next;
5452 dev_kfree_skb_any(tmp_msdu);
5453 tmp_msdu = skb_next;
5454 }
5455
5456 kfree(mon_mpdu);
5457 }
5458 }
5459
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5460 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5461 int mac_id,
5462 struct ath11k_mon_data *pmon,
5463 struct napi_struct *napi)
5464 {
5465 struct ath11k_pdev_mon_stats *rx_mon_stats;
5466 struct dp_full_mon_mpdu *tmp;
5467 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5468 struct sk_buff *head_msdu, *tail_msdu;
5469 struct ath11k_base *ab = ar->ab;
5470 struct ath11k_dp *dp = &ab->dp;
5471 int ret;
5472
5473 rx_mon_stats = &pmon->rx_mon_stats;
5474
5475 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5476 list_del(&mon_mpdu->list);
5477 head_msdu = mon_mpdu->head;
5478 tail_msdu = mon_mpdu->tail;
5479 if (head_msdu && tail_msdu) {
5480 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5481 &pmon->mon_ppdu_info,
5482 tail_msdu, napi);
5483 rx_mon_stats->dest_mpdu_done++;
5484 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5485 }
5486 kfree(mon_mpdu);
5487 }
5488
5489 return ret;
5490 }
5491
5492 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5493 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5494 struct napi_struct *napi, int budget)
5495 {
5496 struct ath11k *ar = ab->pdevs[mac_id].ar;
5497 struct ath11k_pdev_dp *dp = &ar->dp;
5498 struct ath11k_mon_data *pmon = &dp->mon_data;
5499 struct hal_sw_mon_ring_entries *sw_mon_entries;
5500 int quota = 0, work = 0, count;
5501
5502 sw_mon_entries = &pmon->sw_mon_entries;
5503
5504 while (pmon->hold_mon_dst_ring) {
5505 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5506 napi, 1);
5507 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5508 count = sw_mon_entries->status_buf_count;
5509 if (count > 1) {
5510 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5511 napi, count);
5512 }
5513
5514 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5515 pmon, napi);
5516 pmon->hold_mon_dst_ring = false;
5517 } else if (!pmon->mon_status_paddr ||
5518 pmon->buf_state == DP_MON_STATUS_LEAD) {
5519 sw_mon_entries->drop_ppdu = true;
5520 pmon->hold_mon_dst_ring = false;
5521 }
5522
5523 if (!quota)
5524 break;
5525
5526 work += quota;
5527 }
5528
5529 if (sw_mon_entries->drop_ppdu)
5530 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5531
5532 return work;
5533 }
5534
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5535 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5536 struct napi_struct *napi, int budget)
5537 {
5538 struct ath11k *ar = ab->pdevs[mac_id].ar;
5539 struct ath11k_pdev_dp *dp = &ar->dp;
5540 struct ath11k_mon_data *pmon = &dp->mon_data;
5541 struct hal_sw_mon_ring_entries *sw_mon_entries;
5542 struct ath11k_pdev_mon_stats *rx_mon_stats;
5543 struct sk_buff *head_msdu, *tail_msdu;
5544 void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5545 void *ring_entry;
5546 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5547 int quota = 0, ret;
5548 bool break_dst_ring = false;
5549
5550 spin_lock_bh(&pmon->mon_lock);
5551
5552 sw_mon_entries = &pmon->sw_mon_entries;
5553 rx_mon_stats = &pmon->rx_mon_stats;
5554
5555 if (pmon->hold_mon_dst_ring) {
5556 spin_unlock_bh(&pmon->mon_lock);
5557 goto reap_status_ring;
5558 }
5559
5560 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5561 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5562 head_msdu = NULL;
5563 tail_msdu = NULL;
5564
5565 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5566 &head_msdu,
5567 &tail_msdu,
5568 sw_mon_entries);
5569 rx_bufs_used += mpdu_rx_bufs_used;
5570
5571 if (!sw_mon_entries->end_of_ppdu) {
5572 if (head_msdu) {
5573 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5574 pmon->mon_mpdu,
5575 head_msdu,
5576 tail_msdu);
5577 if (ret)
5578 break_dst_ring = true;
5579 }
5580
5581 goto next_entry;
5582 } else {
5583 if (!sw_mon_entries->ppdu_id &&
5584 !sw_mon_entries->mon_status_paddr) {
5585 break_dst_ring = true;
5586 goto next_entry;
5587 }
5588 }
5589
5590 rx_mon_stats->dest_ppdu_done++;
5591 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5592 pmon->buf_state = DP_MON_STATUS_LAG;
5593 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5594 pmon->hold_mon_dst_ring = true;
5595 next_entry:
5596 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5597 mon_dst_srng);
5598 if (break_dst_ring)
5599 break;
5600 }
5601
5602 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5603 spin_unlock_bh(&pmon->mon_lock);
5604
5605 if (rx_bufs_used) {
5606 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5607 &dp->rxdma_mon_buf_ring,
5608 rx_bufs_used,
5609 HAL_RX_BUF_RBM_SW3_BM);
5610 }
5611
5612 reap_status_ring:
5613 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5614 napi, budget);
5615
5616 return quota;
5617 }
5618
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5619 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5620 struct napi_struct *napi, int budget)
5621 {
5622 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5623 int ret = 0;
5624
5625 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5626 ab->hw_params.full_monitor_mode)
5627 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5628 else
5629 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5630
5631 return ret;
5632 }
5633
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5634 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5635 {
5636 struct ath11k_pdev_dp *dp = &ar->dp;
5637 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5638
5639 skb_queue_head_init(&pmon->rx_status_q);
5640
5641 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5642
5643 memset(&pmon->rx_mon_stats, 0,
5644 sizeof(pmon->rx_mon_stats));
5645 return 0;
5646 }
5647
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5648 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5649 {
5650 struct ath11k_pdev_dp *dp = &ar->dp;
5651 struct ath11k_mon_data *pmon = &dp->mon_data;
5652 struct hal_srng *mon_desc_srng = NULL;
5653 struct dp_srng *dp_srng;
5654 int ret = 0;
5655 u32 n_link_desc = 0;
5656
5657 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5658 if (ret) {
5659 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5660 return ret;
5661 }
5662
5663 /* if rxdma1_enable is false, no need to setup
5664 * rxdma_mon_desc_ring.
5665 */
5666 if (!ar->ab->hw_params.rxdma1_enable)
5667 return 0;
5668
5669 dp_srng = &dp->rxdma_mon_desc_ring;
5670 n_link_desc = dp_srng->size /
5671 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5672 mon_desc_srng =
5673 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5674
5675 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5676 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5677 n_link_desc);
5678 if (ret) {
5679 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5680 return ret;
5681 }
5682 pmon->mon_last_linkdesc_paddr = 0;
5683 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5684 spin_lock_init(&pmon->mon_lock);
5685
5686 return 0;
5687 }
5688
ath11k_dp_mon_link_free(struct ath11k * ar)5689 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5690 {
5691 struct ath11k_pdev_dp *dp = &ar->dp;
5692 struct ath11k_mon_data *pmon = &dp->mon_data;
5693
5694 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5695 HAL_RXDMA_MONITOR_DESC,
5696 &dp->rxdma_mon_desc_ring);
5697 return 0;
5698 }
5699
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5700 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5701 {
5702 ath11k_dp_mon_link_free(ar);
5703 return 0;
5704 }
5705
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5706 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5707 {
5708 /* start reap timer */
5709 mod_timer(&ab->mon_reap_timer,
5710 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5711
5712 return 0;
5713 }
5714
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5715 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5716 {
5717 int ret;
5718
5719 if (stop_timer)
5720 del_timer_sync(&ab->mon_reap_timer);
5721
5722 /* reap all the monitor related rings */
5723 ret = ath11k_dp_purge_mon_ring(ab);
5724 if (ret) {
5725 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5726 return ret;
5727 }
5728
5729 return 0;
5730 }
5731