1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Test driver to test endpoint functionality
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/pci_ids.h>
16 #include <linux/random.h>
17
18 #include <linux/pci-epc.h>
19 #include <linux/pci-epf.h>
20 #include <linux/pci_regs.h>
21
22 #define IRQ_TYPE_LEGACY 0
23 #define IRQ_TYPE_MSI 1
24 #define IRQ_TYPE_MSIX 2
25
26 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
27 #define COMMAND_RAISE_MSI_IRQ BIT(1)
28 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
29 #define COMMAND_READ BIT(3)
30 #define COMMAND_WRITE BIT(4)
31 #define COMMAND_COPY BIT(5)
32
33 #define STATUS_READ_SUCCESS BIT(0)
34 #define STATUS_READ_FAIL BIT(1)
35 #define STATUS_WRITE_SUCCESS BIT(2)
36 #define STATUS_WRITE_FAIL BIT(3)
37 #define STATUS_COPY_SUCCESS BIT(4)
38 #define STATUS_COPY_FAIL BIT(5)
39 #define STATUS_IRQ_RAISED BIT(6)
40 #define STATUS_SRC_ADDR_INVALID BIT(7)
41 #define STATUS_DST_ADDR_INVALID BIT(8)
42
43 #define FLAG_USE_DMA BIT(0)
44
45 #define TIMER_RESOLUTION 1
46
47 static struct workqueue_struct *kpcitest_workqueue;
48
49 struct pci_epf_test {
50 void *reg[PCI_STD_NUM_BARS];
51 struct pci_epf *epf;
52 enum pci_barno test_reg_bar;
53 size_t msix_table_offset;
54 struct delayed_work cmd_handler;
55 struct dma_chan *dma_chan_tx;
56 struct dma_chan *dma_chan_rx;
57 struct dma_chan *transfer_chan;
58 dma_cookie_t transfer_cookie;
59 enum dma_status transfer_status;
60 struct completion transfer_complete;
61 bool dma_supported;
62 bool dma_private;
63 const struct pci_epc_features *epc_features;
64 };
65
66 struct pci_epf_test_reg {
67 u32 magic;
68 u32 command;
69 u32 status;
70 u64 src_addr;
71 u64 dst_addr;
72 u32 size;
73 u32 checksum;
74 u32 irq_type;
75 u32 irq_number;
76 u32 flags;
77 } __packed;
78
79 static struct pci_epf_header test_header = {
80 .vendorid = PCI_ANY_ID,
81 .deviceid = PCI_ANY_ID,
82 .baseclass_code = PCI_CLASS_OTHERS,
83 .interrupt_pin = PCI_INTERRUPT_INTA,
84 };
85
86 static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
87
pci_epf_test_dma_callback(void * param)88 static void pci_epf_test_dma_callback(void *param)
89 {
90 struct pci_epf_test *epf_test = param;
91 struct dma_tx_state state;
92
93 epf_test->transfer_status =
94 dmaengine_tx_status(epf_test->transfer_chan,
95 epf_test->transfer_cookie, &state);
96 if (epf_test->transfer_status == DMA_COMPLETE ||
97 epf_test->transfer_status == DMA_ERROR)
98 complete(&epf_test->transfer_complete);
99 }
100
101 /**
102 * pci_epf_test_data_transfer() - Function that uses dmaengine API to transfer
103 * data between PCIe EP and remote PCIe RC
104 * @epf_test: the EPF test device that performs the data transfer operation
105 * @dma_dst: The destination address of the data transfer. It can be a physical
106 * address given by pci_epc_mem_alloc_addr or DMA mapping APIs.
107 * @dma_src: The source address of the data transfer. It can be a physical
108 * address given by pci_epc_mem_alloc_addr or DMA mapping APIs.
109 * @len: The size of the data transfer
110 * @dma_remote: remote RC physical address
111 * @dir: DMA transfer direction
112 *
113 * Function that uses dmaengine API to transfer data between PCIe EP and remote
114 * PCIe RC. The source and destination address can be a physical address given
115 * by pci_epc_mem_alloc_addr or the one obtained using DMA mapping APIs.
116 *
117 * The function returns '0' on success and negative value on failure.
118 */
pci_epf_test_data_transfer(struct pci_epf_test * epf_test,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len,dma_addr_t dma_remote,enum dma_transfer_direction dir)119 static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test,
120 dma_addr_t dma_dst, dma_addr_t dma_src,
121 size_t len, dma_addr_t dma_remote,
122 enum dma_transfer_direction dir)
123 {
124 struct dma_chan *chan = (dir == DMA_MEM_TO_DEV) ?
125 epf_test->dma_chan_tx : epf_test->dma_chan_rx;
126 dma_addr_t dma_local = (dir == DMA_MEM_TO_DEV) ? dma_src : dma_dst;
127 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
128 struct pci_epf *epf = epf_test->epf;
129 struct dma_async_tx_descriptor *tx;
130 struct dma_slave_config sconf = {};
131 struct device *dev = &epf->dev;
132 int ret;
133
134 if (IS_ERR_OR_NULL(chan)) {
135 dev_err(dev, "Invalid DMA memcpy channel\n");
136 return -EINVAL;
137 }
138
139 if (epf_test->dma_private) {
140 sconf.direction = dir;
141 if (dir == DMA_MEM_TO_DEV)
142 sconf.dst_addr = dma_remote;
143 else
144 sconf.src_addr = dma_remote;
145
146 if (dmaengine_slave_config(chan, &sconf)) {
147 dev_err(dev, "DMA slave config fail\n");
148 return -EIO;
149 }
150 tx = dmaengine_prep_slave_single(chan, dma_local, len, dir,
151 flags);
152 } else {
153 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len,
154 flags);
155 }
156
157 if (!tx) {
158 dev_err(dev, "Failed to prepare DMA memcpy\n");
159 return -EIO;
160 }
161
162 reinit_completion(&epf_test->transfer_complete);
163 epf_test->transfer_chan = chan;
164 tx->callback = pci_epf_test_dma_callback;
165 tx->callback_param = epf_test;
166 epf_test->transfer_cookie = tx->tx_submit(tx);
167
168 ret = dma_submit_error(epf_test->transfer_cookie);
169 if (ret) {
170 dev_err(dev, "Failed to do DMA tx_submit %d\n", ret);
171 goto terminate;
172 }
173
174 dma_async_issue_pending(chan);
175 ret = wait_for_completion_interruptible(&epf_test->transfer_complete);
176 if (ret < 0) {
177 dev_err(dev, "DMA wait_for_completion interrupted\n");
178 goto terminate;
179 }
180
181 if (epf_test->transfer_status == DMA_ERROR) {
182 dev_err(dev, "DMA transfer failed\n");
183 ret = -EIO;
184 }
185
186 terminate:
187 dmaengine_terminate_sync(chan);
188
189 return ret;
190 }
191
192 struct epf_dma_filter {
193 struct device *dev;
194 u32 dma_mask;
195 };
196
epf_dma_filter_fn(struct dma_chan * chan,void * node)197 static bool epf_dma_filter_fn(struct dma_chan *chan, void *node)
198 {
199 struct epf_dma_filter *filter = node;
200 struct dma_slave_caps caps;
201
202 memset(&caps, 0, sizeof(caps));
203 dma_get_slave_caps(chan, &caps);
204
205 return chan->device->dev == filter->dev
206 && (filter->dma_mask & caps.directions);
207 }
208
209 /**
210 * pci_epf_test_init_dma_chan() - Function to initialize EPF test DMA channel
211 * @epf_test: the EPF test device that performs data transfer operation
212 *
213 * Function to initialize EPF test DMA channel.
214 */
pci_epf_test_init_dma_chan(struct pci_epf_test * epf_test)215 static int pci_epf_test_init_dma_chan(struct pci_epf_test *epf_test)
216 {
217 struct pci_epf *epf = epf_test->epf;
218 struct device *dev = &epf->dev;
219 struct epf_dma_filter filter;
220 struct dma_chan *dma_chan;
221 dma_cap_mask_t mask;
222 int ret;
223
224 filter.dev = epf->epc->dev.parent;
225 filter.dma_mask = BIT(DMA_DEV_TO_MEM);
226
227 dma_cap_zero(mask);
228 dma_cap_set(DMA_SLAVE, mask);
229 dma_chan = dma_request_channel(mask, epf_dma_filter_fn, &filter);
230 if (!dma_chan) {
231 dev_info(dev, "Failed to get private DMA rx channel. Falling back to generic one\n");
232 goto fail_back_tx;
233 }
234
235 epf_test->dma_chan_rx = dma_chan;
236
237 filter.dma_mask = BIT(DMA_MEM_TO_DEV);
238 dma_chan = dma_request_channel(mask, epf_dma_filter_fn, &filter);
239
240 if (!dma_chan) {
241 dev_info(dev, "Failed to get private DMA tx channel. Falling back to generic one\n");
242 goto fail_back_rx;
243 }
244
245 epf_test->dma_chan_tx = dma_chan;
246 epf_test->dma_private = true;
247
248 init_completion(&epf_test->transfer_complete);
249
250 return 0;
251
252 fail_back_rx:
253 dma_release_channel(epf_test->dma_chan_rx);
254 epf_test->dma_chan_tx = NULL;
255
256 fail_back_tx:
257 dma_cap_zero(mask);
258 dma_cap_set(DMA_MEMCPY, mask);
259
260 dma_chan = dma_request_chan_by_mask(&mask);
261 if (IS_ERR(dma_chan)) {
262 ret = PTR_ERR(dma_chan);
263 if (ret != -EPROBE_DEFER)
264 dev_err(dev, "Failed to get DMA channel\n");
265 return ret;
266 }
267 init_completion(&epf_test->transfer_complete);
268
269 epf_test->dma_chan_tx = epf_test->dma_chan_rx = dma_chan;
270
271 return 0;
272 }
273
274 /**
275 * pci_epf_test_clean_dma_chan() - Function to cleanup EPF test DMA channel
276 * @epf_test: the EPF test device that performs data transfer operation
277 *
278 * Helper to cleanup EPF test DMA channel.
279 */
pci_epf_test_clean_dma_chan(struct pci_epf_test * epf_test)280 static void pci_epf_test_clean_dma_chan(struct pci_epf_test *epf_test)
281 {
282 if (!epf_test->dma_supported)
283 return;
284
285 dma_release_channel(epf_test->dma_chan_tx);
286 if (epf_test->dma_chan_tx == epf_test->dma_chan_rx) {
287 epf_test->dma_chan_tx = NULL;
288 epf_test->dma_chan_rx = NULL;
289 return;
290 }
291
292 dma_release_channel(epf_test->dma_chan_rx);
293 epf_test->dma_chan_rx = NULL;
294
295 return;
296 }
297
pci_epf_test_print_rate(const char * ops,u64 size,struct timespec64 * start,struct timespec64 * end,bool dma)298 static void pci_epf_test_print_rate(const char *ops, u64 size,
299 struct timespec64 *start,
300 struct timespec64 *end, bool dma)
301 {
302 struct timespec64 ts;
303 u64 rate, ns;
304
305 ts = timespec64_sub(*end, *start);
306
307 /* convert both size (stored in 'rate') and time in terms of 'ns' */
308 ns = timespec64_to_ns(&ts);
309 rate = size * NSEC_PER_SEC;
310
311 /* Divide both size (stored in 'rate') and ns by a common factor */
312 while (ns > UINT_MAX) {
313 rate >>= 1;
314 ns >>= 1;
315 }
316
317 if (!ns)
318 return;
319
320 /* calculate the rate */
321 do_div(rate, (uint32_t)ns);
322
323 pr_info("\n%s => Size: %llu bytes\t DMA: %s\t Time: %llu.%09u seconds\t"
324 "Rate: %llu KB/s\n", ops, size, dma ? "YES" : "NO",
325 (u64)ts.tv_sec, (u32)ts.tv_nsec, rate / 1024);
326 }
327
pci_epf_test_copy(struct pci_epf_test * epf_test)328 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
329 {
330 int ret;
331 bool use_dma;
332 void __iomem *src_addr;
333 void __iomem *dst_addr;
334 phys_addr_t src_phys_addr;
335 phys_addr_t dst_phys_addr;
336 struct timespec64 start, end;
337 struct pci_epf *epf = epf_test->epf;
338 struct device *dev = &epf->dev;
339 struct pci_epc *epc = epf->epc;
340 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
341 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
342
343 src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
344 if (!src_addr) {
345 dev_err(dev, "Failed to allocate source address\n");
346 reg->status = STATUS_SRC_ADDR_INVALID;
347 ret = -ENOMEM;
348 goto err;
349 }
350
351 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr,
352 reg->src_addr, reg->size);
353 if (ret) {
354 dev_err(dev, "Failed to map source address\n");
355 reg->status = STATUS_SRC_ADDR_INVALID;
356 goto err_src_addr;
357 }
358
359 dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
360 if (!dst_addr) {
361 dev_err(dev, "Failed to allocate destination address\n");
362 reg->status = STATUS_DST_ADDR_INVALID;
363 ret = -ENOMEM;
364 goto err_src_map_addr;
365 }
366
367 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr,
368 reg->dst_addr, reg->size);
369 if (ret) {
370 dev_err(dev, "Failed to map destination address\n");
371 reg->status = STATUS_DST_ADDR_INVALID;
372 goto err_dst_addr;
373 }
374
375 ktime_get_ts64(&start);
376 use_dma = !!(reg->flags & FLAG_USE_DMA);
377 if (use_dma) {
378 if (!epf_test->dma_supported) {
379 dev_err(dev, "Cannot transfer data using DMA\n");
380 ret = -EINVAL;
381 goto err_map_addr;
382 }
383
384 if (epf_test->dma_private) {
385 dev_err(dev, "Cannot transfer data using DMA\n");
386 ret = -EINVAL;
387 goto err_map_addr;
388 }
389
390 ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr,
391 src_phys_addr, reg->size, 0,
392 DMA_MEM_TO_MEM);
393 if (ret)
394 dev_err(dev, "Data transfer failed\n");
395 } else {
396 void *buf;
397
398 buf = kzalloc(reg->size, GFP_KERNEL);
399 if (!buf) {
400 ret = -ENOMEM;
401 goto err_map_addr;
402 }
403
404 memcpy_fromio(buf, src_addr, reg->size);
405 memcpy_toio(dst_addr, buf, reg->size);
406 kfree(buf);
407 }
408 ktime_get_ts64(&end);
409 pci_epf_test_print_rate("COPY", reg->size, &start, &end, use_dma);
410
411 err_map_addr:
412 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr);
413
414 err_dst_addr:
415 pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
416
417 err_src_map_addr:
418 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr);
419
420 err_src_addr:
421 pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
422
423 err:
424 return ret;
425 }
426
pci_epf_test_read(struct pci_epf_test * epf_test)427 static int pci_epf_test_read(struct pci_epf_test *epf_test)
428 {
429 int ret;
430 void __iomem *src_addr;
431 void *buf;
432 u32 crc32;
433 bool use_dma;
434 phys_addr_t phys_addr;
435 phys_addr_t dst_phys_addr;
436 struct timespec64 start, end;
437 struct pci_epf *epf = epf_test->epf;
438 struct device *dev = &epf->dev;
439 struct pci_epc *epc = epf->epc;
440 struct device *dma_dev = epf->epc->dev.parent;
441 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
442 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
443
444 src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
445 if (!src_addr) {
446 dev_err(dev, "Failed to allocate address\n");
447 reg->status = STATUS_SRC_ADDR_INVALID;
448 ret = -ENOMEM;
449 goto err;
450 }
451
452 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr,
453 reg->src_addr, reg->size);
454 if (ret) {
455 dev_err(dev, "Failed to map address\n");
456 reg->status = STATUS_SRC_ADDR_INVALID;
457 goto err_addr;
458 }
459
460 buf = kzalloc(reg->size, GFP_KERNEL);
461 if (!buf) {
462 ret = -ENOMEM;
463 goto err_map_addr;
464 }
465
466 use_dma = !!(reg->flags & FLAG_USE_DMA);
467 if (use_dma) {
468 if (!epf_test->dma_supported) {
469 dev_err(dev, "Cannot transfer data using DMA\n");
470 ret = -EINVAL;
471 goto err_dma_map;
472 }
473
474 dst_phys_addr = dma_map_single(dma_dev, buf, reg->size,
475 DMA_FROM_DEVICE);
476 if (dma_mapping_error(dma_dev, dst_phys_addr)) {
477 dev_err(dev, "Failed to map destination buffer addr\n");
478 ret = -ENOMEM;
479 goto err_dma_map;
480 }
481
482 ktime_get_ts64(&start);
483 ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr,
484 phys_addr, reg->size,
485 reg->src_addr, DMA_DEV_TO_MEM);
486 if (ret)
487 dev_err(dev, "Data transfer failed\n");
488 ktime_get_ts64(&end);
489
490 dma_unmap_single(dma_dev, dst_phys_addr, reg->size,
491 DMA_FROM_DEVICE);
492 } else {
493 ktime_get_ts64(&start);
494 memcpy_fromio(buf, src_addr, reg->size);
495 ktime_get_ts64(&end);
496 }
497
498 pci_epf_test_print_rate("READ", reg->size, &start, &end, use_dma);
499
500 crc32 = crc32_le(~0, buf, reg->size);
501 if (crc32 != reg->checksum)
502 ret = -EIO;
503
504 err_dma_map:
505 kfree(buf);
506
507 err_map_addr:
508 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr);
509
510 err_addr:
511 pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
512
513 err:
514 return ret;
515 }
516
pci_epf_test_write(struct pci_epf_test * epf_test)517 static int pci_epf_test_write(struct pci_epf_test *epf_test)
518 {
519 int ret;
520 void __iomem *dst_addr;
521 void *buf;
522 bool use_dma;
523 phys_addr_t phys_addr;
524 phys_addr_t src_phys_addr;
525 struct timespec64 start, end;
526 struct pci_epf *epf = epf_test->epf;
527 struct device *dev = &epf->dev;
528 struct pci_epc *epc = epf->epc;
529 struct device *dma_dev = epf->epc->dev.parent;
530 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
531 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
532
533 dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
534 if (!dst_addr) {
535 dev_err(dev, "Failed to allocate address\n");
536 reg->status = STATUS_DST_ADDR_INVALID;
537 ret = -ENOMEM;
538 goto err;
539 }
540
541 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr,
542 reg->dst_addr, reg->size);
543 if (ret) {
544 dev_err(dev, "Failed to map address\n");
545 reg->status = STATUS_DST_ADDR_INVALID;
546 goto err_addr;
547 }
548
549 buf = kzalloc(reg->size, GFP_KERNEL);
550 if (!buf) {
551 ret = -ENOMEM;
552 goto err_map_addr;
553 }
554
555 get_random_bytes(buf, reg->size);
556 reg->checksum = crc32_le(~0, buf, reg->size);
557
558 use_dma = !!(reg->flags & FLAG_USE_DMA);
559 if (use_dma) {
560 if (!epf_test->dma_supported) {
561 dev_err(dev, "Cannot transfer data using DMA\n");
562 ret = -EINVAL;
563 goto err_dma_map;
564 }
565
566 src_phys_addr = dma_map_single(dma_dev, buf, reg->size,
567 DMA_TO_DEVICE);
568 if (dma_mapping_error(dma_dev, src_phys_addr)) {
569 dev_err(dev, "Failed to map source buffer addr\n");
570 ret = -ENOMEM;
571 goto err_dma_map;
572 }
573
574 ktime_get_ts64(&start);
575
576 ret = pci_epf_test_data_transfer(epf_test, phys_addr,
577 src_phys_addr, reg->size,
578 reg->dst_addr,
579 DMA_MEM_TO_DEV);
580 if (ret)
581 dev_err(dev, "Data transfer failed\n");
582 ktime_get_ts64(&end);
583
584 dma_unmap_single(dma_dev, src_phys_addr, reg->size,
585 DMA_TO_DEVICE);
586 } else {
587 ktime_get_ts64(&start);
588 memcpy_toio(dst_addr, buf, reg->size);
589 ktime_get_ts64(&end);
590 }
591
592 pci_epf_test_print_rate("WRITE", reg->size, &start, &end, use_dma);
593
594 /*
595 * wait 1ms inorder for the write to complete. Without this delay L3
596 * error in observed in the host system.
597 */
598 usleep_range(1000, 2000);
599
600 err_dma_map:
601 kfree(buf);
602
603 err_map_addr:
604 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr);
605
606 err_addr:
607 pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
608
609 err:
610 return ret;
611 }
612
pci_epf_test_raise_irq(struct pci_epf_test * epf_test,u8 irq_type,u16 irq)613 static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
614 u16 irq)
615 {
616 struct pci_epf *epf = epf_test->epf;
617 struct device *dev = &epf->dev;
618 struct pci_epc *epc = epf->epc;
619 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
620 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
621
622 reg->status |= STATUS_IRQ_RAISED;
623
624 switch (irq_type) {
625 case IRQ_TYPE_LEGACY:
626 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
627 PCI_EPC_IRQ_LEGACY, 0);
628 break;
629 case IRQ_TYPE_MSI:
630 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
631 PCI_EPC_IRQ_MSI, irq);
632 break;
633 case IRQ_TYPE_MSIX:
634 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
635 PCI_EPC_IRQ_MSIX, irq);
636 break;
637 default:
638 dev_err(dev, "Failed to raise IRQ, unknown type\n");
639 break;
640 }
641 }
642
pci_epf_test_cmd_handler(struct work_struct * work)643 static void pci_epf_test_cmd_handler(struct work_struct *work)
644 {
645 int ret;
646 int count;
647 u32 command;
648 struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
649 cmd_handler.work);
650 struct pci_epf *epf = epf_test->epf;
651 struct device *dev = &epf->dev;
652 struct pci_epc *epc = epf->epc;
653 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
654 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
655
656 command = reg->command;
657 if (!command)
658 goto reset_handler;
659
660 reg->command = 0;
661 reg->status = 0;
662
663 if (reg->irq_type > IRQ_TYPE_MSIX) {
664 dev_err(dev, "Failed to detect IRQ type\n");
665 goto reset_handler;
666 }
667
668 if (command & COMMAND_RAISE_LEGACY_IRQ) {
669 reg->status = STATUS_IRQ_RAISED;
670 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
671 PCI_EPC_IRQ_LEGACY, 0);
672 goto reset_handler;
673 }
674
675 if (command & COMMAND_WRITE) {
676 ret = pci_epf_test_write(epf_test);
677 if (ret)
678 reg->status |= STATUS_WRITE_FAIL;
679 else
680 reg->status |= STATUS_WRITE_SUCCESS;
681 pci_epf_test_raise_irq(epf_test, reg->irq_type,
682 reg->irq_number);
683 goto reset_handler;
684 }
685
686 if (command & COMMAND_READ) {
687 ret = pci_epf_test_read(epf_test);
688 if (!ret)
689 reg->status |= STATUS_READ_SUCCESS;
690 else
691 reg->status |= STATUS_READ_FAIL;
692 pci_epf_test_raise_irq(epf_test, reg->irq_type,
693 reg->irq_number);
694 goto reset_handler;
695 }
696
697 if (command & COMMAND_COPY) {
698 ret = pci_epf_test_copy(epf_test);
699 if (!ret)
700 reg->status |= STATUS_COPY_SUCCESS;
701 else
702 reg->status |= STATUS_COPY_FAIL;
703 pci_epf_test_raise_irq(epf_test, reg->irq_type,
704 reg->irq_number);
705 goto reset_handler;
706 }
707
708 if (command & COMMAND_RAISE_MSI_IRQ) {
709 count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
710 if (reg->irq_number > count || count <= 0)
711 goto reset_handler;
712 reg->status = STATUS_IRQ_RAISED;
713 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
714 PCI_EPC_IRQ_MSI, reg->irq_number);
715 goto reset_handler;
716 }
717
718 if (command & COMMAND_RAISE_MSIX_IRQ) {
719 count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
720 if (reg->irq_number > count || count <= 0)
721 goto reset_handler;
722 reg->status = STATUS_IRQ_RAISED;
723 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
724 PCI_EPC_IRQ_MSIX, reg->irq_number);
725 goto reset_handler;
726 }
727
728 reset_handler:
729 queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
730 msecs_to_jiffies(1));
731 }
732
pci_epf_test_unbind(struct pci_epf * epf)733 static void pci_epf_test_unbind(struct pci_epf *epf)
734 {
735 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
736 struct pci_epc *epc = epf->epc;
737 struct pci_epf_bar *epf_bar;
738 int bar;
739
740 cancel_delayed_work(&epf_test->cmd_handler);
741 pci_epf_test_clean_dma_chan(epf_test);
742 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
743 epf_bar = &epf->bar[bar];
744
745 if (epf_test->reg[bar]) {
746 pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no,
747 epf_bar);
748 pci_epf_free_space(epf, epf_test->reg[bar], bar,
749 PRIMARY_INTERFACE);
750 }
751 }
752 }
753
pci_epf_test_set_bar(struct pci_epf * epf)754 static int pci_epf_test_set_bar(struct pci_epf *epf)
755 {
756 int bar, add;
757 int ret;
758 struct pci_epf_bar *epf_bar;
759 struct pci_epc *epc = epf->epc;
760 struct device *dev = &epf->dev;
761 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
762 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
763 const struct pci_epc_features *epc_features;
764
765 epc_features = epf_test->epc_features;
766
767 for (bar = 0; bar < PCI_STD_NUM_BARS; bar += add) {
768 epf_bar = &epf->bar[bar];
769 /*
770 * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
771 * if the specific implementation required a 64-bit BAR,
772 * even if we only requested a 32-bit BAR.
773 */
774 add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
775
776 if (!!(epc_features->reserved_bar & (1 << bar)))
777 continue;
778
779 ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no,
780 epf_bar);
781 if (ret) {
782 pci_epf_free_space(epf, epf_test->reg[bar], bar,
783 PRIMARY_INTERFACE);
784 dev_err(dev, "Failed to set BAR%d\n", bar);
785 if (bar == test_reg_bar)
786 return ret;
787 }
788 }
789
790 return 0;
791 }
792
pci_epf_test_core_init(struct pci_epf * epf)793 static int pci_epf_test_core_init(struct pci_epf *epf)
794 {
795 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
796 struct pci_epf_header *header = epf->header;
797 const struct pci_epc_features *epc_features;
798 struct pci_epc *epc = epf->epc;
799 struct device *dev = &epf->dev;
800 bool msix_capable = false;
801 bool msi_capable = true;
802 int ret;
803
804 epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no);
805 if (epc_features) {
806 msix_capable = epc_features->msix_capable;
807 msi_capable = epc_features->msi_capable;
808 }
809
810 if (epf->vfunc_no <= 1) {
811 ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, header);
812 if (ret) {
813 dev_err(dev, "Configuration header write failed\n");
814 return ret;
815 }
816 }
817
818 ret = pci_epf_test_set_bar(epf);
819 if (ret)
820 return ret;
821
822 if (msi_capable) {
823 ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
824 epf->msi_interrupts);
825 if (ret) {
826 dev_err(dev, "MSI configuration failed\n");
827 return ret;
828 }
829 }
830
831 if (msix_capable) {
832 ret = pci_epc_set_msix(epc, epf->func_no, epf->vfunc_no,
833 epf->msix_interrupts,
834 epf_test->test_reg_bar,
835 epf_test->msix_table_offset);
836 if (ret) {
837 dev_err(dev, "MSI-X configuration failed\n");
838 return ret;
839 }
840 }
841
842 return 0;
843 }
844
pci_epf_test_notifier(struct notifier_block * nb,unsigned long val,void * data)845 static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
846 void *data)
847 {
848 struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
849 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
850 int ret;
851
852 switch (val) {
853 case CORE_INIT:
854 ret = pci_epf_test_core_init(epf);
855 if (ret)
856 return NOTIFY_BAD;
857 break;
858
859 case LINK_UP:
860 queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
861 msecs_to_jiffies(1));
862 break;
863
864 default:
865 dev_err(&epf->dev, "Invalid EPF test notifier event\n");
866 return NOTIFY_BAD;
867 }
868
869 return NOTIFY_OK;
870 }
871
pci_epf_test_alloc_space(struct pci_epf * epf)872 static int pci_epf_test_alloc_space(struct pci_epf *epf)
873 {
874 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
875 struct device *dev = &epf->dev;
876 struct pci_epf_bar *epf_bar;
877 size_t msix_table_size = 0;
878 size_t test_reg_bar_size;
879 size_t pba_size = 0;
880 bool msix_capable;
881 void *base;
882 int bar, add;
883 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
884 const struct pci_epc_features *epc_features;
885 size_t test_reg_size;
886
887 epc_features = epf_test->epc_features;
888
889 test_reg_bar_size = ALIGN(sizeof(struct pci_epf_test_reg), 128);
890
891 msix_capable = epc_features->msix_capable;
892 if (msix_capable) {
893 msix_table_size = PCI_MSIX_ENTRY_SIZE * epf->msix_interrupts;
894 epf_test->msix_table_offset = test_reg_bar_size;
895 /* Align to QWORD or 8 Bytes */
896 pba_size = ALIGN(DIV_ROUND_UP(epf->msix_interrupts, 8), 8);
897 }
898 test_reg_size = test_reg_bar_size + msix_table_size + pba_size;
899
900 if (epc_features->bar_fixed_size[test_reg_bar]) {
901 if (test_reg_size > bar_size[test_reg_bar])
902 return -ENOMEM;
903 test_reg_size = bar_size[test_reg_bar];
904 }
905
906 base = pci_epf_alloc_space(epf, test_reg_size, test_reg_bar,
907 epc_features->align, PRIMARY_INTERFACE);
908 if (!base) {
909 dev_err(dev, "Failed to allocated register space\n");
910 return -ENOMEM;
911 }
912 epf_test->reg[test_reg_bar] = base;
913
914 for (bar = 0; bar < PCI_STD_NUM_BARS; bar += add) {
915 epf_bar = &epf->bar[bar];
916 add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
917
918 if (bar == test_reg_bar)
919 continue;
920
921 if (!!(epc_features->reserved_bar & (1 << bar)))
922 continue;
923
924 base = pci_epf_alloc_space(epf, bar_size[bar], bar,
925 epc_features->align,
926 PRIMARY_INTERFACE);
927 if (!base)
928 dev_err(dev, "Failed to allocate space for BAR%d\n",
929 bar);
930 epf_test->reg[bar] = base;
931 }
932
933 return 0;
934 }
935
pci_epf_configure_bar(struct pci_epf * epf,const struct pci_epc_features * epc_features)936 static void pci_epf_configure_bar(struct pci_epf *epf,
937 const struct pci_epc_features *epc_features)
938 {
939 struct pci_epf_bar *epf_bar;
940 bool bar_fixed_64bit;
941 int i;
942
943 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
944 epf_bar = &epf->bar[i];
945 bar_fixed_64bit = !!(epc_features->bar_fixed_64bit & (1 << i));
946 if (bar_fixed_64bit)
947 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
948 if (epc_features->bar_fixed_size[i])
949 bar_size[i] = epc_features->bar_fixed_size[i];
950 }
951 }
952
pci_epf_test_bind(struct pci_epf * epf)953 static int pci_epf_test_bind(struct pci_epf *epf)
954 {
955 int ret;
956 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
957 const struct pci_epc_features *epc_features;
958 enum pci_barno test_reg_bar = BAR_0;
959 struct pci_epc *epc = epf->epc;
960 bool linkup_notifier = false;
961 bool core_init_notifier = false;
962
963 if (WARN_ON_ONCE(!epc))
964 return -EINVAL;
965
966 epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no);
967 if (!epc_features) {
968 dev_err(&epf->dev, "epc_features not implemented\n");
969 return -EOPNOTSUPP;
970 }
971
972 linkup_notifier = epc_features->linkup_notifier;
973 core_init_notifier = epc_features->core_init_notifier;
974 test_reg_bar = pci_epc_get_first_free_bar(epc_features);
975 if (test_reg_bar < 0)
976 return -EINVAL;
977 pci_epf_configure_bar(epf, epc_features);
978
979 epf_test->test_reg_bar = test_reg_bar;
980 epf_test->epc_features = epc_features;
981
982 ret = pci_epf_test_alloc_space(epf);
983 if (ret)
984 return ret;
985
986 if (!core_init_notifier) {
987 ret = pci_epf_test_core_init(epf);
988 if (ret)
989 return ret;
990 }
991
992 epf_test->dma_supported = true;
993
994 ret = pci_epf_test_init_dma_chan(epf_test);
995 if (ret)
996 epf_test->dma_supported = false;
997
998 if (linkup_notifier || core_init_notifier) {
999 epf->nb.notifier_call = pci_epf_test_notifier;
1000 pci_epc_register_notifier(epc, &epf->nb);
1001 } else {
1002 queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
1003 }
1004
1005 return 0;
1006 }
1007
1008 static const struct pci_epf_device_id pci_epf_test_ids[] = {
1009 {
1010 .name = "pci_epf_test",
1011 },
1012 {},
1013 };
1014
pci_epf_test_probe(struct pci_epf * epf)1015 static int pci_epf_test_probe(struct pci_epf *epf)
1016 {
1017 struct pci_epf_test *epf_test;
1018 struct device *dev = &epf->dev;
1019
1020 epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
1021 if (!epf_test)
1022 return -ENOMEM;
1023
1024 epf->header = &test_header;
1025 epf_test->epf = epf;
1026
1027 INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
1028
1029 epf_set_drvdata(epf, epf_test);
1030 return 0;
1031 }
1032
1033 static struct pci_epf_ops ops = {
1034 .unbind = pci_epf_test_unbind,
1035 .bind = pci_epf_test_bind,
1036 };
1037
1038 static struct pci_epf_driver test_driver = {
1039 .driver.name = "pci_epf_test",
1040 .probe = pci_epf_test_probe,
1041 .id_table = pci_epf_test_ids,
1042 .ops = &ops,
1043 .owner = THIS_MODULE,
1044 };
1045
pci_epf_test_init(void)1046 static int __init pci_epf_test_init(void)
1047 {
1048 int ret;
1049
1050 kpcitest_workqueue = alloc_workqueue("kpcitest",
1051 WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
1052 if (!kpcitest_workqueue) {
1053 pr_err("Failed to allocate the kpcitest work queue\n");
1054 return -ENOMEM;
1055 }
1056
1057 ret = pci_epf_register_driver(&test_driver);
1058 if (ret) {
1059 destroy_workqueue(kpcitest_workqueue);
1060 pr_err("Failed to register pci epf test driver --> %d\n", ret);
1061 return ret;
1062 }
1063
1064 return 0;
1065 }
1066 module_init(pci_epf_test_init);
1067
pci_epf_test_exit(void)1068 static void __exit pci_epf_test_exit(void)
1069 {
1070 if (kpcitest_workqueue)
1071 destroy_workqueue(kpcitest_workqueue);
1072 pci_epf_unregister_driver(&test_driver);
1073 }
1074 module_exit(pci_epf_test_exit);
1075
1076 MODULE_DESCRIPTION("PCI EPF TEST DRIVER");
1077 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1078 MODULE_LICENSE("GPL v2");
1079