1 /* bnx2x_cmn.c: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
17 *
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/etherdevice.h>
23 #include <linux/if_vlan.h>
24 #include <linux/interrupt.h>
25 #include <linux/ip.h>
26 #include <linux/crash_dump.h>
27 #include <net/tcp.h>
28 #include <net/gro.h>
29 #include <net/ipv6.h>
30 #include <net/ip6_checksum.h>
31 #include <linux/prefetch.h>
32 #include "bnx2x_cmn.h"
33 #include "bnx2x_init.h"
34 #include "bnx2x_sp.h"
35
36 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
37 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
38 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
39 static int bnx2x_poll(struct napi_struct *napi, int budget);
40
bnx2x_add_all_napi_cnic(struct bnx2x * bp)41 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
42 {
43 int i;
44
45 /* Add NAPI objects */
46 for_each_rx_queue_cnic(bp, i) {
47 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), bnx2x_poll);
48 }
49 }
50
bnx2x_add_all_napi(struct bnx2x * bp)51 static void bnx2x_add_all_napi(struct bnx2x *bp)
52 {
53 int i;
54
55 /* Add NAPI objects */
56 for_each_eth_queue(bp, i) {
57 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), bnx2x_poll);
58 }
59 }
60
bnx2x_calc_num_queues(struct bnx2x * bp)61 static int bnx2x_calc_num_queues(struct bnx2x *bp)
62 {
63 int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues();
64
65 /* Reduce memory usage in kdump environment by using only one queue */
66 if (is_kdump_kernel())
67 nq = 1;
68
69 nq = clamp(nq, 1, BNX2X_MAX_QUEUES(bp));
70 return nq;
71 }
72
73 /**
74 * bnx2x_move_fp - move content of the fastpath structure.
75 *
76 * @bp: driver handle
77 * @from: source FP index
78 * @to: destination FP index
79 *
80 * Makes sure the contents of the bp->fp[to].napi is kept
81 * intact. This is done by first copying the napi struct from
82 * the target to the source, and then mem copying the entire
83 * source onto the target. Update txdata pointers and related
84 * content.
85 */
bnx2x_move_fp(struct bnx2x * bp,int from,int to)86 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
87 {
88 struct bnx2x_fastpath *from_fp = &bp->fp[from];
89 struct bnx2x_fastpath *to_fp = &bp->fp[to];
90 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
91 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
92 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
93 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
94 int old_max_eth_txqs, new_max_eth_txqs;
95 int old_txdata_index = 0, new_txdata_index = 0;
96 struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
97
98 /* Copy the NAPI object as it has been already initialized */
99 from_fp->napi = to_fp->napi;
100
101 /* Move bnx2x_fastpath contents */
102 memcpy(to_fp, from_fp, sizeof(*to_fp));
103 to_fp->index = to;
104
105 /* Retain the tpa_info of the original `to' version as we don't want
106 * 2 FPs to contain the same tpa_info pointer.
107 */
108 to_fp->tpa_info = old_tpa_info;
109
110 /* move sp_objs contents as well, as their indices match fp ones */
111 memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
112
113 /* move fp_stats contents as well, as their indices match fp ones */
114 memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
115
116 /* Update txdata pointers in fp and move txdata content accordingly:
117 * Each fp consumes 'max_cos' txdata structures, so the index should be
118 * decremented by max_cos x delta.
119 */
120
121 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
122 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
123 (bp)->max_cos;
124 if (from == FCOE_IDX(bp)) {
125 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
126 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
127 }
128
129 memcpy(&bp->bnx2x_txq[new_txdata_index],
130 &bp->bnx2x_txq[old_txdata_index],
131 sizeof(struct bnx2x_fp_txdata));
132 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
133 }
134
135 /**
136 * bnx2x_fill_fw_str - Fill buffer with FW version string.
137 *
138 * @bp: driver handle
139 * @buf: character buffer to fill with the fw name
140 * @buf_len: length of the above buffer
141 *
142 */
bnx2x_fill_fw_str(struct bnx2x * bp,char * buf,size_t buf_len)143 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
144 {
145 if (IS_PF(bp)) {
146 u8 phy_fw_ver[PHY_FW_VER_LEN];
147
148 phy_fw_ver[0] = '\0';
149 bnx2x_get_ext_phy_fw_version(&bp->link_params,
150 phy_fw_ver, PHY_FW_VER_LEN);
151 strscpy(buf, bp->fw_ver, buf_len);
152 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
153 "bc %d.%d.%d%s%s",
154 (bp->common.bc_ver & 0xff0000) >> 16,
155 (bp->common.bc_ver & 0xff00) >> 8,
156 (bp->common.bc_ver & 0xff),
157 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
158 } else {
159 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
160 }
161 }
162
163 /**
164 * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
165 *
166 * @bp: driver handle
167 * @delta: number of eth queues which were not allocated
168 */
bnx2x_shrink_eth_fp(struct bnx2x * bp,int delta)169 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
170 {
171 int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
172
173 /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
174 * backward along the array could cause memory to be overridden
175 */
176 for (cos = 1; cos < bp->max_cos; cos++) {
177 for (i = 0; i < old_eth_num - delta; i++) {
178 struct bnx2x_fastpath *fp = &bp->fp[i];
179 int new_idx = cos * (old_eth_num - delta) + i;
180
181 memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
182 sizeof(struct bnx2x_fp_txdata));
183 fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
184 }
185 }
186 }
187
188 int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
189
190 /* free skb in the packet ring at pos idx
191 * return idx of last bd freed
192 */
bnx2x_free_tx_pkt(struct bnx2x * bp,struct bnx2x_fp_txdata * txdata,u16 idx,unsigned int * pkts_compl,unsigned int * bytes_compl)193 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
194 u16 idx, unsigned int *pkts_compl,
195 unsigned int *bytes_compl)
196 {
197 struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
198 struct eth_tx_start_bd *tx_start_bd;
199 struct eth_tx_bd *tx_data_bd;
200 struct sk_buff *skb = tx_buf->skb;
201 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
202 int nbd;
203 u16 split_bd_len = 0;
204
205 /* prefetch skb end pointer to speedup dev_kfree_skb() */
206 prefetch(&skb->end);
207
208 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
209 txdata->txq_index, idx, tx_buf, skb);
210
211 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
212
213 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
214 #ifdef BNX2X_STOP_ON_ERROR
215 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
216 BNX2X_ERR("BAD nbd!\n");
217 bnx2x_panic();
218 }
219 #endif
220 new_cons = nbd + tx_buf->first_bd;
221
222 /* Get the next bd */
223 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
224
225 /* Skip a parse bd... */
226 --nbd;
227 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
228
229 if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) {
230 /* Skip second parse bd... */
231 --nbd;
232 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
233 }
234
235 /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
236 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
237 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
238 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
239 --nbd;
240 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
241 }
242
243 /* unmap first bd */
244 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
245 BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
246 DMA_TO_DEVICE);
247
248 /* now free frags */
249 while (nbd > 0) {
250
251 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
252 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
253 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
254 if (--nbd)
255 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
256 }
257
258 /* release skb */
259 WARN_ON(!skb);
260 if (likely(skb)) {
261 (*pkts_compl)++;
262 (*bytes_compl) += skb->len;
263 dev_kfree_skb_any(skb);
264 }
265
266 tx_buf->first_bd = 0;
267 tx_buf->skb = NULL;
268
269 return new_cons;
270 }
271
bnx2x_tx_int(struct bnx2x * bp,struct bnx2x_fp_txdata * txdata)272 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
273 {
274 struct netdev_queue *txq;
275 u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
276 unsigned int pkts_compl = 0, bytes_compl = 0;
277
278 #ifdef BNX2X_STOP_ON_ERROR
279 if (unlikely(bp->panic))
280 return -1;
281 #endif
282
283 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
284 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
285 sw_cons = txdata->tx_pkt_cons;
286
287 /* Ensure subsequent loads occur after hw_cons */
288 smp_rmb();
289
290 while (sw_cons != hw_cons) {
291 u16 pkt_cons;
292
293 pkt_cons = TX_BD(sw_cons);
294
295 DP(NETIF_MSG_TX_DONE,
296 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
297 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
298
299 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
300 &pkts_compl, &bytes_compl);
301
302 sw_cons++;
303 }
304
305 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
306
307 txdata->tx_pkt_cons = sw_cons;
308 txdata->tx_bd_cons = bd_cons;
309
310 /* Need to make the tx_bd_cons update visible to start_xmit()
311 * before checking for netif_tx_queue_stopped(). Without the
312 * memory barrier, there is a small possibility that
313 * start_xmit() will miss it and cause the queue to be stopped
314 * forever.
315 * On the other hand we need an rmb() here to ensure the proper
316 * ordering of bit testing in the following
317 * netif_tx_queue_stopped(txq) call.
318 */
319 smp_mb();
320
321 if (unlikely(netif_tx_queue_stopped(txq))) {
322 /* Taking tx_lock() is needed to prevent re-enabling the queue
323 * while it's empty. This could have happen if rx_action() gets
324 * suspended in bnx2x_tx_int() after the condition before
325 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
326 *
327 * stops the queue->sees fresh tx_bd_cons->releases the queue->
328 * sends some packets consuming the whole queue again->
329 * stops the queue
330 */
331
332 __netif_tx_lock(txq, smp_processor_id());
333
334 if ((netif_tx_queue_stopped(txq)) &&
335 (bp->state == BNX2X_STATE_OPEN) &&
336 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
337 netif_tx_wake_queue(txq);
338
339 __netif_tx_unlock(txq);
340 }
341 return 0;
342 }
343
bnx2x_update_last_max_sge(struct bnx2x_fastpath * fp,u16 idx)344 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
345 u16 idx)
346 {
347 u16 last_max = fp->last_max_sge;
348
349 if (SUB_S16(idx, last_max) > 0)
350 fp->last_max_sge = idx;
351 }
352
bnx2x_update_sge_prod(struct bnx2x_fastpath * fp,u16 sge_len,struct eth_end_agg_rx_cqe * cqe)353 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
354 u16 sge_len,
355 struct eth_end_agg_rx_cqe *cqe)
356 {
357 struct bnx2x *bp = fp->bp;
358 u16 last_max, last_elem, first_elem;
359 u16 delta = 0;
360 u16 i;
361
362 if (!sge_len)
363 return;
364
365 /* First mark all used pages */
366 for (i = 0; i < sge_len; i++)
367 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
368 RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
369
370 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
371 sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
372
373 /* Here we assume that the last SGE index is the biggest */
374 prefetch((void *)(fp->sge_mask));
375 bnx2x_update_last_max_sge(fp,
376 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
377
378 last_max = RX_SGE(fp->last_max_sge);
379 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
380 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
381
382 /* If ring is not full */
383 if (last_elem + 1 != first_elem)
384 last_elem++;
385
386 /* Now update the prod */
387 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
388 if (likely(fp->sge_mask[i]))
389 break;
390
391 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
392 delta += BIT_VEC64_ELEM_SZ;
393 }
394
395 if (delta > 0) {
396 fp->rx_sge_prod += delta;
397 /* clear page-end entries */
398 bnx2x_clear_sge_mask_next_elems(fp);
399 }
400
401 DP(NETIF_MSG_RX_STATUS,
402 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
403 fp->last_max_sge, fp->rx_sge_prod);
404 }
405
406 /* Get Toeplitz hash value in the skb using the value from the
407 * CQE (calculated by HW).
408 */
bnx2x_get_rxhash(const struct bnx2x * bp,const struct eth_fast_path_rx_cqe * cqe,enum pkt_hash_types * rxhash_type)409 static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
410 const struct eth_fast_path_rx_cqe *cqe,
411 enum pkt_hash_types *rxhash_type)
412 {
413 /* Get Toeplitz hash from CQE */
414 if ((bp->dev->features & NETIF_F_RXHASH) &&
415 (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
416 enum eth_rss_hash_type htype;
417
418 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
419 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
420 (htype == TCP_IPV6_HASH_TYPE)) ?
421 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
422
423 return le32_to_cpu(cqe->rss_hash_result);
424 }
425 *rxhash_type = PKT_HASH_TYPE_NONE;
426 return 0;
427 }
428
bnx2x_tpa_start(struct bnx2x_fastpath * fp,u16 queue,u16 cons,u16 prod,struct eth_fast_path_rx_cqe * cqe)429 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
430 u16 cons, u16 prod,
431 struct eth_fast_path_rx_cqe *cqe)
432 {
433 struct bnx2x *bp = fp->bp;
434 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
435 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
436 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
437 dma_addr_t mapping;
438 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
439 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
440
441 /* print error if current state != stop */
442 if (tpa_info->tpa_state != BNX2X_TPA_STOP)
443 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
444
445 /* Try to map an empty data buffer from the aggregation info */
446 mapping = dma_map_single(&bp->pdev->dev,
447 first_buf->data + NET_SKB_PAD,
448 fp->rx_buf_size, DMA_FROM_DEVICE);
449 /*
450 * ...if it fails - move the skb from the consumer to the producer
451 * and set the current aggregation state as ERROR to drop it
452 * when TPA_STOP arrives.
453 */
454
455 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
456 /* Move the BD from the consumer to the producer */
457 bnx2x_reuse_rx_data(fp, cons, prod);
458 tpa_info->tpa_state = BNX2X_TPA_ERROR;
459 return;
460 }
461
462 /* move empty data from pool to prod */
463 prod_rx_buf->data = first_buf->data;
464 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
465 /* point prod_bd to new data */
466 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
467 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
468
469 /* move partial skb from cons to pool (don't unmap yet) */
470 *first_buf = *cons_rx_buf;
471
472 /* mark bin state as START */
473 tpa_info->parsing_flags =
474 le16_to_cpu(cqe->pars_flags.flags);
475 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
476 tpa_info->tpa_state = BNX2X_TPA_START;
477 tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
478 tpa_info->placement_offset = cqe->placement_offset;
479 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
480 if (fp->mode == TPA_MODE_GRO) {
481 u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
482 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
483 tpa_info->gro_size = gro_size;
484 }
485
486 #ifdef BNX2X_STOP_ON_ERROR
487 fp->tpa_queue_used |= (1 << queue);
488 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
489 fp->tpa_queue_used);
490 #endif
491 }
492
493 /* Timestamp option length allowed for TPA aggregation:
494 *
495 * nop nop kind length echo val
496 */
497 #define TPA_TSTAMP_OPT_LEN 12
498 /**
499 * bnx2x_set_gro_params - compute GRO values
500 *
501 * @skb: packet skb
502 * @parsing_flags: parsing flags from the START CQE
503 * @len_on_bd: total length of the first packet for the
504 * aggregation.
505 * @pkt_len: length of all segments
506 * @num_of_coalesced_segs: count of segments
507 *
508 * Approximate value of the MSS for this aggregation calculated using
509 * the first packet of it.
510 * Compute number of aggregated segments, and gso_type.
511 */
bnx2x_set_gro_params(struct sk_buff * skb,u16 parsing_flags,u16 len_on_bd,unsigned int pkt_len,u16 num_of_coalesced_segs)512 static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
513 u16 len_on_bd, unsigned int pkt_len,
514 u16 num_of_coalesced_segs)
515 {
516 /* TPA aggregation won't have either IP options or TCP options
517 * other than timestamp or IPv6 extension headers.
518 */
519 u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
520
521 if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
522 PRS_FLAG_OVERETH_IPV6) {
523 hdrs_len += sizeof(struct ipv6hdr);
524 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
525 } else {
526 hdrs_len += sizeof(struct iphdr);
527 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
528 }
529
530 /* Check if there was a TCP timestamp, if there is it's will
531 * always be 12 bytes length: nop nop kind length echo val.
532 *
533 * Otherwise FW would close the aggregation.
534 */
535 if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
536 hdrs_len += TPA_TSTAMP_OPT_LEN;
537
538 skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
539
540 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
541 * to skb_shinfo(skb)->gso_segs
542 */
543 NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
544 }
545
bnx2x_alloc_rx_sge(struct bnx2x * bp,struct bnx2x_fastpath * fp,u16 index,gfp_t gfp_mask)546 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
547 u16 index, gfp_t gfp_mask)
548 {
549 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
550 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
551 struct bnx2x_alloc_pool *pool = &fp->page_pool;
552 dma_addr_t mapping;
553
554 if (!pool->page) {
555 pool->page = alloc_pages(gfp_mask, PAGES_PER_SGE_SHIFT);
556 if (unlikely(!pool->page))
557 return -ENOMEM;
558
559 pool->offset = 0;
560 }
561
562 mapping = dma_map_page(&bp->pdev->dev, pool->page,
563 pool->offset, SGE_PAGE_SIZE, DMA_FROM_DEVICE);
564 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
565 BNX2X_ERR("Can't map sge\n");
566 return -ENOMEM;
567 }
568
569 sw_buf->page = pool->page;
570 sw_buf->offset = pool->offset;
571
572 dma_unmap_addr_set(sw_buf, mapping, mapping);
573
574 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
575 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
576
577 pool->offset += SGE_PAGE_SIZE;
578 if (PAGE_SIZE - pool->offset >= SGE_PAGE_SIZE)
579 get_page(pool->page);
580 else
581 pool->page = NULL;
582 return 0;
583 }
584
bnx2x_fill_frag_skb(struct bnx2x * bp,struct bnx2x_fastpath * fp,struct bnx2x_agg_info * tpa_info,u16 pages,struct sk_buff * skb,struct eth_end_agg_rx_cqe * cqe,u16 cqe_idx)585 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
586 struct bnx2x_agg_info *tpa_info,
587 u16 pages,
588 struct sk_buff *skb,
589 struct eth_end_agg_rx_cqe *cqe,
590 u16 cqe_idx)
591 {
592 struct sw_rx_page *rx_pg, old_rx_pg;
593 u32 i, frag_len, frag_size;
594 int err, j, frag_id = 0;
595 u16 len_on_bd = tpa_info->len_on_bd;
596 u16 full_page = 0, gro_size = 0;
597
598 frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
599
600 if (fp->mode == TPA_MODE_GRO) {
601 gro_size = tpa_info->gro_size;
602 full_page = tpa_info->full_page;
603 }
604
605 /* This is needed in order to enable forwarding support */
606 if (frag_size)
607 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
608 le16_to_cpu(cqe->pkt_len),
609 le16_to_cpu(cqe->num_of_coalesced_segs));
610
611 #ifdef BNX2X_STOP_ON_ERROR
612 if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
613 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
614 pages, cqe_idx);
615 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
616 bnx2x_panic();
617 return -EINVAL;
618 }
619 #endif
620
621 /* Run through the SGL and compose the fragmented skb */
622 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
623 u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
624
625 /* FW gives the indices of the SGE as if the ring is an array
626 (meaning that "next" element will consume 2 indices) */
627 if (fp->mode == TPA_MODE_GRO)
628 frag_len = min_t(u32, frag_size, (u32)full_page);
629 else /* LRO */
630 frag_len = min_t(u32, frag_size, (u32)SGE_PAGES);
631
632 rx_pg = &fp->rx_page_ring[sge_idx];
633 old_rx_pg = *rx_pg;
634
635 /* If we fail to allocate a substitute page, we simply stop
636 where we are and drop the whole packet */
637 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, GFP_ATOMIC);
638 if (unlikely(err)) {
639 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
640 return err;
641 }
642
643 dma_unmap_page(&bp->pdev->dev,
644 dma_unmap_addr(&old_rx_pg, mapping),
645 SGE_PAGE_SIZE, DMA_FROM_DEVICE);
646 /* Add one frag and update the appropriate fields in the skb */
647 if (fp->mode == TPA_MODE_LRO)
648 skb_fill_page_desc(skb, j, old_rx_pg.page,
649 old_rx_pg.offset, frag_len);
650 else { /* GRO */
651 int rem;
652 int offset = 0;
653 for (rem = frag_len; rem > 0; rem -= gro_size) {
654 int len = rem > gro_size ? gro_size : rem;
655 skb_fill_page_desc(skb, frag_id++,
656 old_rx_pg.page,
657 old_rx_pg.offset + offset,
658 len);
659 if (offset)
660 get_page(old_rx_pg.page);
661 offset += len;
662 }
663 }
664
665 skb->data_len += frag_len;
666 skb->truesize += SGE_PAGES;
667 skb->len += frag_len;
668
669 frag_size -= frag_len;
670 }
671
672 return 0;
673 }
674
bnx2x_frag_free(const struct bnx2x_fastpath * fp,void * data)675 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
676 {
677 if (fp->rx_frag_size)
678 skb_free_frag(data);
679 else
680 kfree(data);
681 }
682
bnx2x_frag_alloc(const struct bnx2x_fastpath * fp,gfp_t gfp_mask)683 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
684 {
685 if (fp->rx_frag_size) {
686 /* GFP_KERNEL allocations are used only during initialization */
687 if (unlikely(gfpflags_allow_blocking(gfp_mask)))
688 return (void *)__get_free_page(gfp_mask);
689
690 return napi_alloc_frag(fp->rx_frag_size);
691 }
692
693 return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
694 }
695
696 #ifdef CONFIG_INET
bnx2x_gro_ip_csum(struct bnx2x * bp,struct sk_buff * skb)697 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
698 {
699 const struct iphdr *iph = ip_hdr(skb);
700 struct tcphdr *th;
701
702 skb_set_transport_header(skb, sizeof(struct iphdr));
703 th = tcp_hdr(skb);
704
705 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
706 iph->saddr, iph->daddr, 0);
707 }
708
bnx2x_gro_ipv6_csum(struct bnx2x * bp,struct sk_buff * skb)709 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
710 {
711 struct ipv6hdr *iph = ipv6_hdr(skb);
712 struct tcphdr *th;
713
714 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
715 th = tcp_hdr(skb);
716
717 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
718 &iph->saddr, &iph->daddr, 0);
719 }
720
bnx2x_gro_csum(struct bnx2x * bp,struct sk_buff * skb,void (* gro_func)(struct bnx2x *,struct sk_buff *))721 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
722 void (*gro_func)(struct bnx2x*, struct sk_buff*))
723 {
724 skb_reset_network_header(skb);
725 gro_func(bp, skb);
726 tcp_gro_complete(skb);
727 }
728 #endif
729
bnx2x_gro_receive(struct bnx2x * bp,struct bnx2x_fastpath * fp,struct sk_buff * skb)730 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
731 struct sk_buff *skb)
732 {
733 #ifdef CONFIG_INET
734 if (skb_shinfo(skb)->gso_size) {
735 switch (be16_to_cpu(skb->protocol)) {
736 case ETH_P_IP:
737 bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
738 break;
739 case ETH_P_IPV6:
740 bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
741 break;
742 default:
743 netdev_WARN_ONCE(bp->dev,
744 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
745 be16_to_cpu(skb->protocol));
746 }
747 }
748 #endif
749 skb_record_rx_queue(skb, fp->rx_queue);
750 napi_gro_receive(&fp->napi, skb);
751 }
752
bnx2x_tpa_stop(struct bnx2x * bp,struct bnx2x_fastpath * fp,struct bnx2x_agg_info * tpa_info,u16 pages,struct eth_end_agg_rx_cqe * cqe,u16 cqe_idx)753 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
754 struct bnx2x_agg_info *tpa_info,
755 u16 pages,
756 struct eth_end_agg_rx_cqe *cqe,
757 u16 cqe_idx)
758 {
759 struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
760 u8 pad = tpa_info->placement_offset;
761 u16 len = tpa_info->len_on_bd;
762 struct sk_buff *skb = NULL;
763 u8 *new_data, *data = rx_buf->data;
764 u8 old_tpa_state = tpa_info->tpa_state;
765
766 tpa_info->tpa_state = BNX2X_TPA_STOP;
767
768 /* If we there was an error during the handling of the TPA_START -
769 * drop this aggregation.
770 */
771 if (old_tpa_state == BNX2X_TPA_ERROR)
772 goto drop;
773
774 /* Try to allocate the new data */
775 new_data = bnx2x_frag_alloc(fp, GFP_ATOMIC);
776 /* Unmap skb in the pool anyway, as we are going to change
777 pool entry status to BNX2X_TPA_STOP even if new skb allocation
778 fails. */
779 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
780 fp->rx_buf_size, DMA_FROM_DEVICE);
781 if (likely(new_data))
782 skb = build_skb(data, fp->rx_frag_size);
783
784 if (likely(skb)) {
785 #ifdef BNX2X_STOP_ON_ERROR
786 if (pad + len > fp->rx_buf_size) {
787 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
788 pad, len, fp->rx_buf_size);
789 bnx2x_panic();
790 bnx2x_frag_free(fp, new_data);
791 return;
792 }
793 #endif
794
795 skb_reserve(skb, pad + NET_SKB_PAD);
796 skb_put(skb, len);
797 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
798
799 skb->protocol = eth_type_trans(skb, bp->dev);
800 skb->ip_summed = CHECKSUM_UNNECESSARY;
801
802 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
803 skb, cqe, cqe_idx)) {
804 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
805 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tpa_info->vlan_tag);
806 bnx2x_gro_receive(bp, fp, skb);
807 } else {
808 DP(NETIF_MSG_RX_STATUS,
809 "Failed to allocate new pages - dropping packet!\n");
810 dev_kfree_skb_any(skb);
811 }
812
813 /* put new data in bin */
814 rx_buf->data = new_data;
815
816 return;
817 }
818 if (new_data)
819 bnx2x_frag_free(fp, new_data);
820 drop:
821 /* drop the packet and keep the buffer in the bin */
822 DP(NETIF_MSG_RX_STATUS,
823 "Failed to allocate or map a new skb - dropping packet!\n");
824 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
825 }
826
bnx2x_alloc_rx_data(struct bnx2x * bp,struct bnx2x_fastpath * fp,u16 index,gfp_t gfp_mask)827 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
828 u16 index, gfp_t gfp_mask)
829 {
830 u8 *data;
831 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
832 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
833 dma_addr_t mapping;
834
835 data = bnx2x_frag_alloc(fp, gfp_mask);
836 if (unlikely(data == NULL))
837 return -ENOMEM;
838
839 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
840 fp->rx_buf_size,
841 DMA_FROM_DEVICE);
842 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
843 bnx2x_frag_free(fp, data);
844 BNX2X_ERR("Can't map rx data\n");
845 return -ENOMEM;
846 }
847
848 rx_buf->data = data;
849 dma_unmap_addr_set(rx_buf, mapping, mapping);
850
851 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
852 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
853
854 return 0;
855 }
856
857 static
bnx2x_csum_validate(struct sk_buff * skb,union eth_rx_cqe * cqe,struct bnx2x_fastpath * fp,struct bnx2x_eth_q_stats * qstats)858 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
859 struct bnx2x_fastpath *fp,
860 struct bnx2x_eth_q_stats *qstats)
861 {
862 /* Do nothing if no L4 csum validation was done.
863 * We do not check whether IP csum was validated. For IPv4 we assume
864 * that if the card got as far as validating the L4 csum, it also
865 * validated the IP csum. IPv6 has no IP csum.
866 */
867 if (cqe->fast_path_cqe.status_flags &
868 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
869 return;
870
871 /* If L4 validation was done, check if an error was found. */
872
873 if (cqe->fast_path_cqe.type_error_flags &
874 (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
875 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
876 qstats->hw_csum_err++;
877 else
878 skb->ip_summed = CHECKSUM_UNNECESSARY;
879 }
880
bnx2x_rx_int(struct bnx2x_fastpath * fp,int budget)881 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
882 {
883 struct bnx2x *bp = fp->bp;
884 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
885 u16 sw_comp_cons, sw_comp_prod;
886 int rx_pkt = 0;
887 union eth_rx_cqe *cqe;
888 struct eth_fast_path_rx_cqe *cqe_fp;
889
890 #ifdef BNX2X_STOP_ON_ERROR
891 if (unlikely(bp->panic))
892 return 0;
893 #endif
894 if (budget <= 0)
895 return rx_pkt;
896
897 bd_cons = fp->rx_bd_cons;
898 bd_prod = fp->rx_bd_prod;
899 bd_prod_fw = bd_prod;
900 sw_comp_cons = fp->rx_comp_cons;
901 sw_comp_prod = fp->rx_comp_prod;
902
903 comp_ring_cons = RCQ_BD(sw_comp_cons);
904 cqe = &fp->rx_comp_ring[comp_ring_cons];
905 cqe_fp = &cqe->fast_path_cqe;
906
907 DP(NETIF_MSG_RX_STATUS,
908 "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
909
910 while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
911 struct sw_rx_bd *rx_buf = NULL;
912 struct sk_buff *skb;
913 u8 cqe_fp_flags;
914 enum eth_rx_cqe_type cqe_fp_type;
915 u16 len, pad, queue;
916 u8 *data;
917 u32 rxhash;
918 enum pkt_hash_types rxhash_type;
919
920 #ifdef BNX2X_STOP_ON_ERROR
921 if (unlikely(bp->panic))
922 return 0;
923 #endif
924
925 bd_prod = RX_BD(bd_prod);
926 bd_cons = RX_BD(bd_cons);
927
928 /* A rmb() is required to ensure that the CQE is not read
929 * before it is written by the adapter DMA. PCI ordering
930 * rules will make sure the other fields are written before
931 * the marker at the end of struct eth_fast_path_rx_cqe
932 * but without rmb() a weakly ordered processor can process
933 * stale data. Without the barrier TPA state-machine might
934 * enter inconsistent state and kernel stack might be
935 * provided with incorrect packet description - these lead
936 * to various kernel crashed.
937 */
938 rmb();
939
940 cqe_fp_flags = cqe_fp->type_error_flags;
941 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
942
943 DP(NETIF_MSG_RX_STATUS,
944 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
945 CQE_TYPE(cqe_fp_flags),
946 cqe_fp_flags, cqe_fp->status_flags,
947 le32_to_cpu(cqe_fp->rss_hash_result),
948 le16_to_cpu(cqe_fp->vlan_tag),
949 le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
950
951 /* is this a slowpath msg? */
952 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
953 bnx2x_sp_event(fp, cqe);
954 goto next_cqe;
955 }
956
957 rx_buf = &fp->rx_buf_ring[bd_cons];
958 data = rx_buf->data;
959
960 if (!CQE_TYPE_FAST(cqe_fp_type)) {
961 struct bnx2x_agg_info *tpa_info;
962 u16 frag_size, pages;
963 #ifdef BNX2X_STOP_ON_ERROR
964 /* sanity check */
965 if (fp->mode == TPA_MODE_DISABLED &&
966 (CQE_TYPE_START(cqe_fp_type) ||
967 CQE_TYPE_STOP(cqe_fp_type)))
968 BNX2X_ERR("START/STOP packet while TPA disabled, type %x\n",
969 CQE_TYPE(cqe_fp_type));
970 #endif
971
972 if (CQE_TYPE_START(cqe_fp_type)) {
973 u16 queue = cqe_fp->queue_index;
974 DP(NETIF_MSG_RX_STATUS,
975 "calling tpa_start on queue %d\n",
976 queue);
977
978 bnx2x_tpa_start(fp, queue,
979 bd_cons, bd_prod,
980 cqe_fp);
981
982 goto next_rx;
983 }
984 queue = cqe->end_agg_cqe.queue_index;
985 tpa_info = &fp->tpa_info[queue];
986 DP(NETIF_MSG_RX_STATUS,
987 "calling tpa_stop on queue %d\n",
988 queue);
989
990 frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
991 tpa_info->len_on_bd;
992
993 if (fp->mode == TPA_MODE_GRO)
994 pages = (frag_size + tpa_info->full_page - 1) /
995 tpa_info->full_page;
996 else
997 pages = SGE_PAGE_ALIGN(frag_size) >>
998 SGE_PAGE_SHIFT;
999
1000 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
1001 &cqe->end_agg_cqe, comp_ring_cons);
1002 #ifdef BNX2X_STOP_ON_ERROR
1003 if (bp->panic)
1004 return 0;
1005 #endif
1006
1007 bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
1008 goto next_cqe;
1009 }
1010 /* non TPA */
1011 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
1012 pad = cqe_fp->placement_offset;
1013 dma_sync_single_for_cpu(&bp->pdev->dev,
1014 dma_unmap_addr(rx_buf, mapping),
1015 pad + RX_COPY_THRESH,
1016 DMA_FROM_DEVICE);
1017 pad += NET_SKB_PAD;
1018 prefetch(data + pad); /* speedup eth_type_trans() */
1019 /* is this an error packet? */
1020 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1021 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1022 "ERROR flags %x rx packet %u\n",
1023 cqe_fp_flags, sw_comp_cons);
1024 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
1025 goto reuse_rx;
1026 }
1027
1028 /* Since we don't have a jumbo ring
1029 * copy small packets if mtu > 1500
1030 */
1031 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1032 (len <= RX_COPY_THRESH)) {
1033 skb = napi_alloc_skb(&fp->napi, len);
1034 if (skb == NULL) {
1035 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1036 "ERROR packet dropped because of alloc failure\n");
1037 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1038 goto reuse_rx;
1039 }
1040 memcpy(skb->data, data + pad, len);
1041 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1042 } else {
1043 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1044 GFP_ATOMIC) == 0)) {
1045 dma_unmap_single(&bp->pdev->dev,
1046 dma_unmap_addr(rx_buf, mapping),
1047 fp->rx_buf_size,
1048 DMA_FROM_DEVICE);
1049 skb = build_skb(data, fp->rx_frag_size);
1050 if (unlikely(!skb)) {
1051 bnx2x_frag_free(fp, data);
1052 bnx2x_fp_qstats(bp, fp)->
1053 rx_skb_alloc_failed++;
1054 goto next_rx;
1055 }
1056 skb_reserve(skb, pad);
1057 } else {
1058 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1059 "ERROR packet dropped because of alloc failure\n");
1060 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1061 reuse_rx:
1062 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1063 goto next_rx;
1064 }
1065 }
1066
1067 skb_put(skb, len);
1068 skb->protocol = eth_type_trans(skb, bp->dev);
1069
1070 /* Set Toeplitz hash for a none-LRO skb */
1071 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1072 skb_set_hash(skb, rxhash, rxhash_type);
1073
1074 skb_checksum_none_assert(skb);
1075
1076 if (bp->dev->features & NETIF_F_RXCSUM)
1077 bnx2x_csum_validate(skb, cqe, fp,
1078 bnx2x_fp_qstats(bp, fp));
1079
1080 skb_record_rx_queue(skb, fp->rx_queue);
1081
1082 /* Check if this packet was timestamped */
1083 if (unlikely(cqe->fast_path_cqe.type_error_flags &
1084 (1 << ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT)))
1085 bnx2x_set_rx_ts(bp, skb);
1086
1087 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1088 PARSING_FLAGS_VLAN)
1089 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1090 le16_to_cpu(cqe_fp->vlan_tag));
1091
1092 napi_gro_receive(&fp->napi, skb);
1093 next_rx:
1094 rx_buf->data = NULL;
1095
1096 bd_cons = NEXT_RX_IDX(bd_cons);
1097 bd_prod = NEXT_RX_IDX(bd_prod);
1098 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1099 rx_pkt++;
1100 next_cqe:
1101 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1102 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1103
1104 /* mark CQE as free */
1105 BNX2X_SEED_CQE(cqe_fp);
1106
1107 if (rx_pkt == budget)
1108 break;
1109
1110 comp_ring_cons = RCQ_BD(sw_comp_cons);
1111 cqe = &fp->rx_comp_ring[comp_ring_cons];
1112 cqe_fp = &cqe->fast_path_cqe;
1113 } /* while */
1114
1115 fp->rx_bd_cons = bd_cons;
1116 fp->rx_bd_prod = bd_prod_fw;
1117 fp->rx_comp_cons = sw_comp_cons;
1118 fp->rx_comp_prod = sw_comp_prod;
1119
1120 /* Update producers */
1121 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1122 fp->rx_sge_prod);
1123
1124 return rx_pkt;
1125 }
1126
bnx2x_msix_fp_int(int irq,void * fp_cookie)1127 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1128 {
1129 struct bnx2x_fastpath *fp = fp_cookie;
1130 struct bnx2x *bp = fp->bp;
1131 u8 cos;
1132
1133 DP(NETIF_MSG_INTR,
1134 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1135 fp->index, fp->fw_sb_id, fp->igu_sb_id);
1136
1137 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1138
1139 #ifdef BNX2X_STOP_ON_ERROR
1140 if (unlikely(bp->panic))
1141 return IRQ_HANDLED;
1142 #endif
1143
1144 /* Handle Rx and Tx according to MSI-X vector */
1145 for_each_cos_in_tx_queue(fp, cos)
1146 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1147
1148 prefetch(&fp->sb_running_index[SM_RX_ID]);
1149 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1150
1151 return IRQ_HANDLED;
1152 }
1153
1154 /* HW Lock for shared dual port PHYs */
bnx2x_acquire_phy_lock(struct bnx2x * bp)1155 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1156 {
1157 mutex_lock(&bp->port.phy_mutex);
1158
1159 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1160 }
1161
bnx2x_release_phy_lock(struct bnx2x * bp)1162 void bnx2x_release_phy_lock(struct bnx2x *bp)
1163 {
1164 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1165
1166 mutex_unlock(&bp->port.phy_mutex);
1167 }
1168
1169 /* calculates MF speed according to current linespeed and MF configuration */
bnx2x_get_mf_speed(struct bnx2x * bp)1170 u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1171 {
1172 u16 line_speed = bp->link_vars.line_speed;
1173 if (IS_MF(bp)) {
1174 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1175 bp->mf_config[BP_VN(bp)]);
1176
1177 /* Calculate the current MAX line speed limit for the MF
1178 * devices
1179 */
1180 if (IS_MF_PERCENT_BW(bp))
1181 line_speed = (line_speed * maxCfg) / 100;
1182 else { /* SD mode */
1183 u16 vn_max_rate = maxCfg * 100;
1184
1185 if (vn_max_rate < line_speed)
1186 line_speed = vn_max_rate;
1187 }
1188 }
1189
1190 return line_speed;
1191 }
1192
1193 /**
1194 * bnx2x_fill_report_data - fill link report data to report
1195 *
1196 * @bp: driver handle
1197 * @data: link state to update
1198 *
1199 * It uses a none-atomic bit operations because is called under the mutex.
1200 */
bnx2x_fill_report_data(struct bnx2x * bp,struct bnx2x_link_report_data * data)1201 static void bnx2x_fill_report_data(struct bnx2x *bp,
1202 struct bnx2x_link_report_data *data)
1203 {
1204 memset(data, 0, sizeof(*data));
1205
1206 if (IS_PF(bp)) {
1207 /* Fill the report data: effective line speed */
1208 data->line_speed = bnx2x_get_mf_speed(bp);
1209
1210 /* Link is down */
1211 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1212 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1213 &data->link_report_flags);
1214
1215 if (!BNX2X_NUM_ETH_QUEUES(bp))
1216 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1217 &data->link_report_flags);
1218
1219 /* Full DUPLEX */
1220 if (bp->link_vars.duplex == DUPLEX_FULL)
1221 __set_bit(BNX2X_LINK_REPORT_FD,
1222 &data->link_report_flags);
1223
1224 /* Rx Flow Control is ON */
1225 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1226 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1227 &data->link_report_flags);
1228
1229 /* Tx Flow Control is ON */
1230 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1231 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1232 &data->link_report_flags);
1233 } else { /* VF */
1234 *data = bp->vf_link_vars;
1235 }
1236 }
1237
1238 /**
1239 * bnx2x_link_report - report link status to OS.
1240 *
1241 * @bp: driver handle
1242 *
1243 * Calls the __bnx2x_link_report() under the same locking scheme
1244 * as a link/PHY state managing code to ensure a consistent link
1245 * reporting.
1246 */
1247
bnx2x_link_report(struct bnx2x * bp)1248 void bnx2x_link_report(struct bnx2x *bp)
1249 {
1250 bnx2x_acquire_phy_lock(bp);
1251 __bnx2x_link_report(bp);
1252 bnx2x_release_phy_lock(bp);
1253 }
1254
1255 /**
1256 * __bnx2x_link_report - report link status to OS.
1257 *
1258 * @bp: driver handle
1259 *
1260 * None atomic implementation.
1261 * Should be called under the phy_lock.
1262 */
__bnx2x_link_report(struct bnx2x * bp)1263 void __bnx2x_link_report(struct bnx2x *bp)
1264 {
1265 struct bnx2x_link_report_data cur_data;
1266
1267 if (bp->force_link_down) {
1268 bp->link_vars.link_up = 0;
1269 return;
1270 }
1271
1272 /* reread mf_cfg */
1273 if (IS_PF(bp) && !CHIP_IS_E1(bp))
1274 bnx2x_read_mf_cfg(bp);
1275
1276 /* Read the current link report info */
1277 bnx2x_fill_report_data(bp, &cur_data);
1278
1279 /* Don't report link down or exactly the same link status twice */
1280 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1281 (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1282 &bp->last_reported_link.link_report_flags) &&
1283 test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1284 &cur_data.link_report_flags)))
1285 return;
1286
1287 bp->link_cnt++;
1288
1289 /* We are going to report a new link parameters now -
1290 * remember the current data for the next time.
1291 */
1292 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1293
1294 /* propagate status to VFs */
1295 if (IS_PF(bp))
1296 bnx2x_iov_link_update(bp);
1297
1298 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1299 &cur_data.link_report_flags)) {
1300 netif_carrier_off(bp->dev);
1301 netdev_err(bp->dev, "NIC Link is Down\n");
1302 return;
1303 } else {
1304 const char *duplex;
1305 const char *flow;
1306
1307 netif_carrier_on(bp->dev);
1308
1309 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1310 &cur_data.link_report_flags))
1311 duplex = "full";
1312 else
1313 duplex = "half";
1314
1315 /* Handle the FC at the end so that only these flags would be
1316 * possibly set. This way we may easily check if there is no FC
1317 * enabled.
1318 */
1319 if (cur_data.link_report_flags) {
1320 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1321 &cur_data.link_report_flags)) {
1322 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1323 &cur_data.link_report_flags))
1324 flow = "ON - receive & transmit";
1325 else
1326 flow = "ON - receive";
1327 } else {
1328 flow = "ON - transmit";
1329 }
1330 } else {
1331 flow = "none";
1332 }
1333 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1334 cur_data.line_speed, duplex, flow);
1335 }
1336 }
1337
bnx2x_set_next_page_sgl(struct bnx2x_fastpath * fp)1338 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1339 {
1340 int i;
1341
1342 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1343 struct eth_rx_sge *sge;
1344
1345 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1346 sge->addr_hi =
1347 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1348 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1349
1350 sge->addr_lo =
1351 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1352 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1353 }
1354 }
1355
bnx2x_free_tpa_pool(struct bnx2x * bp,struct bnx2x_fastpath * fp,int last)1356 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1357 struct bnx2x_fastpath *fp, int last)
1358 {
1359 int i;
1360
1361 for (i = 0; i < last; i++) {
1362 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1363 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1364 u8 *data = first_buf->data;
1365
1366 if (data == NULL) {
1367 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1368 continue;
1369 }
1370 if (tpa_info->tpa_state == BNX2X_TPA_START)
1371 dma_unmap_single(&bp->pdev->dev,
1372 dma_unmap_addr(first_buf, mapping),
1373 fp->rx_buf_size, DMA_FROM_DEVICE);
1374 bnx2x_frag_free(fp, data);
1375 first_buf->data = NULL;
1376 }
1377 }
1378
bnx2x_init_rx_rings_cnic(struct bnx2x * bp)1379 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1380 {
1381 int j;
1382
1383 for_each_rx_queue_cnic(bp, j) {
1384 struct bnx2x_fastpath *fp = &bp->fp[j];
1385
1386 fp->rx_bd_cons = 0;
1387
1388 /* Activate BD ring */
1389 /* Warning!
1390 * this will generate an interrupt (to the TSTORM)
1391 * must only be done after chip is initialized
1392 */
1393 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1394 fp->rx_sge_prod);
1395 }
1396 }
1397
bnx2x_init_rx_rings(struct bnx2x * bp)1398 void bnx2x_init_rx_rings(struct bnx2x *bp)
1399 {
1400 int func = BP_FUNC(bp);
1401 u16 ring_prod;
1402 int i, j;
1403
1404 /* Allocate TPA resources */
1405 for_each_eth_queue(bp, j) {
1406 struct bnx2x_fastpath *fp = &bp->fp[j];
1407
1408 DP(NETIF_MSG_IFUP,
1409 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1410
1411 if (fp->mode != TPA_MODE_DISABLED) {
1412 /* Fill the per-aggregation pool */
1413 for (i = 0; i < MAX_AGG_QS(bp); i++) {
1414 struct bnx2x_agg_info *tpa_info =
1415 &fp->tpa_info[i];
1416 struct sw_rx_bd *first_buf =
1417 &tpa_info->first_buf;
1418
1419 first_buf->data =
1420 bnx2x_frag_alloc(fp, GFP_KERNEL);
1421 if (!first_buf->data) {
1422 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1423 j);
1424 bnx2x_free_tpa_pool(bp, fp, i);
1425 fp->mode = TPA_MODE_DISABLED;
1426 break;
1427 }
1428 dma_unmap_addr_set(first_buf, mapping, 0);
1429 tpa_info->tpa_state = BNX2X_TPA_STOP;
1430 }
1431
1432 /* "next page" elements initialization */
1433 bnx2x_set_next_page_sgl(fp);
1434
1435 /* set SGEs bit mask */
1436 bnx2x_init_sge_ring_bit_mask(fp);
1437
1438 /* Allocate SGEs and initialize the ring elements */
1439 for (i = 0, ring_prod = 0;
1440 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1441
1442 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1443 GFP_KERNEL) < 0) {
1444 BNX2X_ERR("was only able to allocate %d rx sges\n",
1445 i);
1446 BNX2X_ERR("disabling TPA for queue[%d]\n",
1447 j);
1448 /* Cleanup already allocated elements */
1449 bnx2x_free_rx_sge_range(bp, fp,
1450 ring_prod);
1451 bnx2x_free_tpa_pool(bp, fp,
1452 MAX_AGG_QS(bp));
1453 fp->mode = TPA_MODE_DISABLED;
1454 ring_prod = 0;
1455 break;
1456 }
1457 ring_prod = NEXT_SGE_IDX(ring_prod);
1458 }
1459
1460 fp->rx_sge_prod = ring_prod;
1461 }
1462 }
1463
1464 for_each_eth_queue(bp, j) {
1465 struct bnx2x_fastpath *fp = &bp->fp[j];
1466
1467 fp->rx_bd_cons = 0;
1468
1469 /* Activate BD ring */
1470 /* Warning!
1471 * this will generate an interrupt (to the TSTORM)
1472 * must only be done after chip is initialized
1473 */
1474 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1475 fp->rx_sge_prod);
1476
1477 if (j != 0)
1478 continue;
1479
1480 if (CHIP_IS_E1(bp)) {
1481 REG_WR(bp, BAR_USTRORM_INTMEM +
1482 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1483 U64_LO(fp->rx_comp_mapping));
1484 REG_WR(bp, BAR_USTRORM_INTMEM +
1485 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1486 U64_HI(fp->rx_comp_mapping));
1487 }
1488 }
1489 }
1490
bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath * fp)1491 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1492 {
1493 u8 cos;
1494 struct bnx2x *bp = fp->bp;
1495
1496 for_each_cos_in_tx_queue(fp, cos) {
1497 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1498 unsigned pkts_compl = 0, bytes_compl = 0;
1499
1500 u16 sw_prod = txdata->tx_pkt_prod;
1501 u16 sw_cons = txdata->tx_pkt_cons;
1502
1503 while (sw_cons != sw_prod) {
1504 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1505 &pkts_compl, &bytes_compl);
1506 sw_cons++;
1507 }
1508
1509 netdev_tx_reset_queue(
1510 netdev_get_tx_queue(bp->dev,
1511 txdata->txq_index));
1512 }
1513 }
1514
bnx2x_free_tx_skbs_cnic(struct bnx2x * bp)1515 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1516 {
1517 int i;
1518
1519 for_each_tx_queue_cnic(bp, i) {
1520 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1521 }
1522 }
1523
bnx2x_free_tx_skbs(struct bnx2x * bp)1524 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1525 {
1526 int i;
1527
1528 for_each_eth_queue(bp, i) {
1529 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1530 }
1531 }
1532
bnx2x_free_rx_bds(struct bnx2x_fastpath * fp)1533 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1534 {
1535 struct bnx2x *bp = fp->bp;
1536 int i;
1537
1538 /* ring wasn't allocated */
1539 if (fp->rx_buf_ring == NULL)
1540 return;
1541
1542 for (i = 0; i < NUM_RX_BD; i++) {
1543 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1544 u8 *data = rx_buf->data;
1545
1546 if (data == NULL)
1547 continue;
1548 dma_unmap_single(&bp->pdev->dev,
1549 dma_unmap_addr(rx_buf, mapping),
1550 fp->rx_buf_size, DMA_FROM_DEVICE);
1551
1552 rx_buf->data = NULL;
1553 bnx2x_frag_free(fp, data);
1554 }
1555 }
1556
bnx2x_free_rx_skbs_cnic(struct bnx2x * bp)1557 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1558 {
1559 int j;
1560
1561 for_each_rx_queue_cnic(bp, j) {
1562 bnx2x_free_rx_bds(&bp->fp[j]);
1563 }
1564 }
1565
bnx2x_free_rx_skbs(struct bnx2x * bp)1566 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1567 {
1568 int j;
1569
1570 for_each_eth_queue(bp, j) {
1571 struct bnx2x_fastpath *fp = &bp->fp[j];
1572
1573 bnx2x_free_rx_bds(fp);
1574
1575 if (fp->mode != TPA_MODE_DISABLED)
1576 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1577 }
1578 }
1579
bnx2x_free_skbs_cnic(struct bnx2x * bp)1580 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1581 {
1582 bnx2x_free_tx_skbs_cnic(bp);
1583 bnx2x_free_rx_skbs_cnic(bp);
1584 }
1585
bnx2x_free_skbs(struct bnx2x * bp)1586 void bnx2x_free_skbs(struct bnx2x *bp)
1587 {
1588 bnx2x_free_tx_skbs(bp);
1589 bnx2x_free_rx_skbs(bp);
1590 }
1591
bnx2x_update_max_mf_config(struct bnx2x * bp,u32 value)1592 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1593 {
1594 /* load old values */
1595 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1596
1597 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1598 /* leave all but MAX value */
1599 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1600
1601 /* set new MAX value */
1602 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1603 & FUNC_MF_CFG_MAX_BW_MASK;
1604
1605 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1606 }
1607 }
1608
1609 /**
1610 * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1611 *
1612 * @bp: driver handle
1613 * @nvecs: number of vectors to be released
1614 */
bnx2x_free_msix_irqs(struct bnx2x * bp,int nvecs)1615 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1616 {
1617 int i, offset = 0;
1618
1619 if (nvecs == offset)
1620 return;
1621
1622 /* VFs don't have a default SB */
1623 if (IS_PF(bp)) {
1624 free_irq(bp->msix_table[offset].vector, bp->dev);
1625 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1626 bp->msix_table[offset].vector);
1627 offset++;
1628 }
1629
1630 if (CNIC_SUPPORT(bp)) {
1631 if (nvecs == offset)
1632 return;
1633 offset++;
1634 }
1635
1636 for_each_eth_queue(bp, i) {
1637 if (nvecs == offset)
1638 return;
1639 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1640 i, bp->msix_table[offset].vector);
1641
1642 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1643 }
1644 }
1645
bnx2x_free_irq(struct bnx2x * bp)1646 void bnx2x_free_irq(struct bnx2x *bp)
1647 {
1648 if (bp->flags & USING_MSIX_FLAG &&
1649 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1650 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1651
1652 /* vfs don't have a default status block */
1653 if (IS_PF(bp))
1654 nvecs++;
1655
1656 bnx2x_free_msix_irqs(bp, nvecs);
1657 } else {
1658 free_irq(bp->dev->irq, bp->dev);
1659 }
1660 }
1661
bnx2x_enable_msix(struct bnx2x * bp)1662 int bnx2x_enable_msix(struct bnx2x *bp)
1663 {
1664 int msix_vec = 0, i, rc;
1665
1666 /* VFs don't have a default status block */
1667 if (IS_PF(bp)) {
1668 bp->msix_table[msix_vec].entry = msix_vec;
1669 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1670 bp->msix_table[0].entry);
1671 msix_vec++;
1672 }
1673
1674 /* Cnic requires an msix vector for itself */
1675 if (CNIC_SUPPORT(bp)) {
1676 bp->msix_table[msix_vec].entry = msix_vec;
1677 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1678 msix_vec, bp->msix_table[msix_vec].entry);
1679 msix_vec++;
1680 }
1681
1682 /* We need separate vectors for ETH queues only (not FCoE) */
1683 for_each_eth_queue(bp, i) {
1684 bp->msix_table[msix_vec].entry = msix_vec;
1685 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1686 msix_vec, msix_vec, i);
1687 msix_vec++;
1688 }
1689
1690 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1691 msix_vec);
1692
1693 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1694 BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1695 /*
1696 * reconfigure number of tx/rx queues according to available
1697 * MSI-X vectors
1698 */
1699 if (rc == -ENOSPC) {
1700 /* Get by with single vector */
1701 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1702 if (rc < 0) {
1703 BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1704 rc);
1705 goto no_msix;
1706 }
1707
1708 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1709 bp->flags |= USING_SINGLE_MSIX_FLAG;
1710
1711 BNX2X_DEV_INFO("set number of queues to 1\n");
1712 bp->num_ethernet_queues = 1;
1713 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1714 } else if (rc < 0) {
1715 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1716 goto no_msix;
1717 } else if (rc < msix_vec) {
1718 /* how less vectors we will have? */
1719 int diff = msix_vec - rc;
1720
1721 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1722
1723 /*
1724 * decrease number of queues by number of unallocated entries
1725 */
1726 bp->num_ethernet_queues -= diff;
1727 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1728
1729 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1730 bp->num_queues);
1731 }
1732
1733 bp->flags |= USING_MSIX_FLAG;
1734
1735 return 0;
1736
1737 no_msix:
1738 /* fall to INTx if not enough memory */
1739 if (rc == -ENOMEM)
1740 bp->flags |= DISABLE_MSI_FLAG;
1741
1742 return rc;
1743 }
1744
bnx2x_req_msix_irqs(struct bnx2x * bp)1745 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1746 {
1747 int i, rc, offset = 0;
1748
1749 /* no default status block for vf */
1750 if (IS_PF(bp)) {
1751 rc = request_irq(bp->msix_table[offset++].vector,
1752 bnx2x_msix_sp_int, 0,
1753 bp->dev->name, bp->dev);
1754 if (rc) {
1755 BNX2X_ERR("request sp irq failed\n");
1756 return -EBUSY;
1757 }
1758 }
1759
1760 if (CNIC_SUPPORT(bp))
1761 offset++;
1762
1763 for_each_eth_queue(bp, i) {
1764 struct bnx2x_fastpath *fp = &bp->fp[i];
1765 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1766 bp->dev->name, i);
1767
1768 rc = request_irq(bp->msix_table[offset].vector,
1769 bnx2x_msix_fp_int, 0, fp->name, fp);
1770 if (rc) {
1771 BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i,
1772 bp->msix_table[offset].vector, rc);
1773 bnx2x_free_msix_irqs(bp, offset);
1774 return -EBUSY;
1775 }
1776
1777 offset++;
1778 }
1779
1780 i = BNX2X_NUM_ETH_QUEUES(bp);
1781 if (IS_PF(bp)) {
1782 offset = 1 + CNIC_SUPPORT(bp);
1783 netdev_info(bp->dev,
1784 "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1785 bp->msix_table[0].vector,
1786 0, bp->msix_table[offset].vector,
1787 i - 1, bp->msix_table[offset + i - 1].vector);
1788 } else {
1789 offset = CNIC_SUPPORT(bp);
1790 netdev_info(bp->dev,
1791 "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n",
1792 0, bp->msix_table[offset].vector,
1793 i - 1, bp->msix_table[offset + i - 1].vector);
1794 }
1795 return 0;
1796 }
1797
bnx2x_enable_msi(struct bnx2x * bp)1798 int bnx2x_enable_msi(struct bnx2x *bp)
1799 {
1800 int rc;
1801
1802 rc = pci_enable_msi(bp->pdev);
1803 if (rc) {
1804 BNX2X_DEV_INFO("MSI is not attainable\n");
1805 return -1;
1806 }
1807 bp->flags |= USING_MSI_FLAG;
1808
1809 return 0;
1810 }
1811
bnx2x_req_irq(struct bnx2x * bp)1812 static int bnx2x_req_irq(struct bnx2x *bp)
1813 {
1814 unsigned long flags;
1815 unsigned int irq;
1816
1817 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1818 flags = 0;
1819 else
1820 flags = IRQF_SHARED;
1821
1822 if (bp->flags & USING_MSIX_FLAG)
1823 irq = bp->msix_table[0].vector;
1824 else
1825 irq = bp->pdev->irq;
1826
1827 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1828 }
1829
bnx2x_setup_irqs(struct bnx2x * bp)1830 static int bnx2x_setup_irqs(struct bnx2x *bp)
1831 {
1832 int rc = 0;
1833 if (bp->flags & USING_MSIX_FLAG &&
1834 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1835 rc = bnx2x_req_msix_irqs(bp);
1836 if (rc)
1837 return rc;
1838 } else {
1839 rc = bnx2x_req_irq(bp);
1840 if (rc) {
1841 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
1842 return rc;
1843 }
1844 if (bp->flags & USING_MSI_FLAG) {
1845 bp->dev->irq = bp->pdev->irq;
1846 netdev_info(bp->dev, "using MSI IRQ %d\n",
1847 bp->dev->irq);
1848 }
1849 if (bp->flags & USING_MSIX_FLAG) {
1850 bp->dev->irq = bp->msix_table[0].vector;
1851 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1852 bp->dev->irq);
1853 }
1854 }
1855
1856 return 0;
1857 }
1858
bnx2x_napi_enable_cnic(struct bnx2x * bp)1859 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1860 {
1861 int i;
1862
1863 for_each_rx_queue_cnic(bp, i) {
1864 napi_enable(&bnx2x_fp(bp, i, napi));
1865 }
1866 }
1867
bnx2x_napi_enable(struct bnx2x * bp)1868 static void bnx2x_napi_enable(struct bnx2x *bp)
1869 {
1870 int i;
1871
1872 for_each_eth_queue(bp, i) {
1873 napi_enable(&bnx2x_fp(bp, i, napi));
1874 }
1875 }
1876
bnx2x_napi_disable_cnic(struct bnx2x * bp)1877 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1878 {
1879 int i;
1880
1881 for_each_rx_queue_cnic(bp, i) {
1882 napi_disable(&bnx2x_fp(bp, i, napi));
1883 }
1884 }
1885
bnx2x_napi_disable(struct bnx2x * bp)1886 static void bnx2x_napi_disable(struct bnx2x *bp)
1887 {
1888 int i;
1889
1890 for_each_eth_queue(bp, i) {
1891 napi_disable(&bnx2x_fp(bp, i, napi));
1892 }
1893 }
1894
bnx2x_netif_start(struct bnx2x * bp)1895 void bnx2x_netif_start(struct bnx2x *bp)
1896 {
1897 if (netif_running(bp->dev)) {
1898 bnx2x_napi_enable(bp);
1899 if (CNIC_LOADED(bp))
1900 bnx2x_napi_enable_cnic(bp);
1901 bnx2x_int_enable(bp);
1902 if (bp->state == BNX2X_STATE_OPEN)
1903 netif_tx_wake_all_queues(bp->dev);
1904 }
1905 }
1906
bnx2x_netif_stop(struct bnx2x * bp,int disable_hw)1907 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1908 {
1909 bnx2x_int_disable_sync(bp, disable_hw);
1910 bnx2x_napi_disable(bp);
1911 if (CNIC_LOADED(bp))
1912 bnx2x_napi_disable_cnic(bp);
1913 }
1914
bnx2x_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)1915 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
1916 struct net_device *sb_dev)
1917 {
1918 struct bnx2x *bp = netdev_priv(dev);
1919
1920 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1921 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1922 u16 ether_type = ntohs(hdr->h_proto);
1923
1924 /* Skip VLAN tag if present */
1925 if (ether_type == ETH_P_8021Q) {
1926 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
1927
1928 ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
1929 }
1930
1931 /* If ethertype is FCoE or FIP - use FCoE ring */
1932 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1933 return bnx2x_fcoe_tx(bp, txq_index);
1934 }
1935
1936 /* select a non-FCoE queue */
1937 return netdev_pick_tx(dev, skb, NULL) %
1938 (BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos);
1939 }
1940
bnx2x_set_num_queues(struct bnx2x * bp)1941 void bnx2x_set_num_queues(struct bnx2x *bp)
1942 {
1943 /* RSS queues */
1944 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1945
1946 /* override in STORAGE SD modes */
1947 if (IS_MF_STORAGE_ONLY(bp))
1948 bp->num_ethernet_queues = 1;
1949
1950 /* Add special queues */
1951 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1952 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1953
1954 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1955 }
1956
1957 /**
1958 * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1959 *
1960 * @bp: Driver handle
1961 * @include_cnic: handle cnic case
1962 *
1963 * We currently support for at most 16 Tx queues for each CoS thus we will
1964 * allocate a multiple of 16 for ETH L2 rings according to the value of the
1965 * bp->max_cos.
1966 *
1967 * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1968 * index after all ETH L2 indices.
1969 *
1970 * If the actual number of Tx queues (for each CoS) is less than 16 then there
1971 * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
1972 * 16..31,...) with indices that are not coupled with any real Tx queue.
1973 *
1974 * The proper configuration of skb->queue_mapping is handled by
1975 * bnx2x_select_queue() and __skb_tx_hash().
1976 *
1977 * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1978 * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1979 */
bnx2x_set_real_num_queues(struct bnx2x * bp,int include_cnic)1980 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1981 {
1982 int rc, tx, rx;
1983
1984 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1985 rx = BNX2X_NUM_ETH_QUEUES(bp);
1986
1987 /* account for fcoe queue */
1988 if (include_cnic && !NO_FCOE(bp)) {
1989 rx++;
1990 tx++;
1991 }
1992
1993 rc = netif_set_real_num_tx_queues(bp->dev, tx);
1994 if (rc) {
1995 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1996 return rc;
1997 }
1998 rc = netif_set_real_num_rx_queues(bp->dev, rx);
1999 if (rc) {
2000 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
2001 return rc;
2002 }
2003
2004 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
2005 tx, rx);
2006
2007 return rc;
2008 }
2009
bnx2x_set_rx_buf_size(struct bnx2x * bp)2010 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
2011 {
2012 int i;
2013
2014 for_each_queue(bp, i) {
2015 struct bnx2x_fastpath *fp = &bp->fp[i];
2016 u32 mtu;
2017
2018 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
2019 if (IS_FCOE_IDX(i))
2020 /*
2021 * Although there are no IP frames expected to arrive to
2022 * this ring we still want to add an
2023 * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
2024 * overrun attack.
2025 */
2026 mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2027 else
2028 mtu = bp->dev->mtu;
2029 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
2030 IP_HEADER_ALIGNMENT_PADDING +
2031 ETH_OVERHEAD +
2032 mtu +
2033 BNX2X_FW_RX_ALIGN_END;
2034 fp->rx_buf_size = SKB_DATA_ALIGN(fp->rx_buf_size);
2035 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
2036 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
2037 fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
2038 else
2039 fp->rx_frag_size = 0;
2040 }
2041 }
2042
bnx2x_init_rss(struct bnx2x * bp)2043 static int bnx2x_init_rss(struct bnx2x *bp)
2044 {
2045 int i;
2046 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2047
2048 /* Prepare the initial contents for the indirection table if RSS is
2049 * enabled
2050 */
2051 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2052 bp->rss_conf_obj.ind_table[i] =
2053 bp->fp->cl_id +
2054 ethtool_rxfh_indir_default(i, num_eth_queues);
2055
2056 /*
2057 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2058 * per-port, so if explicit configuration is needed , do it only
2059 * for a PMF.
2060 *
2061 * For 57712 and newer on the other hand it's a per-function
2062 * configuration.
2063 */
2064 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2065 }
2066
bnx2x_rss(struct bnx2x * bp,struct bnx2x_rss_config_obj * rss_obj,bool config_hash,bool enable)2067 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2068 bool config_hash, bool enable)
2069 {
2070 struct bnx2x_config_rss_params params = {NULL};
2071
2072 /* Although RSS is meaningless when there is a single HW queue we
2073 * still need it enabled in order to have HW Rx hash generated.
2074 *
2075 * if (!is_eth_multi(bp))
2076 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
2077 */
2078
2079 params.rss_obj = rss_obj;
2080
2081 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
2082
2083 if (enable) {
2084 __set_bit(BNX2X_RSS_MODE_REGULAR, ¶ms.rss_flags);
2085
2086 /* RSS configuration */
2087 __set_bit(BNX2X_RSS_IPV4, ¶ms.rss_flags);
2088 __set_bit(BNX2X_RSS_IPV4_TCP, ¶ms.rss_flags);
2089 __set_bit(BNX2X_RSS_IPV6, ¶ms.rss_flags);
2090 __set_bit(BNX2X_RSS_IPV6_TCP, ¶ms.rss_flags);
2091 if (rss_obj->udp_rss_v4)
2092 __set_bit(BNX2X_RSS_IPV4_UDP, ¶ms.rss_flags);
2093 if (rss_obj->udp_rss_v6)
2094 __set_bit(BNX2X_RSS_IPV6_UDP, ¶ms.rss_flags);
2095
2096 if (!CHIP_IS_E1x(bp)) {
2097 /* valid only for TUNN_MODE_VXLAN tunnel mode */
2098 __set_bit(BNX2X_RSS_IPV4_VXLAN, ¶ms.rss_flags);
2099 __set_bit(BNX2X_RSS_IPV6_VXLAN, ¶ms.rss_flags);
2100
2101 /* valid only for TUNN_MODE_GRE tunnel mode */
2102 __set_bit(BNX2X_RSS_TUNN_INNER_HDRS, ¶ms.rss_flags);
2103 }
2104 } else {
2105 __set_bit(BNX2X_RSS_MODE_DISABLED, ¶ms.rss_flags);
2106 }
2107
2108 /* Hash bits */
2109 params.rss_result_mask = MULTI_MASK;
2110
2111 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
2112
2113 if (config_hash) {
2114 /* RSS keys */
2115 netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4);
2116 __set_bit(BNX2X_RSS_SET_SRCH, ¶ms.rss_flags);
2117 }
2118
2119 if (IS_PF(bp))
2120 return bnx2x_config_rss(bp, ¶ms);
2121 else
2122 return bnx2x_vfpf_config_rss(bp, ¶ms);
2123 }
2124
bnx2x_init_hw(struct bnx2x * bp,u32 load_code)2125 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
2126 {
2127 struct bnx2x_func_state_params func_params = {NULL};
2128
2129 /* Prepare parameters for function state transitions */
2130 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2131
2132 func_params.f_obj = &bp->func_obj;
2133 func_params.cmd = BNX2X_F_CMD_HW_INIT;
2134
2135 func_params.params.hw_init.load_phase = load_code;
2136
2137 return bnx2x_func_state_change(bp, &func_params);
2138 }
2139
2140 /*
2141 * Cleans the object that have internal lists without sending
2142 * ramrods. Should be run when interrupts are disabled.
2143 */
bnx2x_squeeze_objects(struct bnx2x * bp)2144 void bnx2x_squeeze_objects(struct bnx2x *bp)
2145 {
2146 int rc;
2147 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2148 struct bnx2x_mcast_ramrod_params rparam = {NULL};
2149 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2150
2151 /***************** Cleanup MACs' object first *************************/
2152
2153 /* Wait for completion of requested */
2154 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2155 /* Perform a dry cleanup */
2156 __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2157
2158 /* Clean ETH primary MAC */
2159 __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2160 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2161 &ramrod_flags);
2162 if (rc != 0)
2163 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2164
2165 /* Cleanup UC list */
2166 vlan_mac_flags = 0;
2167 __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2168 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2169 &ramrod_flags);
2170 if (rc != 0)
2171 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2172
2173 /***************** Now clean mcast object *****************************/
2174 rparam.mcast_obj = &bp->mcast_obj;
2175 __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2176
2177 /* Add a DEL command... - Since we're doing a driver cleanup only,
2178 * we take a lock surrounding both the initial send and the CONTs,
2179 * as we don't want a true completion to disrupt us in the middle.
2180 */
2181 netif_addr_lock_bh(bp->dev);
2182 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2183 if (rc < 0)
2184 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2185 rc);
2186
2187 /* ...and wait until all pending commands are cleared */
2188 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2189 while (rc != 0) {
2190 if (rc < 0) {
2191 BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2192 rc);
2193 netif_addr_unlock_bh(bp->dev);
2194 return;
2195 }
2196
2197 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2198 }
2199 netif_addr_unlock_bh(bp->dev);
2200 }
2201
2202 #ifndef BNX2X_STOP_ON_ERROR
2203 #define LOAD_ERROR_EXIT(bp, label) \
2204 do { \
2205 (bp)->state = BNX2X_STATE_ERROR; \
2206 goto label; \
2207 } while (0)
2208
2209 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2210 do { \
2211 bp->cnic_loaded = false; \
2212 goto label; \
2213 } while (0)
2214 #else /*BNX2X_STOP_ON_ERROR*/
2215 #define LOAD_ERROR_EXIT(bp, label) \
2216 do { \
2217 (bp)->state = BNX2X_STATE_ERROR; \
2218 (bp)->panic = 1; \
2219 return -EBUSY; \
2220 } while (0)
2221 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2222 do { \
2223 bp->cnic_loaded = false; \
2224 (bp)->panic = 1; \
2225 return -EBUSY; \
2226 } while (0)
2227 #endif /*BNX2X_STOP_ON_ERROR*/
2228
bnx2x_free_fw_stats_mem(struct bnx2x * bp)2229 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2230 {
2231 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2232 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2233 return;
2234 }
2235
bnx2x_alloc_fw_stats_mem(struct bnx2x * bp)2236 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2237 {
2238 int num_groups, vf_headroom = 0;
2239 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2240
2241 /* number of queues for statistics is number of eth queues + FCoE */
2242 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2243
2244 /* Total number of FW statistics requests =
2245 * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2246 * and fcoe l2 queue) stats + num of queues (which includes another 1
2247 * for fcoe l2 queue if applicable)
2248 */
2249 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2250
2251 /* vf stats appear in the request list, but their data is allocated by
2252 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2253 * it is used to determine where to place the vf stats queries in the
2254 * request struct
2255 */
2256 if (IS_SRIOV(bp))
2257 vf_headroom = bnx2x_vf_headroom(bp);
2258
2259 /* Request is built from stats_query_header and an array of
2260 * stats_query_cmd_group each of which contains
2261 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2262 * configured in the stats_query_header.
2263 */
2264 num_groups =
2265 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2266 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2267 1 : 0));
2268
2269 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2270 bp->fw_stats_num, vf_headroom, num_groups);
2271 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2272 num_groups * sizeof(struct stats_query_cmd_group);
2273
2274 /* Data for statistics requests + stats_counter
2275 * stats_counter holds per-STORM counters that are incremented
2276 * when STORM has finished with the current request.
2277 * memory for FCoE offloaded statistics are counted anyway,
2278 * even if they will not be sent.
2279 * VF stats are not accounted for here as the data of VF stats is stored
2280 * in memory allocated by the VF, not here.
2281 */
2282 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2283 sizeof(struct per_pf_stats) +
2284 sizeof(struct fcoe_statistics_params) +
2285 sizeof(struct per_queue_stats) * num_queue_stats +
2286 sizeof(struct stats_counter);
2287
2288 bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2289 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2290 if (!bp->fw_stats)
2291 goto alloc_mem_err;
2292
2293 /* Set shortcuts */
2294 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2295 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2296 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2297 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2298 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2299 bp->fw_stats_req_sz;
2300
2301 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
2302 U64_HI(bp->fw_stats_req_mapping),
2303 U64_LO(bp->fw_stats_req_mapping));
2304 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
2305 U64_HI(bp->fw_stats_data_mapping),
2306 U64_LO(bp->fw_stats_data_mapping));
2307 return 0;
2308
2309 alloc_mem_err:
2310 bnx2x_free_fw_stats_mem(bp);
2311 BNX2X_ERR("Can't allocate FW stats memory\n");
2312 return -ENOMEM;
2313 }
2314
2315 /* send load request to mcp and analyze response */
bnx2x_nic_load_request(struct bnx2x * bp,u32 * load_code)2316 static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2317 {
2318 u32 param;
2319
2320 /* init fw_seq */
2321 bp->fw_seq =
2322 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2323 DRV_MSG_SEQ_NUMBER_MASK);
2324 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2325
2326 /* Get current FW pulse sequence */
2327 bp->fw_drv_pulse_wr_seq =
2328 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2329 DRV_PULSE_SEQ_MASK);
2330 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2331
2332 param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2333
2334 if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2335 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2336
2337 /* load request */
2338 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2339
2340 /* if mcp fails to respond we must abort */
2341 if (!(*load_code)) {
2342 BNX2X_ERR("MCP response failure, aborting\n");
2343 return -EBUSY;
2344 }
2345
2346 /* If mcp refused (e.g. other port is in diagnostic mode) we
2347 * must abort
2348 */
2349 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2350 BNX2X_ERR("MCP refused load request, aborting\n");
2351 return -EBUSY;
2352 }
2353 return 0;
2354 }
2355
2356 /* check whether another PF has already loaded FW to chip. In
2357 * virtualized environments a pf from another VM may have already
2358 * initialized the device including loading FW
2359 */
bnx2x_compare_fw_ver(struct bnx2x * bp,u32 load_code,bool print_err)2360 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err)
2361 {
2362 /* is another pf loaded on this engine? */
2363 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2364 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2365 u8 loaded_fw_major, loaded_fw_minor, loaded_fw_rev, loaded_fw_eng;
2366 u32 loaded_fw;
2367
2368 /* read loaded FW from chip */
2369 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2370
2371 loaded_fw_major = loaded_fw & 0xff;
2372 loaded_fw_minor = (loaded_fw >> 8) & 0xff;
2373 loaded_fw_rev = (loaded_fw >> 16) & 0xff;
2374 loaded_fw_eng = (loaded_fw >> 24) & 0xff;
2375
2376 DP(BNX2X_MSG_SP, "loaded fw 0x%x major 0x%x minor 0x%x rev 0x%x eng 0x%x\n",
2377 loaded_fw, loaded_fw_major, loaded_fw_minor, loaded_fw_rev, loaded_fw_eng);
2378
2379 /* abort nic load if version mismatch */
2380 if (loaded_fw_major != BCM_5710_FW_MAJOR_VERSION ||
2381 loaded_fw_minor != BCM_5710_FW_MINOR_VERSION ||
2382 loaded_fw_eng != BCM_5710_FW_ENGINEERING_VERSION ||
2383 loaded_fw_rev < BCM_5710_FW_REVISION_VERSION_V15) {
2384 if (print_err)
2385 BNX2X_ERR("loaded FW incompatible. Aborting\n");
2386 else
2387 BNX2X_DEV_INFO("loaded FW incompatible, possibly due to MF UNDI\n");
2388
2389 return -EBUSY;
2390 }
2391 }
2392 return 0;
2393 }
2394
2395 /* returns the "mcp load_code" according to global load_count array */
bnx2x_nic_load_no_mcp(struct bnx2x * bp,int port)2396 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2397 {
2398 int path = BP_PATH(bp);
2399
2400 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n",
2401 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2402 bnx2x_load_count[path][2]);
2403 bnx2x_load_count[path][0]++;
2404 bnx2x_load_count[path][1 + port]++;
2405 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n",
2406 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2407 bnx2x_load_count[path][2]);
2408 if (bnx2x_load_count[path][0] == 1)
2409 return FW_MSG_CODE_DRV_LOAD_COMMON;
2410 else if (bnx2x_load_count[path][1 + port] == 1)
2411 return FW_MSG_CODE_DRV_LOAD_PORT;
2412 else
2413 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2414 }
2415
2416 /* mark PMF if applicable */
bnx2x_nic_load_pmf(struct bnx2x * bp,u32 load_code)2417 static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2418 {
2419 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2420 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2421 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2422 bp->port.pmf = 1;
2423 /* We need the barrier to ensure the ordering between the
2424 * writing to bp->port.pmf here and reading it from the
2425 * bnx2x_periodic_task().
2426 */
2427 smp_mb();
2428 } else {
2429 bp->port.pmf = 0;
2430 }
2431
2432 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2433 }
2434
bnx2x_nic_load_afex_dcc(struct bnx2x * bp,int load_code)2435 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2436 {
2437 if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2438 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2439 (bp->common.shmem2_base)) {
2440 if (SHMEM2_HAS(bp, dcc_support))
2441 SHMEM2_WR(bp, dcc_support,
2442 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2443 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2444 if (SHMEM2_HAS(bp, afex_driver_support))
2445 SHMEM2_WR(bp, afex_driver_support,
2446 SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2447 }
2448
2449 /* Set AFEX default VLAN tag to an invalid value */
2450 bp->afex_def_vlan_tag = -1;
2451 }
2452
2453 /**
2454 * bnx2x_bz_fp - zero content of the fastpath structure.
2455 *
2456 * @bp: driver handle
2457 * @index: fastpath index to be zeroed
2458 *
2459 * Makes sure the contents of the bp->fp[index].napi is kept
2460 * intact.
2461 */
bnx2x_bz_fp(struct bnx2x * bp,int index)2462 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2463 {
2464 struct bnx2x_fastpath *fp = &bp->fp[index];
2465 int cos;
2466 struct napi_struct orig_napi = fp->napi;
2467 struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2468
2469 /* bzero bnx2x_fastpath contents */
2470 if (fp->tpa_info)
2471 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2472 sizeof(struct bnx2x_agg_info));
2473 memset(fp, 0, sizeof(*fp));
2474
2475 /* Restore the NAPI object as it has been already initialized */
2476 fp->napi = orig_napi;
2477 fp->tpa_info = orig_tpa_info;
2478 fp->bp = bp;
2479 fp->index = index;
2480 if (IS_ETH_FP(fp))
2481 fp->max_cos = bp->max_cos;
2482 else
2483 /* Special queues support only one CoS */
2484 fp->max_cos = 1;
2485
2486 /* Init txdata pointers */
2487 if (IS_FCOE_FP(fp))
2488 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2489 if (IS_ETH_FP(fp))
2490 for_each_cos_in_tx_queue(fp, cos)
2491 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2492 BNX2X_NUM_ETH_QUEUES(bp) + index];
2493
2494 /* set the tpa flag for each queue. The tpa flag determines the queue
2495 * minimal size so it must be set prior to queue memory allocation
2496 */
2497 if (bp->dev->features & NETIF_F_LRO)
2498 fp->mode = TPA_MODE_LRO;
2499 else if (bp->dev->features & NETIF_F_GRO_HW)
2500 fp->mode = TPA_MODE_GRO;
2501 else
2502 fp->mode = TPA_MODE_DISABLED;
2503
2504 /* We don't want TPA if it's disabled in bp
2505 * or if this is an FCoE L2 ring.
2506 */
2507 if (bp->disable_tpa || IS_FCOE_FP(fp))
2508 fp->mode = TPA_MODE_DISABLED;
2509 }
2510
bnx2x_set_os_driver_state(struct bnx2x * bp,u32 state)2511 void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state)
2512 {
2513 u32 cur;
2514
2515 if (!IS_MF_BD(bp) || !SHMEM2_HAS(bp, os_driver_state) || IS_VF(bp))
2516 return;
2517
2518 cur = SHMEM2_RD(bp, os_driver_state[BP_FW_MB_IDX(bp)]);
2519 DP(NETIF_MSG_IFUP, "Driver state %08x-->%08x\n",
2520 cur, state);
2521
2522 SHMEM2_WR(bp, os_driver_state[BP_FW_MB_IDX(bp)], state);
2523 }
2524
bnx2x_load_cnic(struct bnx2x * bp)2525 int bnx2x_load_cnic(struct bnx2x *bp)
2526 {
2527 int i, rc, port = BP_PORT(bp);
2528
2529 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2530
2531 mutex_init(&bp->cnic_mutex);
2532
2533 if (IS_PF(bp)) {
2534 rc = bnx2x_alloc_mem_cnic(bp);
2535 if (rc) {
2536 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2537 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2538 }
2539 }
2540
2541 rc = bnx2x_alloc_fp_mem_cnic(bp);
2542 if (rc) {
2543 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2544 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2545 }
2546
2547 /* Update the number of queues with the cnic queues */
2548 rc = bnx2x_set_real_num_queues(bp, 1);
2549 if (rc) {
2550 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2551 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2552 }
2553
2554 /* Add all CNIC NAPI objects */
2555 bnx2x_add_all_napi_cnic(bp);
2556 DP(NETIF_MSG_IFUP, "cnic napi added\n");
2557 bnx2x_napi_enable_cnic(bp);
2558
2559 rc = bnx2x_init_hw_func_cnic(bp);
2560 if (rc)
2561 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2562
2563 bnx2x_nic_init_cnic(bp);
2564
2565 if (IS_PF(bp)) {
2566 /* Enable Timer scan */
2567 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2568
2569 /* setup cnic queues */
2570 for_each_cnic_queue(bp, i) {
2571 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2572 if (rc) {
2573 BNX2X_ERR("Queue setup failed\n");
2574 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2575 }
2576 }
2577 }
2578
2579 /* Initialize Rx filter. */
2580 bnx2x_set_rx_mode_inner(bp);
2581
2582 /* re-read iscsi info */
2583 bnx2x_get_iscsi_info(bp);
2584 bnx2x_setup_cnic_irq_info(bp);
2585 bnx2x_setup_cnic_info(bp);
2586 bp->cnic_loaded = true;
2587 if (bp->state == BNX2X_STATE_OPEN)
2588 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2589
2590 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2591
2592 return 0;
2593
2594 #ifndef BNX2X_STOP_ON_ERROR
2595 load_error_cnic2:
2596 /* Disable Timer scan */
2597 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2598
2599 load_error_cnic1:
2600 bnx2x_napi_disable_cnic(bp);
2601 /* Update the number of queues without the cnic queues */
2602 if (bnx2x_set_real_num_queues(bp, 0))
2603 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2604 load_error_cnic0:
2605 BNX2X_ERR("CNIC-related load failed\n");
2606 bnx2x_free_fp_mem_cnic(bp);
2607 bnx2x_free_mem_cnic(bp);
2608 return rc;
2609 #endif /* ! BNX2X_STOP_ON_ERROR */
2610 }
2611
2612 /* must be called with rtnl_lock */
bnx2x_nic_load(struct bnx2x * bp,int load_mode)2613 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2614 {
2615 int port = BP_PORT(bp);
2616 int i, rc = 0, load_code = 0;
2617
2618 DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2619 DP(NETIF_MSG_IFUP,
2620 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2621
2622 #ifdef BNX2X_STOP_ON_ERROR
2623 if (unlikely(bp->panic)) {
2624 BNX2X_ERR("Can't load NIC when there is panic\n");
2625 return -EPERM;
2626 }
2627 #endif
2628
2629 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2630
2631 /* zero the structure w/o any lock, before SP handler is initialized */
2632 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2633 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2634 &bp->last_reported_link.link_report_flags);
2635
2636 if (IS_PF(bp))
2637 /* must be called before memory allocation and HW init */
2638 bnx2x_ilt_set_info(bp);
2639
2640 /*
2641 * Zero fastpath structures preserving invariants like napi, which are
2642 * allocated only once, fp index, max_cos, bp pointer.
2643 * Also set fp->mode and txdata_ptr.
2644 */
2645 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2646 for_each_queue(bp, i)
2647 bnx2x_bz_fp(bp, i);
2648 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2649 bp->num_cnic_queues) *
2650 sizeof(struct bnx2x_fp_txdata));
2651
2652 bp->fcoe_init = false;
2653
2654 /* Set the receive queues buffer size */
2655 bnx2x_set_rx_buf_size(bp);
2656
2657 if (IS_PF(bp)) {
2658 rc = bnx2x_alloc_mem(bp);
2659 if (rc) {
2660 BNX2X_ERR("Unable to allocate bp memory\n");
2661 return rc;
2662 }
2663 }
2664
2665 /* need to be done after alloc mem, since it's self adjusting to amount
2666 * of memory available for RSS queues
2667 */
2668 rc = bnx2x_alloc_fp_mem(bp);
2669 if (rc) {
2670 BNX2X_ERR("Unable to allocate memory for fps\n");
2671 LOAD_ERROR_EXIT(bp, load_error0);
2672 }
2673
2674 /* Allocated memory for FW statistics */
2675 rc = bnx2x_alloc_fw_stats_mem(bp);
2676 if (rc)
2677 LOAD_ERROR_EXIT(bp, load_error0);
2678
2679 /* request pf to initialize status blocks */
2680 if (IS_VF(bp)) {
2681 rc = bnx2x_vfpf_init(bp);
2682 if (rc)
2683 LOAD_ERROR_EXIT(bp, load_error0);
2684 }
2685
2686 /* As long as bnx2x_alloc_mem() may possibly update
2687 * bp->num_queues, bnx2x_set_real_num_queues() should always
2688 * come after it. At this stage cnic queues are not counted.
2689 */
2690 rc = bnx2x_set_real_num_queues(bp, 0);
2691 if (rc) {
2692 BNX2X_ERR("Unable to set real_num_queues\n");
2693 LOAD_ERROR_EXIT(bp, load_error0);
2694 }
2695
2696 /* configure multi cos mappings in kernel.
2697 * this configuration may be overridden by a multi class queue
2698 * discipline or by a dcbx negotiation result.
2699 */
2700 bnx2x_setup_tc(bp->dev, bp->max_cos);
2701
2702 /* Add all NAPI objects */
2703 bnx2x_add_all_napi(bp);
2704 DP(NETIF_MSG_IFUP, "napi added\n");
2705 bnx2x_napi_enable(bp);
2706
2707 if (IS_PF(bp)) {
2708 /* set pf load just before approaching the MCP */
2709 bnx2x_set_pf_load(bp);
2710
2711 /* if mcp exists send load request and analyze response */
2712 if (!BP_NOMCP(bp)) {
2713 /* attempt to load pf */
2714 rc = bnx2x_nic_load_request(bp, &load_code);
2715 if (rc)
2716 LOAD_ERROR_EXIT(bp, load_error1);
2717
2718 /* what did mcp say? */
2719 rc = bnx2x_compare_fw_ver(bp, load_code, true);
2720 if (rc) {
2721 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2722 LOAD_ERROR_EXIT(bp, load_error2);
2723 }
2724 } else {
2725 load_code = bnx2x_nic_load_no_mcp(bp, port);
2726 }
2727
2728 /* mark pmf if applicable */
2729 bnx2x_nic_load_pmf(bp, load_code);
2730
2731 /* Init Function state controlling object */
2732 bnx2x__init_func_obj(bp);
2733
2734 /* Initialize HW */
2735 rc = bnx2x_init_hw(bp, load_code);
2736 if (rc) {
2737 BNX2X_ERR("HW init failed, aborting\n");
2738 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2739 LOAD_ERROR_EXIT(bp, load_error2);
2740 }
2741 }
2742
2743 bnx2x_pre_irq_nic_init(bp);
2744
2745 /* Connect to IRQs */
2746 rc = bnx2x_setup_irqs(bp);
2747 if (rc) {
2748 BNX2X_ERR("setup irqs failed\n");
2749 if (IS_PF(bp))
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2751 LOAD_ERROR_EXIT(bp, load_error2);
2752 }
2753
2754 /* Init per-function objects */
2755 if (IS_PF(bp)) {
2756 /* Setup NIC internals and enable interrupts */
2757 bnx2x_post_irq_nic_init(bp, load_code);
2758
2759 bnx2x_init_bp_objs(bp);
2760 bnx2x_iov_nic_init(bp);
2761
2762 /* Set AFEX default VLAN tag to an invalid value */
2763 bp->afex_def_vlan_tag = -1;
2764 bnx2x_nic_load_afex_dcc(bp, load_code);
2765 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2766 rc = bnx2x_func_start(bp);
2767 if (rc) {
2768 BNX2X_ERR("Function start failed!\n");
2769 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2770
2771 LOAD_ERROR_EXIT(bp, load_error3);
2772 }
2773
2774 /* Send LOAD_DONE command to MCP */
2775 if (!BP_NOMCP(bp)) {
2776 load_code = bnx2x_fw_command(bp,
2777 DRV_MSG_CODE_LOAD_DONE, 0);
2778 if (!load_code) {
2779 BNX2X_ERR("MCP response failure, aborting\n");
2780 rc = -EBUSY;
2781 LOAD_ERROR_EXIT(bp, load_error3);
2782 }
2783 }
2784
2785 /* initialize FW coalescing state machines in RAM */
2786 bnx2x_update_coalesce(bp);
2787 }
2788
2789 /* setup the leading queue */
2790 rc = bnx2x_setup_leading(bp);
2791 if (rc) {
2792 BNX2X_ERR("Setup leading failed!\n");
2793 LOAD_ERROR_EXIT(bp, load_error3);
2794 }
2795
2796 /* set up the rest of the queues */
2797 for_each_nondefault_eth_queue(bp, i) {
2798 if (IS_PF(bp))
2799 rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2800 else /* VF */
2801 rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2802 if (rc) {
2803 BNX2X_ERR("Queue %d setup failed\n", i);
2804 LOAD_ERROR_EXIT(bp, load_error3);
2805 }
2806 }
2807
2808 /* setup rss */
2809 rc = bnx2x_init_rss(bp);
2810 if (rc) {
2811 BNX2X_ERR("PF RSS init failed\n");
2812 LOAD_ERROR_EXIT(bp, load_error3);
2813 }
2814
2815 /* Now when Clients are configured we are ready to work */
2816 bp->state = BNX2X_STATE_OPEN;
2817
2818 /* Configure a ucast MAC */
2819 if (IS_PF(bp))
2820 rc = bnx2x_set_eth_mac(bp, true);
2821 else /* vf */
2822 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2823 true);
2824 if (rc) {
2825 BNX2X_ERR("Setting Ethernet MAC failed\n");
2826 LOAD_ERROR_EXIT(bp, load_error3);
2827 }
2828
2829 if (IS_PF(bp) && bp->pending_max) {
2830 bnx2x_update_max_mf_config(bp, bp->pending_max);
2831 bp->pending_max = 0;
2832 }
2833
2834 bp->force_link_down = false;
2835 if (bp->port.pmf) {
2836 rc = bnx2x_initial_phy_init(bp, load_mode);
2837 if (rc)
2838 LOAD_ERROR_EXIT(bp, load_error3);
2839 }
2840 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2841
2842 /* Start fast path */
2843
2844 /* Re-configure vlan filters */
2845 rc = bnx2x_vlan_reconfigure_vid(bp);
2846 if (rc)
2847 LOAD_ERROR_EXIT(bp, load_error3);
2848
2849 /* Initialize Rx filter. */
2850 bnx2x_set_rx_mode_inner(bp);
2851
2852 if (bp->flags & PTP_SUPPORTED) {
2853 bnx2x_register_phc(bp);
2854 bnx2x_init_ptp(bp);
2855 bnx2x_configure_ptp_filters(bp);
2856 }
2857 /* Start Tx */
2858 switch (load_mode) {
2859 case LOAD_NORMAL:
2860 /* Tx queue should be only re-enabled */
2861 netif_tx_wake_all_queues(bp->dev);
2862 break;
2863
2864 case LOAD_OPEN:
2865 netif_tx_start_all_queues(bp->dev);
2866 smp_mb__after_atomic();
2867 break;
2868
2869 case LOAD_DIAG:
2870 case LOAD_LOOPBACK_EXT:
2871 bp->state = BNX2X_STATE_DIAG;
2872 break;
2873
2874 default:
2875 break;
2876 }
2877
2878 if (bp->port.pmf)
2879 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2880 else
2881 bnx2x__link_status_update(bp);
2882
2883 /* start the timer */
2884 mod_timer(&bp->timer, jiffies + bp->current_interval);
2885
2886 if (CNIC_ENABLED(bp))
2887 bnx2x_load_cnic(bp);
2888
2889 if (IS_PF(bp))
2890 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2891
2892 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2893 /* mark driver is loaded in shmem2 */
2894 u32 val;
2895 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2896 val &= ~DRV_FLAGS_MTU_MASK;
2897 val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT);
2898 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2899 val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2900 DRV_FLAGS_CAPABILITIES_LOADED_L2);
2901 }
2902
2903 /* Wait for all pending SP commands to complete */
2904 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2905 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2906 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2907 return -EBUSY;
2908 }
2909
2910 /* Update driver data for On-Chip MFW dump. */
2911 if (IS_PF(bp))
2912 bnx2x_update_mfw_dump(bp);
2913
2914 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2915 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2916 bnx2x_dcbx_init(bp, false);
2917
2918 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
2919 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_ACTIVE);
2920
2921 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2922
2923 return 0;
2924
2925 #ifndef BNX2X_STOP_ON_ERROR
2926 load_error3:
2927 if (IS_PF(bp)) {
2928 bnx2x_int_disable_sync(bp, 1);
2929
2930 /* Clean queueable objects */
2931 bnx2x_squeeze_objects(bp);
2932 }
2933
2934 /* Free SKBs, SGEs, TPA pool and driver internals */
2935 bnx2x_free_skbs(bp);
2936 for_each_rx_queue(bp, i)
2937 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2938
2939 /* Release IRQs */
2940 bnx2x_free_irq(bp);
2941 load_error2:
2942 if (IS_PF(bp) && !BP_NOMCP(bp)) {
2943 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2944 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2945 }
2946
2947 bp->port.pmf = 0;
2948 load_error1:
2949 bnx2x_napi_disable(bp);
2950 bnx2x_del_all_napi(bp);
2951
2952 /* clear pf_load status, as it was already set */
2953 if (IS_PF(bp))
2954 bnx2x_clear_pf_load(bp);
2955 load_error0:
2956 bnx2x_free_fw_stats_mem(bp);
2957 bnx2x_free_fp_mem(bp);
2958 bnx2x_free_mem(bp);
2959
2960 return rc;
2961 #endif /* ! BNX2X_STOP_ON_ERROR */
2962 }
2963
bnx2x_drain_tx_queues(struct bnx2x * bp)2964 int bnx2x_drain_tx_queues(struct bnx2x *bp)
2965 {
2966 u8 rc = 0, cos, i;
2967
2968 /* Wait until tx fastpath tasks complete */
2969 for_each_tx_queue(bp, i) {
2970 struct bnx2x_fastpath *fp = &bp->fp[i];
2971
2972 for_each_cos_in_tx_queue(fp, cos)
2973 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2974 if (rc)
2975 return rc;
2976 }
2977 return 0;
2978 }
2979
2980 /* must be called with rtnl_lock */
bnx2x_nic_unload(struct bnx2x * bp,int unload_mode,bool keep_link)2981 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2982 {
2983 int i;
2984 bool global = false;
2985
2986 DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2987
2988 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
2989 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
2990
2991 /* mark driver is unloaded in shmem2 */
2992 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2993 u32 val;
2994 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2995 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2996 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2997 }
2998
2999 if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
3000 (bp->state == BNX2X_STATE_CLOSED ||
3001 bp->state == BNX2X_STATE_ERROR)) {
3002 /* We can get here if the driver has been unloaded
3003 * during parity error recovery and is either waiting for a
3004 * leader to complete or for other functions to unload and
3005 * then ifdown has been issued. In this case we want to
3006 * unload and let other functions to complete a recovery
3007 * process.
3008 */
3009 bp->recovery_state = BNX2X_RECOVERY_DONE;
3010 bp->is_leader = 0;
3011 bnx2x_release_leader_lock(bp);
3012 smp_mb();
3013
3014 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
3015 BNX2X_ERR("Can't unload in closed or error state\n");
3016 return -EINVAL;
3017 }
3018
3019 /* Nothing to do during unload if previous bnx2x_nic_load()
3020 * have not completed successfully - all resources are released.
3021 *
3022 * we can get here only after unsuccessful ndo_* callback, during which
3023 * dev->IFF_UP flag is still on.
3024 */
3025 if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
3026 return 0;
3027
3028 /* It's important to set the bp->state to the value different from
3029 * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
3030 * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
3031 */
3032 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
3033 smp_mb();
3034
3035 /* indicate to VFs that the PF is going down */
3036 bnx2x_iov_channel_down(bp);
3037
3038 if (CNIC_LOADED(bp))
3039 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
3040
3041 /* Stop Tx */
3042 bnx2x_tx_disable(bp);
3043 netdev_reset_tc(bp->dev);
3044
3045 bp->rx_mode = BNX2X_RX_MODE_NONE;
3046
3047 del_timer_sync(&bp->timer);
3048
3049 if (IS_PF(bp) && !BP_NOMCP(bp)) {
3050 /* Set ALWAYS_ALIVE bit in shmem */
3051 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
3052 bnx2x_drv_pulse(bp);
3053 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
3054 bnx2x_save_statistics(bp);
3055 }
3056
3057 /* wait till consumers catch up with producers in all queues.
3058 * If we're recovering, FW can't write to host so no reason
3059 * to wait for the queues to complete all Tx.
3060 */
3061 if (unload_mode != UNLOAD_RECOVERY)
3062 bnx2x_drain_tx_queues(bp);
3063
3064 /* if VF indicate to PF this function is going down (PF will delete sp
3065 * elements and clear initializations
3066 */
3067 if (IS_VF(bp)) {
3068 bnx2x_clear_vlan_info(bp);
3069 bnx2x_vfpf_close_vf(bp);
3070 } else if (unload_mode != UNLOAD_RECOVERY) {
3071 /* if this is a normal/close unload need to clean up chip*/
3072 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3073 } else {
3074 /* Send the UNLOAD_REQUEST to the MCP */
3075 bnx2x_send_unload_req(bp, unload_mode);
3076
3077 /* Prevent transactions to host from the functions on the
3078 * engine that doesn't reset global blocks in case of global
3079 * attention once global blocks are reset and gates are opened
3080 * (the engine which leader will perform the recovery
3081 * last).
3082 */
3083 if (!CHIP_IS_E1x(bp))
3084 bnx2x_pf_disable(bp);
3085
3086 /* Disable HW interrupts, NAPI */
3087 bnx2x_netif_stop(bp, 1);
3088 /* Delete all NAPI objects */
3089 bnx2x_del_all_napi(bp);
3090 if (CNIC_LOADED(bp))
3091 bnx2x_del_all_napi_cnic(bp);
3092 /* Release IRQs */
3093 bnx2x_free_irq(bp);
3094
3095 /* Report UNLOAD_DONE to MCP */
3096 bnx2x_send_unload_done(bp, false);
3097 }
3098
3099 /*
3100 * At this stage no more interrupts will arrive so we may safely clean
3101 * the queueable objects here in case they failed to get cleaned so far.
3102 */
3103 if (IS_PF(bp))
3104 bnx2x_squeeze_objects(bp);
3105
3106 /* There should be no more pending SP commands at this stage */
3107 bp->sp_state = 0;
3108
3109 bp->port.pmf = 0;
3110
3111 /* clear pending work in rtnl task */
3112 bp->sp_rtnl_state = 0;
3113 smp_mb();
3114
3115 /* Free SKBs, SGEs, TPA pool and driver internals */
3116 bnx2x_free_skbs(bp);
3117 if (CNIC_LOADED(bp))
3118 bnx2x_free_skbs_cnic(bp);
3119 for_each_rx_queue(bp, i)
3120 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3121
3122 bnx2x_free_fp_mem(bp);
3123 if (CNIC_LOADED(bp))
3124 bnx2x_free_fp_mem_cnic(bp);
3125
3126 if (IS_PF(bp)) {
3127 if (CNIC_LOADED(bp))
3128 bnx2x_free_mem_cnic(bp);
3129 }
3130 bnx2x_free_mem(bp);
3131
3132 bp->state = BNX2X_STATE_CLOSED;
3133 bp->cnic_loaded = false;
3134
3135 /* Clear driver version indication in shmem */
3136 if (IS_PF(bp) && !BP_NOMCP(bp))
3137 bnx2x_update_mng_version(bp);
3138
3139 /* Check if there are pending parity attentions. If there are - set
3140 * RECOVERY_IN_PROGRESS.
3141 */
3142 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3143 bnx2x_set_reset_in_progress(bp);
3144
3145 /* Set RESET_IS_GLOBAL if needed */
3146 if (global)
3147 bnx2x_set_reset_global(bp);
3148 }
3149
3150 /* The last driver must disable a "close the gate" if there is no
3151 * parity attention or "process kill" pending.
3152 */
3153 if (IS_PF(bp) &&
3154 !bnx2x_clear_pf_load(bp) &&
3155 bnx2x_reset_is_done(bp, BP_PATH(bp)))
3156 bnx2x_disable_close_the_gate(bp);
3157
3158 DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
3159
3160 return 0;
3161 }
3162
bnx2x_set_power_state(struct bnx2x * bp,pci_power_t state)3163 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
3164 {
3165 u16 pmcsr;
3166
3167 /* If there is no power capability, silently succeed */
3168 if (!bp->pdev->pm_cap) {
3169 BNX2X_DEV_INFO("No power capability. Breaking.\n");
3170 return 0;
3171 }
3172
3173 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
3174
3175 switch (state) {
3176 case PCI_D0:
3177 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3178 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3179 PCI_PM_CTRL_PME_STATUS));
3180
3181 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3182 /* delay required during transition out of D3hot */
3183 msleep(20);
3184 break;
3185
3186 case PCI_D3hot:
3187 /* If there are other clients above don't
3188 shut down the power */
3189 if (atomic_read(&bp->pdev->enable_cnt) != 1)
3190 return 0;
3191 /* Don't shut down the power for emulation and FPGA */
3192 if (CHIP_REV_IS_SLOW(bp))
3193 return 0;
3194
3195 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3196 pmcsr |= 3;
3197
3198 if (bp->wol)
3199 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3200
3201 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3202 pmcsr);
3203
3204 /* No more memory access after this point until
3205 * device is brought back to D0.
3206 */
3207 break;
3208
3209 default:
3210 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
3211 return -EINVAL;
3212 }
3213 return 0;
3214 }
3215
3216 /*
3217 * net_device service functions
3218 */
bnx2x_poll(struct napi_struct * napi,int budget)3219 static int bnx2x_poll(struct napi_struct *napi, int budget)
3220 {
3221 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3222 napi);
3223 struct bnx2x *bp = fp->bp;
3224 int rx_work_done;
3225 u8 cos;
3226
3227 #ifdef BNX2X_STOP_ON_ERROR
3228 if (unlikely(bp->panic)) {
3229 napi_complete(napi);
3230 return 0;
3231 }
3232 #endif
3233 for_each_cos_in_tx_queue(fp, cos)
3234 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
3235 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
3236
3237 rx_work_done = (bnx2x_has_rx_work(fp)) ? bnx2x_rx_int(fp, budget) : 0;
3238
3239 if (rx_work_done < budget) {
3240 /* No need to update SB for FCoE L2 ring as long as
3241 * it's connected to the default SB and the SB
3242 * has been updated when NAPI was scheduled.
3243 */
3244 if (IS_FCOE_FP(fp)) {
3245 napi_complete_done(napi, rx_work_done);
3246 } else {
3247 bnx2x_update_fpsb_idx(fp);
3248 /* bnx2x_has_rx_work() reads the status block,
3249 * thus we need to ensure that status block indices
3250 * have been actually read (bnx2x_update_fpsb_idx)
3251 * prior to this check (bnx2x_has_rx_work) so that
3252 * we won't write the "newer" value of the status block
3253 * to IGU (if there was a DMA right after
3254 * bnx2x_has_rx_work and if there is no rmb, the memory
3255 * reading (bnx2x_update_fpsb_idx) may be postponed
3256 * to right before bnx2x_ack_sb). In this case there
3257 * will never be another interrupt until there is
3258 * another update of the status block, while there
3259 * is still unhandled work.
3260 */
3261 rmb();
3262
3263 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3264 if (napi_complete_done(napi, rx_work_done)) {
3265 /* Re-enable interrupts */
3266 DP(NETIF_MSG_RX_STATUS,
3267 "Update index to %d\n", fp->fp_hc_idx);
3268 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3269 le16_to_cpu(fp->fp_hc_idx),
3270 IGU_INT_ENABLE, 1);
3271 }
3272 } else {
3273 rx_work_done = budget;
3274 }
3275 }
3276 }
3277
3278 return rx_work_done;
3279 }
3280
3281 /* we split the first BD into headers and data BDs
3282 * to ease the pain of our fellow microcode engineers
3283 * we use one mapping for both BDs
3284 */
bnx2x_tx_split(struct bnx2x * bp,struct bnx2x_fp_txdata * txdata,struct sw_tx_bd * tx_buf,struct eth_tx_start_bd ** tx_bd,u16 hlen,u16 bd_prod)3285 static u16 bnx2x_tx_split(struct bnx2x *bp,
3286 struct bnx2x_fp_txdata *txdata,
3287 struct sw_tx_bd *tx_buf,
3288 struct eth_tx_start_bd **tx_bd, u16 hlen,
3289 u16 bd_prod)
3290 {
3291 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
3292 struct eth_tx_bd *d_tx_bd;
3293 dma_addr_t mapping;
3294 int old_len = le16_to_cpu(h_tx_bd->nbytes);
3295
3296 /* first fix first BD */
3297 h_tx_bd->nbytes = cpu_to_le16(hlen);
3298
3299 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x)\n",
3300 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo);
3301
3302 /* now get a new data BD
3303 * (after the pbd) and fill it */
3304 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3305 d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3306
3307 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
3308 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
3309
3310 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3311 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3312 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
3313
3314 /* this marks the BD as one that has no individual mapping */
3315 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
3316
3317 DP(NETIF_MSG_TX_QUEUED,
3318 "TSO split data size is %d (%x:%x)\n",
3319 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
3320
3321 /* update tx_bd */
3322 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
3323
3324 return bd_prod;
3325 }
3326
3327 #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32)))
3328 #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16)))
bnx2x_csum_fix(unsigned char * t_header,u16 csum,s8 fix)3329 static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
3330 {
3331 __sum16 tsum = (__force __sum16) csum;
3332
3333 if (fix > 0)
3334 tsum = ~csum_fold(csum_sub((__force __wsum) csum,
3335 csum_partial(t_header - fix, fix, 0)));
3336
3337 else if (fix < 0)
3338 tsum = ~csum_fold(csum_add((__force __wsum) csum,
3339 csum_partial(t_header, -fix, 0)));
3340
3341 return bswab16(tsum);
3342 }
3343
bnx2x_xmit_type(struct bnx2x * bp,struct sk_buff * skb)3344 static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
3345 {
3346 u32 rc;
3347 __u8 prot = 0;
3348 __be16 protocol;
3349
3350 if (skb->ip_summed != CHECKSUM_PARTIAL)
3351 return XMIT_PLAIN;
3352
3353 protocol = vlan_get_protocol(skb);
3354 if (protocol == htons(ETH_P_IPV6)) {
3355 rc = XMIT_CSUM_V6;
3356 prot = ipv6_hdr(skb)->nexthdr;
3357 } else {
3358 rc = XMIT_CSUM_V4;
3359 prot = ip_hdr(skb)->protocol;
3360 }
3361
3362 if (!CHIP_IS_E1x(bp) && skb->encapsulation) {
3363 if (inner_ip_hdr(skb)->version == 6) {
3364 rc |= XMIT_CSUM_ENC_V6;
3365 if (inner_ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3366 rc |= XMIT_CSUM_TCP;
3367 } else {
3368 rc |= XMIT_CSUM_ENC_V4;
3369 if (inner_ip_hdr(skb)->protocol == IPPROTO_TCP)
3370 rc |= XMIT_CSUM_TCP;
3371 }
3372 }
3373 if (prot == IPPROTO_TCP)
3374 rc |= XMIT_CSUM_TCP;
3375
3376 if (skb_is_gso(skb)) {
3377 if (skb_is_gso_v6(skb)) {
3378 rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP);
3379 if (rc & XMIT_CSUM_ENC)
3380 rc |= XMIT_GSO_ENC_V6;
3381 } else {
3382 rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP);
3383 if (rc & XMIT_CSUM_ENC)
3384 rc |= XMIT_GSO_ENC_V4;
3385 }
3386 }
3387
3388 return rc;
3389 }
3390
3391 /* VXLAN: 4 = 1 (for linear data BD) + 3 (2 for PBD and last BD) */
3392 #define BNX2X_NUM_VXLAN_TSO_WIN_SUB_BDS 4
3393
3394 /* Regular: 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
3395 #define BNX2X_NUM_TSO_WIN_SUB_BDS 3
3396
3397 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT)
3398 /* check if packet requires linearization (packet is too fragmented)
3399 no need to check fragmentation if page size > 8K (there will be no
3400 violation to FW restrictions) */
bnx2x_pkt_req_lin(struct bnx2x * bp,struct sk_buff * skb,u32 xmit_type)3401 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3402 u32 xmit_type)
3403 {
3404 int first_bd_sz = 0, num_tso_win_sub = BNX2X_NUM_TSO_WIN_SUB_BDS;
3405 int to_copy = 0, hlen = 0;
3406
3407 if (xmit_type & XMIT_GSO_ENC)
3408 num_tso_win_sub = BNX2X_NUM_VXLAN_TSO_WIN_SUB_BDS;
3409
3410 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - num_tso_win_sub)) {
3411 if (xmit_type & XMIT_GSO) {
3412 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
3413 int wnd_size = MAX_FETCH_BD - num_tso_win_sub;
3414 /* Number of windows to check */
3415 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
3416 int wnd_idx = 0;
3417 int frag_idx = 0;
3418 u32 wnd_sum = 0;
3419
3420 /* Headers length */
3421 if (xmit_type & XMIT_GSO_ENC)
3422 hlen = skb_inner_tcp_all_headers(skb);
3423 else
3424 hlen = skb_tcp_all_headers(skb);
3425
3426 /* Amount of data (w/o headers) on linear part of SKB*/
3427 first_bd_sz = skb_headlen(skb) - hlen;
3428
3429 wnd_sum = first_bd_sz;
3430
3431 /* Calculate the first sum - it's special */
3432 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
3433 wnd_sum +=
3434 skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]);
3435
3436 /* If there was data on linear skb data - check it */
3437 if (first_bd_sz > 0) {
3438 if (unlikely(wnd_sum < lso_mss)) {
3439 to_copy = 1;
3440 goto exit_lbl;
3441 }
3442
3443 wnd_sum -= first_bd_sz;
3444 }
3445
3446 /* Others are easier: run through the frag list and
3447 check all windows */
3448 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
3449 wnd_sum +=
3450 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]);
3451
3452 if (unlikely(wnd_sum < lso_mss)) {
3453 to_copy = 1;
3454 break;
3455 }
3456 wnd_sum -=
3457 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]);
3458 }
3459 } else {
3460 /* in non-LSO too fragmented packet should always
3461 be linearized */
3462 to_copy = 1;
3463 }
3464 }
3465
3466 exit_lbl:
3467 if (unlikely(to_copy))
3468 DP(NETIF_MSG_TX_QUEUED,
3469 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
3470 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
3471 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
3472
3473 return to_copy;
3474 }
3475 #endif
3476
3477 /**
3478 * bnx2x_set_pbd_gso - update PBD in GSO case.
3479 *
3480 * @skb: packet skb
3481 * @pbd: parse BD
3482 * @xmit_type: xmit flags
3483 */
bnx2x_set_pbd_gso(struct sk_buff * skb,struct eth_tx_parse_bd_e1x * pbd,u32 xmit_type)3484 static void bnx2x_set_pbd_gso(struct sk_buff *skb,
3485 struct eth_tx_parse_bd_e1x *pbd,
3486 u32 xmit_type)
3487 {
3488 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
3489 pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq);
3490 pbd->tcp_flags = pbd_tcp_flags(tcp_hdr(skb));
3491
3492 if (xmit_type & XMIT_GSO_V4) {
3493 pbd->ip_id = bswab16(ip_hdr(skb)->id);
3494 pbd->tcp_pseudo_csum =
3495 bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
3496 ip_hdr(skb)->daddr,
3497 0, IPPROTO_TCP, 0));
3498 } else {
3499 pbd->tcp_pseudo_csum =
3500 bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3501 &ipv6_hdr(skb)->daddr,
3502 0, IPPROTO_TCP, 0));
3503 }
3504
3505 pbd->global_data |=
3506 cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
3507 }
3508
3509 /**
3510 * bnx2x_set_pbd_csum_enc - update PBD with checksum and return header length
3511 *
3512 * @bp: driver handle
3513 * @skb: packet skb
3514 * @parsing_data: data to be updated
3515 * @xmit_type: xmit flags
3516 *
3517 * 57712/578xx related, when skb has encapsulation
3518 */
bnx2x_set_pbd_csum_enc(struct bnx2x * bp,struct sk_buff * skb,u32 * parsing_data,u32 xmit_type)3519 static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
3520 u32 *parsing_data, u32 xmit_type)
3521 {
3522 *parsing_data |=
3523 ((((u8 *)skb_inner_transport_header(skb) - skb->data) >> 1) <<
3524 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
3525 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
3526
3527 if (xmit_type & XMIT_CSUM_TCP) {
3528 *parsing_data |= ((inner_tcp_hdrlen(skb) / 4) <<
3529 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3530 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3531
3532 return skb_inner_tcp_all_headers(skb);
3533 }
3534
3535 /* We support checksum offload for TCP and UDP only.
3536 * No need to pass the UDP header length - it's a constant.
3537 */
3538 return skb_inner_transport_offset(skb) + sizeof(struct udphdr);
3539 }
3540
3541 /**
3542 * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length
3543 *
3544 * @bp: driver handle
3545 * @skb: packet skb
3546 * @parsing_data: data to be updated
3547 * @xmit_type: xmit flags
3548 *
3549 * 57712/578xx related
3550 */
bnx2x_set_pbd_csum_e2(struct bnx2x * bp,struct sk_buff * skb,u32 * parsing_data,u32 xmit_type)3551 static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3552 u32 *parsing_data, u32 xmit_type)
3553 {
3554 *parsing_data |=
3555 ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
3556 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
3557 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
3558
3559 if (xmit_type & XMIT_CSUM_TCP) {
3560 *parsing_data |= ((tcp_hdrlen(skb) / 4) <<
3561 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3562 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3563
3564 return skb_tcp_all_headers(skb);
3565 }
3566 /* We support checksum offload for TCP and UDP only.
3567 * No need to pass the UDP header length - it's a constant.
3568 */
3569 return skb_transport_offset(skb) + sizeof(struct udphdr);
3570 }
3571
3572 /* set FW indication according to inner or outer protocols if tunneled */
bnx2x_set_sbd_csum(struct bnx2x * bp,struct sk_buff * skb,struct eth_tx_start_bd * tx_start_bd,u32 xmit_type)3573 static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3574 struct eth_tx_start_bd *tx_start_bd,
3575 u32 xmit_type)
3576 {
3577 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
3578
3579 if (xmit_type & (XMIT_CSUM_ENC_V6 | XMIT_CSUM_V6))
3580 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
3581
3582 if (!(xmit_type & XMIT_CSUM_TCP))
3583 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP;
3584 }
3585
3586 /**
3587 * bnx2x_set_pbd_csum - update PBD with checksum and return header length
3588 *
3589 * @bp: driver handle
3590 * @skb: packet skb
3591 * @pbd: parse BD to be updated
3592 * @xmit_type: xmit flags
3593 */
bnx2x_set_pbd_csum(struct bnx2x * bp,struct sk_buff * skb,struct eth_tx_parse_bd_e1x * pbd,u32 xmit_type)3594 static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3595 struct eth_tx_parse_bd_e1x *pbd,
3596 u32 xmit_type)
3597 {
3598 u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
3599
3600 /* for now NS flag is not used in Linux */
3601 pbd->global_data =
3602 cpu_to_le16(hlen |
3603 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3604 ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
3605
3606 pbd->ip_hlen_w = (skb_transport_header(skb) -
3607 skb_network_header(skb)) >> 1;
3608
3609 hlen += pbd->ip_hlen_w;
3610
3611 /* We support checksum offload for TCP and UDP only */
3612 if (xmit_type & XMIT_CSUM_TCP)
3613 hlen += tcp_hdrlen(skb) / 2;
3614 else
3615 hlen += sizeof(struct udphdr) / 2;
3616
3617 pbd->total_hlen_w = cpu_to_le16(hlen);
3618 hlen = hlen*2;
3619
3620 if (xmit_type & XMIT_CSUM_TCP) {
3621 pbd->tcp_pseudo_csum = bswab16(tcp_hdr(skb)->check);
3622
3623 } else {
3624 s8 fix = SKB_CS_OFF(skb); /* signed! */
3625
3626 DP(NETIF_MSG_TX_QUEUED,
3627 "hlen %d fix %d csum before fix %x\n",
3628 le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb));
3629
3630 /* HW bug: fixup the CSUM */
3631 pbd->tcp_pseudo_csum =
3632 bnx2x_csum_fix(skb_transport_header(skb),
3633 SKB_CS(skb), fix);
3634
3635 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
3636 pbd->tcp_pseudo_csum);
3637 }
3638
3639 return hlen;
3640 }
3641
bnx2x_update_pbds_gso_enc(struct sk_buff * skb,struct eth_tx_parse_bd_e2 * pbd_e2,struct eth_tx_parse_2nd_bd * pbd2,u16 * global_data,u32 xmit_type)3642 static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
3643 struct eth_tx_parse_bd_e2 *pbd_e2,
3644 struct eth_tx_parse_2nd_bd *pbd2,
3645 u16 *global_data,
3646 u32 xmit_type)
3647 {
3648 u16 hlen_w = 0;
3649 u8 outerip_off, outerip_len = 0;
3650
3651 /* from outer IP to transport */
3652 hlen_w = (skb_inner_transport_header(skb) -
3653 skb_network_header(skb)) >> 1;
3654
3655 /* transport len */
3656 hlen_w += inner_tcp_hdrlen(skb) >> 1;
3657
3658 pbd2->fw_ip_hdr_to_payload_w = hlen_w;
3659
3660 /* outer IP header info */
3661 if (xmit_type & XMIT_CSUM_V4) {
3662 struct iphdr *iph = ip_hdr(skb);
3663 u32 csum = (__force u32)(~iph->check) -
3664 (__force u32)iph->tot_len -
3665 (__force u32)iph->frag_off;
3666
3667 outerip_len = iph->ihl << 1;
3668
3669 pbd2->fw_ip_csum_wo_len_flags_frag =
3670 bswab16(csum_fold((__force __wsum)csum));
3671 } else {
3672 pbd2->fw_ip_hdr_to_payload_w =
3673 hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
3674 pbd_e2->data.tunnel_data.flags |=
3675 ETH_TUNNEL_DATA_IPV6_OUTER;
3676 }
3677
3678 pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
3679
3680 pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb));
3681
3682 /* inner IP header info */
3683 if (xmit_type & XMIT_CSUM_ENC_V4) {
3684 pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id);
3685
3686 pbd_e2->data.tunnel_data.pseudo_csum =
3687 bswab16(~csum_tcpudp_magic(
3688 inner_ip_hdr(skb)->saddr,
3689 inner_ip_hdr(skb)->daddr,
3690 0, IPPROTO_TCP, 0));
3691 } else {
3692 pbd_e2->data.tunnel_data.pseudo_csum =
3693 bswab16(~csum_ipv6_magic(
3694 &inner_ipv6_hdr(skb)->saddr,
3695 &inner_ipv6_hdr(skb)->daddr,
3696 0, IPPROTO_TCP, 0));
3697 }
3698
3699 outerip_off = (skb_network_header(skb) - skb->data) >> 1;
3700
3701 *global_data |=
3702 outerip_off |
3703 (outerip_len <<
3704 ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) |
3705 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3706 ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT);
3707
3708 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
3709 SET_FLAG(*global_data, ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST, 1);
3710 pbd2->tunnel_udp_hdr_start_w = skb_transport_offset(skb) >> 1;
3711 }
3712 }
3713
bnx2x_set_ipv6_ext_e2(struct sk_buff * skb,u32 * parsing_data,u32 xmit_type)3714 static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb, u32 *parsing_data,
3715 u32 xmit_type)
3716 {
3717 struct ipv6hdr *ipv6;
3718
3719 if (!(xmit_type & (XMIT_GSO_ENC_V6 | XMIT_GSO_V6)))
3720 return;
3721
3722 if (xmit_type & XMIT_GSO_ENC_V6)
3723 ipv6 = inner_ipv6_hdr(skb);
3724 else /* XMIT_GSO_V6 */
3725 ipv6 = ipv6_hdr(skb);
3726
3727 if (ipv6->nexthdr == NEXTHDR_IPV6)
3728 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
3729 }
3730
3731 /* called with netif_tx_lock
3732 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
3733 * netif_wake_queue()
3734 */
bnx2x_start_xmit(struct sk_buff * skb,struct net_device * dev)3735 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3736 {
3737 struct bnx2x *bp = netdev_priv(dev);
3738
3739 struct netdev_queue *txq;
3740 struct bnx2x_fp_txdata *txdata;
3741 struct sw_tx_bd *tx_buf;
3742 struct eth_tx_start_bd *tx_start_bd, *first_bd;
3743 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
3744 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
3745 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
3746 struct eth_tx_parse_2nd_bd *pbd2 = NULL;
3747 u32 pbd_e2_parsing_data = 0;
3748 u16 pkt_prod, bd_prod;
3749 int nbd, txq_index;
3750 dma_addr_t mapping;
3751 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3752 int i;
3753 u8 hlen = 0;
3754 __le16 pkt_size = 0;
3755 struct ethhdr *eth;
3756 u8 mac_type = UNICAST_ADDRESS;
3757
3758 #ifdef BNX2X_STOP_ON_ERROR
3759 if (unlikely(bp->panic))
3760 return NETDEV_TX_BUSY;
3761 #endif
3762
3763 txq_index = skb_get_queue_mapping(skb);
3764 txq = netdev_get_tx_queue(dev, txq_index);
3765
3766 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
3767
3768 txdata = &bp->bnx2x_txq[txq_index];
3769
3770 /* enable this debug print to view the transmission queue being used
3771 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
3772 txq_index, fp_index, txdata_index); */
3773
3774 /* enable this debug print to view the transmission details
3775 DP(NETIF_MSG_TX_QUEUED,
3776 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
3777 txdata->cid, fp_index, txdata_index, txdata, fp); */
3778
3779 if (unlikely(bnx2x_tx_avail(bp, txdata) <
3780 skb_shinfo(skb)->nr_frags +
3781 BDS_PER_TX_PKT +
3782 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) {
3783 /* Handle special storage cases separately */
3784 if (txdata->tx_ring_size == 0) {
3785 struct bnx2x_eth_q_stats *q_stats =
3786 bnx2x_fp_qstats(bp, txdata->parent_fp);
3787 q_stats->driver_filtered_tx_pkt++;
3788 dev_kfree_skb(skb);
3789 return NETDEV_TX_OK;
3790 }
3791 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3792 netif_tx_stop_queue(txq);
3793 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
3794
3795 return NETDEV_TX_BUSY;
3796 }
3797
3798 DP(NETIF_MSG_TX_QUEUED,
3799 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x len %d\n",
3800 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
3801 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type,
3802 skb->len);
3803
3804 eth = (struct ethhdr *)skb->data;
3805
3806 /* set flag according to packet type (UNICAST_ADDRESS is default)*/
3807 if (unlikely(is_multicast_ether_addr(eth->h_dest))) {
3808 if (is_broadcast_ether_addr(eth->h_dest))
3809 mac_type = BROADCAST_ADDRESS;
3810 else
3811 mac_type = MULTICAST_ADDRESS;
3812 }
3813
3814 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT)
3815 /* First, check if we need to linearize the skb (due to FW
3816 restrictions). No need to check fragmentation if page size > 8K
3817 (there will be no violation to FW restrictions) */
3818 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3819 /* Statistics of linearization */
3820 bp->lin_cnt++;
3821 if (skb_linearize(skb) != 0) {
3822 DP(NETIF_MSG_TX_QUEUED,
3823 "SKB linearization failed - silently dropping this SKB\n");
3824 dev_kfree_skb_any(skb);
3825 return NETDEV_TX_OK;
3826 }
3827 }
3828 #endif
3829 /* Map skb linear data for DMA */
3830 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3831 skb_headlen(skb), DMA_TO_DEVICE);
3832 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3833 DP(NETIF_MSG_TX_QUEUED,
3834 "SKB mapping failed - silently dropping this SKB\n");
3835 dev_kfree_skb_any(skb);
3836 return NETDEV_TX_OK;
3837 }
3838 /*
3839 Please read carefully. First we use one BD which we mark as start,
3840 then we have a parsing info BD (used for TSO or xsum),
3841 and only then we have the rest of the TSO BDs.
3842 (don't forget to mark the last one as last,
3843 and to unmap only AFTER you write to the BD ...)
3844 And above all, all pdb sizes are in words - NOT DWORDS!
3845 */
3846
3847 /* get current pkt produced now - advance it just before sending packet
3848 * since mapping of pages may fail and cause packet to be dropped
3849 */
3850 pkt_prod = txdata->tx_pkt_prod;
3851 bd_prod = TX_BD(txdata->tx_bd_prod);
3852
3853 /* get a tx_buf and first BD
3854 * tx_start_bd may be changed during SPLIT,
3855 * but first_bd will always stay first
3856 */
3857 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
3858 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
3859 first_bd = tx_start_bd;
3860
3861 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3862
3863 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
3864 if (!(bp->flags & TX_TIMESTAMPING_EN)) {
3865 bp->eth_stats.ptp_skip_tx_ts++;
3866 BNX2X_ERR("Tx timestamping was not enabled, this packet will not be timestamped\n");
3867 } else if (bp->ptp_tx_skb) {
3868 bp->eth_stats.ptp_skip_tx_ts++;
3869 netdev_err_once(bp->dev,
3870 "Device supports only a single outstanding packet to timestamp, this packet won't be timestamped\n");
3871 } else {
3872 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3873 /* schedule check for Tx timestamp */
3874 bp->ptp_tx_skb = skb_get(skb);
3875 bp->ptp_tx_start = jiffies;
3876 schedule_work(&bp->ptp_task);
3877 }
3878 }
3879
3880 /* header nbd: indirectly zero other flags! */
3881 tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT;
3882
3883 /* remember the first BD of the packet */
3884 tx_buf->first_bd = txdata->tx_bd_prod;
3885 tx_buf->skb = skb;
3886 tx_buf->flags = 0;
3887
3888 DP(NETIF_MSG_TX_QUEUED,
3889 "sending pkt %u @%p next_idx %u bd %u @%p\n",
3890 pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd);
3891
3892 if (skb_vlan_tag_present(skb)) {
3893 tx_start_bd->vlan_or_ethertype =
3894 cpu_to_le16(skb_vlan_tag_get(skb));
3895 tx_start_bd->bd_flags.as_bitfield |=
3896 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
3897 } else {
3898 /* when transmitting in a vf, start bd must hold the ethertype
3899 * for fw to enforce it
3900 */
3901 u16 vlan_tci = 0;
3902 #ifndef BNX2X_STOP_ON_ERROR
3903 if (IS_VF(bp)) {
3904 #endif
3905 /* Still need to consider inband vlan for enforced */
3906 if (__vlan_get_tag(skb, &vlan_tci)) {
3907 tx_start_bd->vlan_or_ethertype =
3908 cpu_to_le16(ntohs(eth->h_proto));
3909 } else {
3910 tx_start_bd->bd_flags.as_bitfield |=
3911 (X_ETH_INBAND_VLAN <<
3912 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
3913 tx_start_bd->vlan_or_ethertype =
3914 cpu_to_le16(vlan_tci);
3915 }
3916 #ifndef BNX2X_STOP_ON_ERROR
3917 } else {
3918 /* used by FW for packet accounting */
3919 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
3920 }
3921 #endif
3922 }
3923
3924 nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
3925
3926 /* turn on parsing and get a BD */
3927 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3928
3929 if (xmit_type & XMIT_CSUM)
3930 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
3931
3932 if (!CHIP_IS_E1x(bp)) {
3933 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
3934 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
3935
3936 if (xmit_type & XMIT_CSUM_ENC) {
3937 u16 global_data = 0;
3938
3939 /* Set PBD in enc checksum offload case */
3940 hlen = bnx2x_set_pbd_csum_enc(bp, skb,
3941 &pbd_e2_parsing_data,
3942 xmit_type);
3943
3944 /* turn on 2nd parsing and get a BD */
3945 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3946
3947 pbd2 = &txdata->tx_desc_ring[bd_prod].parse_2nd_bd;
3948
3949 memset(pbd2, 0, sizeof(*pbd2));
3950
3951 pbd_e2->data.tunnel_data.ip_hdr_start_inner_w =
3952 (skb_inner_network_header(skb) -
3953 skb->data) >> 1;
3954
3955 if (xmit_type & XMIT_GSO_ENC)
3956 bnx2x_update_pbds_gso_enc(skb, pbd_e2, pbd2,
3957 &global_data,
3958 xmit_type);
3959
3960 pbd2->global_data = cpu_to_le16(global_data);
3961
3962 /* add addition parse BD indication to start BD */
3963 SET_FLAG(tx_start_bd->general_data,
3964 ETH_TX_START_BD_PARSE_NBDS, 1);
3965 /* set encapsulation flag in start BD */
3966 SET_FLAG(tx_start_bd->general_data,
3967 ETH_TX_START_BD_TUNNEL_EXIST, 1);
3968
3969 tx_buf->flags |= BNX2X_HAS_SECOND_PBD;
3970
3971 nbd++;
3972 } else if (xmit_type & XMIT_CSUM) {
3973 /* Set PBD in checksum offload case w/o encapsulation */
3974 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3975 &pbd_e2_parsing_data,
3976 xmit_type);
3977 }
3978
3979 bnx2x_set_ipv6_ext_e2(skb, &pbd_e2_parsing_data, xmit_type);
3980 /* Add the macs to the parsing BD if this is a vf or if
3981 * Tx Switching is enabled.
3982 */
3983 if (IS_VF(bp)) {
3984 /* override GRE parameters in BD */
3985 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
3986 &pbd_e2->data.mac_addr.src_mid,
3987 &pbd_e2->data.mac_addr.src_lo,
3988 eth->h_source);
3989
3990 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
3991 &pbd_e2->data.mac_addr.dst_mid,
3992 &pbd_e2->data.mac_addr.dst_lo,
3993 eth->h_dest);
3994 } else {
3995 if (bp->flags & TX_SWITCHING)
3996 bnx2x_set_fw_mac_addr(
3997 &pbd_e2->data.mac_addr.dst_hi,
3998 &pbd_e2->data.mac_addr.dst_mid,
3999 &pbd_e2->data.mac_addr.dst_lo,
4000 eth->h_dest);
4001 #ifdef BNX2X_STOP_ON_ERROR
4002 /* Enforce security is always set in Stop on Error -
4003 * source mac should be present in the parsing BD
4004 */
4005 bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
4006 &pbd_e2->data.mac_addr.src_mid,
4007 &pbd_e2->data.mac_addr.src_lo,
4008 eth->h_source);
4009 #endif
4010 }
4011
4012 SET_FLAG(pbd_e2_parsing_data,
4013 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
4014 } else {
4015 u16 global_data = 0;
4016 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
4017 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
4018 /* Set PBD in checksum offload case */
4019 if (xmit_type & XMIT_CSUM)
4020 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
4021
4022 SET_FLAG(global_data,
4023 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
4024 pbd_e1x->global_data |= cpu_to_le16(global_data);
4025 }
4026
4027 /* Setup the data pointer of the first BD of the packet */
4028 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
4029 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
4030 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
4031 pkt_size = tx_start_bd->nbytes;
4032
4033 DP(NETIF_MSG_TX_QUEUED,
4034 "first bd @%p addr (%x:%x) nbytes %d flags %x vlan %x\n",
4035 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
4036 le16_to_cpu(tx_start_bd->nbytes),
4037 tx_start_bd->bd_flags.as_bitfield,
4038 le16_to_cpu(tx_start_bd->vlan_or_ethertype));
4039
4040 if (xmit_type & XMIT_GSO) {
4041
4042 DP(NETIF_MSG_TX_QUEUED,
4043 "TSO packet len %d hlen %d total len %d tso size %d\n",
4044 skb->len, hlen, skb_headlen(skb),
4045 skb_shinfo(skb)->gso_size);
4046
4047 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
4048
4049 if (unlikely(skb_headlen(skb) > hlen)) {
4050 nbd++;
4051 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
4052 &tx_start_bd, hlen,
4053 bd_prod);
4054 }
4055 if (!CHIP_IS_E1x(bp))
4056 pbd_e2_parsing_data |=
4057 (skb_shinfo(skb)->gso_size <<
4058 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
4059 ETH_TX_PARSE_BD_E2_LSO_MSS;
4060 else
4061 bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
4062 }
4063
4064 /* Set the PBD's parsing_data field if not zero
4065 * (for the chips newer than 57711).
4066 */
4067 if (pbd_e2_parsing_data)
4068 pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data);
4069
4070 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
4071
4072 /* Handle fragmented skb */
4073 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4074 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4075
4076 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
4077 skb_frag_size(frag), DMA_TO_DEVICE);
4078 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
4079 unsigned int pkts_compl = 0, bytes_compl = 0;
4080
4081 DP(NETIF_MSG_TX_QUEUED,
4082 "Unable to map page - dropping packet...\n");
4083
4084 /* we need unmap all buffers already mapped
4085 * for this SKB;
4086 * first_bd->nbd need to be properly updated
4087 * before call to bnx2x_free_tx_pkt
4088 */
4089 first_bd->nbd = cpu_to_le16(nbd);
4090 bnx2x_free_tx_pkt(bp, txdata,
4091 TX_BD(txdata->tx_pkt_prod),
4092 &pkts_compl, &bytes_compl);
4093 return NETDEV_TX_OK;
4094 }
4095
4096 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
4097 tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
4098 if (total_pkt_bd == NULL)
4099 total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
4100
4101 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
4102 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
4103 tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag));
4104 le16_add_cpu(&pkt_size, skb_frag_size(frag));
4105 nbd++;
4106
4107 DP(NETIF_MSG_TX_QUEUED,
4108 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
4109 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
4110 le16_to_cpu(tx_data_bd->nbytes));
4111 }
4112
4113 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
4114
4115 /* update with actual num BDs */
4116 first_bd->nbd = cpu_to_le16(nbd);
4117
4118 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
4119
4120 /* now send a tx doorbell, counting the next BD
4121 * if the packet contains or ends with it
4122 */
4123 if (TX_BD_POFF(bd_prod) < nbd)
4124 nbd++;
4125
4126 /* total_pkt_bytes should be set on the first data BD if
4127 * it's not an LSO packet and there is more than one
4128 * data BD. In this case pkt_size is limited by an MTU value.
4129 * However we prefer to set it for an LSO packet (while we don't
4130 * have to) in order to save some CPU cycles in a none-LSO
4131 * case, when we much more care about them.
4132 */
4133 if (total_pkt_bd != NULL)
4134 total_pkt_bd->total_pkt_bytes = pkt_size;
4135
4136 if (pbd_e1x)
4137 DP(NETIF_MSG_TX_QUEUED,
4138 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
4139 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
4140 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
4141 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
4142 le16_to_cpu(pbd_e1x->total_hlen_w));
4143 if (pbd_e2)
4144 DP(NETIF_MSG_TX_QUEUED,
4145 "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n",
4146 pbd_e2,
4147 pbd_e2->data.mac_addr.dst_hi,
4148 pbd_e2->data.mac_addr.dst_mid,
4149 pbd_e2->data.mac_addr.dst_lo,
4150 pbd_e2->data.mac_addr.src_hi,
4151 pbd_e2->data.mac_addr.src_mid,
4152 pbd_e2->data.mac_addr.src_lo,
4153 pbd_e2->parsing_data);
4154 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
4155
4156 netdev_tx_sent_queue(txq, skb->len);
4157
4158 skb_tx_timestamp(skb);
4159
4160 txdata->tx_pkt_prod++;
4161 /*
4162 * Make sure that the BD data is updated before updating the producer
4163 * since FW might read the BD right after the producer is updated.
4164 * This is only applicable for weak-ordered memory model archs such
4165 * as IA-64. The following barrier is also mandatory since FW will
4166 * assumes packets must have BDs.
4167 */
4168 wmb();
4169
4170 txdata->tx_db.data.prod += nbd;
4171 /* make sure descriptor update is observed by HW */
4172 wmb();
4173
4174 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
4175
4176 txdata->tx_bd_prod += nbd;
4177
4178 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
4179 netif_tx_stop_queue(txq);
4180
4181 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
4182 * ordering of set_bit() in netif_tx_stop_queue() and read of
4183 * fp->bd_tx_cons */
4184 smp_mb();
4185
4186 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
4187 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
4188 netif_tx_wake_queue(txq);
4189 }
4190 txdata->tx_pkt++;
4191
4192 return NETDEV_TX_OK;
4193 }
4194
bnx2x_get_c2s_mapping(struct bnx2x * bp,u8 * c2s_map,u8 * c2s_default)4195 void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default)
4196 {
4197 int mfw_vn = BP_FW_MB_IDX(bp);
4198 u32 tmp;
4199
4200 /* If the shmem shouldn't affect configuration, reflect */
4201 if (!IS_MF_BD(bp)) {
4202 int i;
4203
4204 for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
4205 c2s_map[i] = i;
4206 *c2s_default = 0;
4207
4208 return;
4209 }
4210
4211 tmp = SHMEM2_RD(bp, c2s_pcp_map_lower[mfw_vn]);
4212 tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
4213 c2s_map[0] = tmp & 0xff;
4214 c2s_map[1] = (tmp >> 8) & 0xff;
4215 c2s_map[2] = (tmp >> 16) & 0xff;
4216 c2s_map[3] = (tmp >> 24) & 0xff;
4217
4218 tmp = SHMEM2_RD(bp, c2s_pcp_map_upper[mfw_vn]);
4219 tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
4220 c2s_map[4] = tmp & 0xff;
4221 c2s_map[5] = (tmp >> 8) & 0xff;
4222 c2s_map[6] = (tmp >> 16) & 0xff;
4223 c2s_map[7] = (tmp >> 24) & 0xff;
4224
4225 tmp = SHMEM2_RD(bp, c2s_pcp_map_default[mfw_vn]);
4226 tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
4227 *c2s_default = (tmp >> (8 * mfw_vn)) & 0xff;
4228 }
4229
4230 /**
4231 * bnx2x_setup_tc - routine to configure net_device for multi tc
4232 *
4233 * @dev: net device to configure
4234 * @num_tc: number of traffic classes to enable
4235 *
4236 * callback connected to the ndo_setup_tc function pointer
4237 */
bnx2x_setup_tc(struct net_device * dev,u8 num_tc)4238 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
4239 {
4240 struct bnx2x *bp = netdev_priv(dev);
4241 u8 c2s_map[BNX2X_MAX_PRIORITY], c2s_def;
4242 int cos, prio, count, offset;
4243
4244 /* setup tc must be called under rtnl lock */
4245 ASSERT_RTNL();
4246
4247 /* no traffic classes requested. Aborting */
4248 if (!num_tc) {
4249 netdev_reset_tc(dev);
4250 return 0;
4251 }
4252
4253 /* requested to support too many traffic classes */
4254 if (num_tc > bp->max_cos) {
4255 BNX2X_ERR("support for too many traffic classes requested: %d. Max supported is %d\n",
4256 num_tc, bp->max_cos);
4257 return -EINVAL;
4258 }
4259
4260 /* declare amount of supported traffic classes */
4261 if (netdev_set_num_tc(dev, num_tc)) {
4262 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
4263 return -EINVAL;
4264 }
4265
4266 bnx2x_get_c2s_mapping(bp, c2s_map, &c2s_def);
4267
4268 /* configure priority to traffic class mapping */
4269 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
4270 int outer_prio = c2s_map[prio];
4271
4272 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[outer_prio]);
4273 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4274 "mapping priority %d to tc %d\n",
4275 outer_prio, bp->prio_to_cos[outer_prio]);
4276 }
4277
4278 /* Use this configuration to differentiate tc0 from other COSes
4279 This can be used for ets or pfc, and save the effort of setting
4280 up a multio class queue disc or negotiating DCBX with a switch
4281 netdev_set_prio_tc_map(dev, 0, 0);
4282 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0);
4283 for (prio = 1; prio < 16; prio++) {
4284 netdev_set_prio_tc_map(dev, prio, 1);
4285 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1);
4286 } */
4287
4288 /* configure traffic class to transmission queue mapping */
4289 for (cos = 0; cos < bp->max_cos; cos++) {
4290 count = BNX2X_NUM_ETH_QUEUES(bp);
4291 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
4292 netdev_set_tc_queue(dev, cos, count, offset);
4293 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4294 "mapping tc %d to offset %d count %d\n",
4295 cos, offset, count);
4296 }
4297
4298 return 0;
4299 }
4300
__bnx2x_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)4301 int __bnx2x_setup_tc(struct net_device *dev, enum tc_setup_type type,
4302 void *type_data)
4303 {
4304 struct tc_mqprio_qopt *mqprio = type_data;
4305
4306 if (type != TC_SETUP_QDISC_MQPRIO)
4307 return -EOPNOTSUPP;
4308
4309 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
4310
4311 return bnx2x_setup_tc(dev, mqprio->num_tc);
4312 }
4313
4314 /* called with rtnl_lock */
bnx2x_change_mac_addr(struct net_device * dev,void * p)4315 int bnx2x_change_mac_addr(struct net_device *dev, void *p)
4316 {
4317 struct sockaddr *addr = p;
4318 struct bnx2x *bp = netdev_priv(dev);
4319 int rc = 0;
4320
4321 if (!is_valid_ether_addr(addr->sa_data)) {
4322 BNX2X_ERR("Requested MAC address is not valid\n");
4323 return -EINVAL;
4324 }
4325
4326 if (IS_MF_STORAGE_ONLY(bp)) {
4327 BNX2X_ERR("Can't change address on STORAGE ONLY function\n");
4328 return -EINVAL;
4329 }
4330
4331 if (netif_running(dev)) {
4332 rc = bnx2x_set_eth_mac(bp, false);
4333 if (rc)
4334 return rc;
4335 }
4336
4337 eth_hw_addr_set(dev, addr->sa_data);
4338
4339 if (netif_running(dev))
4340 rc = bnx2x_set_eth_mac(bp, true);
4341
4342 if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
4343 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
4344
4345 return rc;
4346 }
4347
bnx2x_free_fp_mem_at(struct bnx2x * bp,int fp_index)4348 static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
4349 {
4350 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
4351 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
4352 u8 cos;
4353
4354 /* Common */
4355
4356 if (IS_FCOE_IDX(fp_index)) {
4357 memset(sb, 0, sizeof(union host_hc_status_block));
4358 fp->status_blk_mapping = 0;
4359 } else {
4360 /* status blocks */
4361 if (!CHIP_IS_E1x(bp))
4362 BNX2X_PCI_FREE(sb->e2_sb,
4363 bnx2x_fp(bp, fp_index,
4364 status_blk_mapping),
4365 sizeof(struct host_hc_status_block_e2));
4366 else
4367 BNX2X_PCI_FREE(sb->e1x_sb,
4368 bnx2x_fp(bp, fp_index,
4369 status_blk_mapping),
4370 sizeof(struct host_hc_status_block_e1x));
4371 }
4372
4373 /* Rx */
4374 if (!skip_rx_queue(bp, fp_index)) {
4375 bnx2x_free_rx_bds(fp);
4376
4377 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4378 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
4379 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
4380 bnx2x_fp(bp, fp_index, rx_desc_mapping),
4381 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4382
4383 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
4384 bnx2x_fp(bp, fp_index, rx_comp_mapping),
4385 sizeof(struct eth_fast_path_rx_cqe) *
4386 NUM_RCQ_BD);
4387
4388 /* SGE ring */
4389 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
4390 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
4391 bnx2x_fp(bp, fp_index, rx_sge_mapping),
4392 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4393 }
4394
4395 /* Tx */
4396 if (!skip_tx_queue(bp, fp_index)) {
4397 /* fastpath tx rings: tx_buf tx_desc */
4398 for_each_cos_in_tx_queue(fp, cos) {
4399 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
4400
4401 DP(NETIF_MSG_IFDOWN,
4402 "freeing tx memory of fp %d cos %d cid %d\n",
4403 fp_index, cos, txdata->cid);
4404
4405 BNX2X_FREE(txdata->tx_buf_ring);
4406 BNX2X_PCI_FREE(txdata->tx_desc_ring,
4407 txdata->tx_desc_mapping,
4408 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4409 }
4410 }
4411 /* end of fastpath */
4412 }
4413
bnx2x_free_fp_mem_cnic(struct bnx2x * bp)4414 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
4415 {
4416 int i;
4417 for_each_cnic_queue(bp, i)
4418 bnx2x_free_fp_mem_at(bp, i);
4419 }
4420
bnx2x_free_fp_mem(struct bnx2x * bp)4421 void bnx2x_free_fp_mem(struct bnx2x *bp)
4422 {
4423 int i;
4424 for_each_eth_queue(bp, i)
4425 bnx2x_free_fp_mem_at(bp, i);
4426 }
4427
set_sb_shortcuts(struct bnx2x * bp,int index)4428 static void set_sb_shortcuts(struct bnx2x *bp, int index)
4429 {
4430 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
4431 if (!CHIP_IS_E1x(bp)) {
4432 bnx2x_fp(bp, index, sb_index_values) =
4433 (__le16 *)status_blk.e2_sb->sb.index_values;
4434 bnx2x_fp(bp, index, sb_running_index) =
4435 (__le16 *)status_blk.e2_sb->sb.running_index;
4436 } else {
4437 bnx2x_fp(bp, index, sb_index_values) =
4438 (__le16 *)status_blk.e1x_sb->sb.index_values;
4439 bnx2x_fp(bp, index, sb_running_index) =
4440 (__le16 *)status_blk.e1x_sb->sb.running_index;
4441 }
4442 }
4443
4444 /* Returns the number of actually allocated BDs */
bnx2x_alloc_rx_bds(struct bnx2x_fastpath * fp,int rx_ring_size)4445 static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
4446 int rx_ring_size)
4447 {
4448 struct bnx2x *bp = fp->bp;
4449 u16 ring_prod, cqe_ring_prod;
4450 int i, failure_cnt = 0;
4451
4452 fp->rx_comp_cons = 0;
4453 cqe_ring_prod = ring_prod = 0;
4454
4455 /* This routine is called only during fo init so
4456 * fp->eth_q_stats.rx_skb_alloc_failed = 0
4457 */
4458 for (i = 0; i < rx_ring_size; i++) {
4459 if (bnx2x_alloc_rx_data(bp, fp, ring_prod, GFP_KERNEL) < 0) {
4460 failure_cnt++;
4461 continue;
4462 }
4463 ring_prod = NEXT_RX_IDX(ring_prod);
4464 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4465 WARN_ON(ring_prod <= (i - failure_cnt));
4466 }
4467
4468 if (failure_cnt)
4469 BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
4470 i - failure_cnt, fp->index);
4471
4472 fp->rx_bd_prod = ring_prod;
4473 /* Limit the CQE producer by the CQE ring size */
4474 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
4475 cqe_ring_prod);
4476
4477 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
4478
4479 return i - failure_cnt;
4480 }
4481
bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath * fp)4482 static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
4483 {
4484 int i;
4485
4486 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4487 struct eth_rx_cqe_next_page *nextpg;
4488
4489 nextpg = (struct eth_rx_cqe_next_page *)
4490 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4491 nextpg->addr_hi =
4492 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4493 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4494 nextpg->addr_lo =
4495 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4496 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4497 }
4498 }
4499
bnx2x_alloc_fp_mem_at(struct bnx2x * bp,int index)4500 static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
4501 {
4502 union host_hc_status_block *sb;
4503 struct bnx2x_fastpath *fp = &bp->fp[index];
4504 int ring_size = 0;
4505 u8 cos;
4506 int rx_ring_size = 0;
4507
4508 if (!bp->rx_ring_size && IS_MF_STORAGE_ONLY(bp)) {
4509 rx_ring_size = MIN_RX_SIZE_NONTPA;
4510 bp->rx_ring_size = rx_ring_size;
4511 } else if (!bp->rx_ring_size) {
4512 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
4513
4514 if (CHIP_IS_E3(bp)) {
4515 u32 cfg = SHMEM_RD(bp,
4516 dev_info.port_hw_config[BP_PORT(bp)].
4517 default_cfg);
4518
4519 /* Decrease ring size for 1G functions */
4520 if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
4521 PORT_HW_CFG_NET_SERDES_IF_SGMII)
4522 rx_ring_size /= 10;
4523 }
4524
4525 /* allocate at least number of buffers required by FW */
4526 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4527 MIN_RX_SIZE_TPA, rx_ring_size);
4528
4529 bp->rx_ring_size = rx_ring_size;
4530 } else /* if rx_ring_size specified - use it */
4531 rx_ring_size = bp->rx_ring_size;
4532
4533 DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size);
4534
4535 /* Common */
4536 sb = &bnx2x_fp(bp, index, status_blk);
4537
4538 if (!IS_FCOE_IDX(index)) {
4539 /* status blocks */
4540 if (!CHIP_IS_E1x(bp)) {
4541 sb->e2_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4542 sizeof(struct host_hc_status_block_e2));
4543 if (!sb->e2_sb)
4544 goto alloc_mem_err;
4545 } else {
4546 sb->e1x_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4547 sizeof(struct host_hc_status_block_e1x));
4548 if (!sb->e1x_sb)
4549 goto alloc_mem_err;
4550 }
4551 }
4552
4553 /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to
4554 * set shortcuts for it.
4555 */
4556 if (!IS_FCOE_IDX(index))
4557 set_sb_shortcuts(bp, index);
4558
4559 /* Tx */
4560 if (!skip_tx_queue(bp, index)) {
4561 /* fastpath tx rings: tx_buf tx_desc */
4562 for_each_cos_in_tx_queue(fp, cos) {
4563 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
4564
4565 DP(NETIF_MSG_IFUP,
4566 "allocating tx memory of fp %d cos %d\n",
4567 index, cos);
4568
4569 txdata->tx_buf_ring = kcalloc(NUM_TX_BD,
4570 sizeof(struct sw_tx_bd),
4571 GFP_KERNEL);
4572 if (!txdata->tx_buf_ring)
4573 goto alloc_mem_err;
4574 txdata->tx_desc_ring = BNX2X_PCI_ALLOC(&txdata->tx_desc_mapping,
4575 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4576 if (!txdata->tx_desc_ring)
4577 goto alloc_mem_err;
4578 }
4579 }
4580
4581 /* Rx */
4582 if (!skip_rx_queue(bp, index)) {
4583 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4584 bnx2x_fp(bp, index, rx_buf_ring) =
4585 kcalloc(NUM_RX_BD, sizeof(struct sw_rx_bd), GFP_KERNEL);
4586 if (!bnx2x_fp(bp, index, rx_buf_ring))
4587 goto alloc_mem_err;
4588 bnx2x_fp(bp, index, rx_desc_ring) =
4589 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_desc_mapping),
4590 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4591 if (!bnx2x_fp(bp, index, rx_desc_ring))
4592 goto alloc_mem_err;
4593
4594 /* Seed all CQEs by 1s */
4595 bnx2x_fp(bp, index, rx_comp_ring) =
4596 BNX2X_PCI_FALLOC(&bnx2x_fp(bp, index, rx_comp_mapping),
4597 sizeof(struct eth_fast_path_rx_cqe) * NUM_RCQ_BD);
4598 if (!bnx2x_fp(bp, index, rx_comp_ring))
4599 goto alloc_mem_err;
4600
4601 /* SGE ring */
4602 bnx2x_fp(bp, index, rx_page_ring) =
4603 kcalloc(NUM_RX_SGE, sizeof(struct sw_rx_page),
4604 GFP_KERNEL);
4605 if (!bnx2x_fp(bp, index, rx_page_ring))
4606 goto alloc_mem_err;
4607 bnx2x_fp(bp, index, rx_sge_ring) =
4608 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_sge_mapping),
4609 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4610 if (!bnx2x_fp(bp, index, rx_sge_ring))
4611 goto alloc_mem_err;
4612 /* RX BD ring */
4613 bnx2x_set_next_page_rx_bd(fp);
4614
4615 /* CQ ring */
4616 bnx2x_set_next_page_rx_cq(fp);
4617
4618 /* BDs */
4619 ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size);
4620 if (ring_size < rx_ring_size)
4621 goto alloc_mem_err;
4622 }
4623
4624 return 0;
4625
4626 /* handles low memory cases */
4627 alloc_mem_err:
4628 BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n",
4629 index, ring_size);
4630 /* FW will drop all packets if queue is not big enough,
4631 * In these cases we disable the queue
4632 * Min size is different for OOO, TPA and non-TPA queues
4633 */
4634 if (ring_size < (fp->mode == TPA_MODE_DISABLED ?
4635 MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) {
4636 /* release memory allocated for this queue */
4637 bnx2x_free_fp_mem_at(bp, index);
4638 return -ENOMEM;
4639 }
4640 return 0;
4641 }
4642
bnx2x_alloc_fp_mem_cnic(struct bnx2x * bp)4643 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
4644 {
4645 if (!NO_FCOE(bp))
4646 /* FCoE */
4647 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4648 /* we will fail load process instead of mark
4649 * NO_FCOE_FLAG
4650 */
4651 return -ENOMEM;
4652
4653 return 0;
4654 }
4655
bnx2x_alloc_fp_mem(struct bnx2x * bp)4656 static int bnx2x_alloc_fp_mem(struct bnx2x *bp)
4657 {
4658 int i;
4659
4660 /* 1. Allocate FP for leading - fatal if error
4661 * 2. Allocate RSS - fix number of queues if error
4662 */
4663
4664 /* leading */
4665 if (bnx2x_alloc_fp_mem_at(bp, 0))
4666 return -ENOMEM;
4667
4668 /* RSS */
4669 for_each_nondefault_eth_queue(bp, i)
4670 if (bnx2x_alloc_fp_mem_at(bp, i))
4671 break;
4672
4673 /* handle memory failures */
4674 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4675 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4676
4677 WARN_ON(delta < 0);
4678 bnx2x_shrink_eth_fp(bp, delta);
4679 if (CNIC_SUPPORT(bp))
4680 /* move non eth FPs next to last eth FP
4681 * must be done in that order
4682 * FCOE_IDX < FWD_IDX < OOO_IDX
4683 */
4684
4685 /* move FCoE fp even NO_FCOE_FLAG is on */
4686 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4687 bp->num_ethernet_queues -= delta;
4688 bp->num_queues = bp->num_ethernet_queues +
4689 bp->num_cnic_queues;
4690 BNX2X_ERR("Adjusted num of queues from %d to %d\n",
4691 bp->num_queues + delta, bp->num_queues);
4692 }
4693
4694 return 0;
4695 }
4696
bnx2x_free_mem_bp(struct bnx2x * bp)4697 void bnx2x_free_mem_bp(struct bnx2x *bp)
4698 {
4699 int i;
4700
4701 for (i = 0; i < bp->fp_array_size; i++)
4702 kfree(bp->fp[i].tpa_info);
4703 kfree(bp->fp);
4704 kfree(bp->sp_objs);
4705 kfree(bp->fp_stats);
4706 kfree(bp->bnx2x_txq);
4707 kfree(bp->msix_table);
4708 kfree(bp->ilt);
4709 }
4710
bnx2x_alloc_mem_bp(struct bnx2x * bp)4711 int bnx2x_alloc_mem_bp(struct bnx2x *bp)
4712 {
4713 struct bnx2x_fastpath *fp;
4714 struct msix_entry *tbl;
4715 struct bnx2x_ilt *ilt;
4716 int msix_table_size = 0;
4717 int fp_array_size, txq_array_size;
4718 int i;
4719
4720 /*
4721 * The biggest MSI-X table we might need is as a maximum number of fast
4722 * path IGU SBs plus default SB (for PF only).
4723 */
4724 msix_table_size = bp->igu_sb_cnt;
4725 if (IS_PF(bp))
4726 msix_table_size++;
4727 BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size);
4728
4729 /* fp array: RSS plus CNIC related L2 queues */
4730 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
4731 bp->fp_array_size = fp_array_size;
4732 BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size);
4733
4734 fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL);
4735 if (!fp)
4736 goto alloc_err;
4737 for (i = 0; i < bp->fp_array_size; i++) {
4738 fp[i].tpa_info =
4739 kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2,
4740 sizeof(struct bnx2x_agg_info), GFP_KERNEL);
4741 if (!(fp[i].tpa_info))
4742 goto alloc_err;
4743 }
4744
4745 bp->fp = fp;
4746
4747 /* allocate sp objs */
4748 bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs),
4749 GFP_KERNEL);
4750 if (!bp->sp_objs)
4751 goto alloc_err;
4752
4753 /* allocate fp_stats */
4754 bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats),
4755 GFP_KERNEL);
4756 if (!bp->fp_stats)
4757 goto alloc_err;
4758
4759 /* Allocate memory for the transmission queues array */
4760 txq_array_size =
4761 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4762 BNX2X_DEV_INFO("txq_array_size %d", txq_array_size);
4763
4764 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4765 GFP_KERNEL);
4766 if (!bp->bnx2x_txq)
4767 goto alloc_err;
4768
4769 /* msix table */
4770 tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL);
4771 if (!tbl)
4772 goto alloc_err;
4773 bp->msix_table = tbl;
4774
4775 /* ilt */
4776 ilt = kzalloc(sizeof(*ilt), GFP_KERNEL);
4777 if (!ilt)
4778 goto alloc_err;
4779 bp->ilt = ilt;
4780
4781 return 0;
4782 alloc_err:
4783 bnx2x_free_mem_bp(bp);
4784 return -ENOMEM;
4785 }
4786
bnx2x_reload_if_running(struct net_device * dev)4787 int bnx2x_reload_if_running(struct net_device *dev)
4788 {
4789 struct bnx2x *bp = netdev_priv(dev);
4790
4791 if (unlikely(!netif_running(dev)))
4792 return 0;
4793
4794 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
4795 return bnx2x_nic_load(bp, LOAD_NORMAL);
4796 }
4797
bnx2x_get_cur_phy_idx(struct bnx2x * bp)4798 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4799 {
4800 u32 sel_phy_idx = 0;
4801 if (bp->link_params.num_phys <= 1)
4802 return INT_PHY;
4803
4804 if (bp->link_vars.link_up) {
4805 sel_phy_idx = EXT_PHY1;
4806 /* In case link is SERDES, check if the EXT_PHY2 is the one */
4807 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4808 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4809 sel_phy_idx = EXT_PHY2;
4810 } else {
4811
4812 switch (bnx2x_phy_selection(&bp->link_params)) {
4813 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4814 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
4815 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4816 sel_phy_idx = EXT_PHY1;
4817 break;
4818 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
4819 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4820 sel_phy_idx = EXT_PHY2;
4821 break;
4822 }
4823 }
4824
4825 return sel_phy_idx;
4826 }
bnx2x_get_link_cfg_idx(struct bnx2x * bp)4827 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4828 {
4829 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4830 /*
4831 * The selected activated PHY is always after swapping (in case PHY
4832 * swapping is enabled). So when swapping is enabled, we need to reverse
4833 * the configuration
4834 */
4835
4836 if (bp->link_params.multi_phy_config &
4837 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
4838 if (sel_phy_idx == EXT_PHY1)
4839 sel_phy_idx = EXT_PHY2;
4840 else if (sel_phy_idx == EXT_PHY2)
4841 sel_phy_idx = EXT_PHY1;
4842 }
4843 return LINK_CONFIG_IDX(sel_phy_idx);
4844 }
4845
4846 #ifdef NETDEV_FCOE_WWNN
bnx2x_fcoe_get_wwn(struct net_device * dev,u64 * wwn,int type)4847 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
4848 {
4849 struct bnx2x *bp = netdev_priv(dev);
4850 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4851
4852 switch (type) {
4853 case NETDEV_FCOE_WWNN:
4854 *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi,
4855 cp->fcoe_wwn_node_name_lo);
4856 break;
4857 case NETDEV_FCOE_WWPN:
4858 *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi,
4859 cp->fcoe_wwn_port_name_lo);
4860 break;
4861 default:
4862 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
4863 return -EINVAL;
4864 }
4865
4866 return 0;
4867 }
4868 #endif
4869
4870 /* called with rtnl_lock */
bnx2x_change_mtu(struct net_device * dev,int new_mtu)4871 int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
4872 {
4873 struct bnx2x *bp = netdev_priv(dev);
4874
4875 if (pci_num_vf(bp->pdev)) {
4876 DP(BNX2X_MSG_IOV, "VFs are enabled, can not change MTU\n");
4877 return -EPERM;
4878 }
4879
4880 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4881 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
4882 return -EAGAIN;
4883 }
4884
4885 /* This does not race with packet allocation
4886 * because the actual alloc size is
4887 * only updated as part of load
4888 */
4889 dev->mtu = new_mtu;
4890
4891 if (!bnx2x_mtu_allows_gro(new_mtu))
4892 dev->features &= ~NETIF_F_GRO_HW;
4893
4894 if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
4895 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
4896
4897 return bnx2x_reload_if_running(dev);
4898 }
4899
bnx2x_fix_features(struct net_device * dev,netdev_features_t features)4900 netdev_features_t bnx2x_fix_features(struct net_device *dev,
4901 netdev_features_t features)
4902 {
4903 struct bnx2x *bp = netdev_priv(dev);
4904
4905 if (pci_num_vf(bp->pdev)) {
4906 netdev_features_t changed = dev->features ^ features;
4907
4908 /* Revert the requested changes in features if they
4909 * would require internal reload of PF in bnx2x_set_features().
4910 */
4911 if (!(features & NETIF_F_RXCSUM) && !bp->disable_tpa) {
4912 features &= ~NETIF_F_RXCSUM;
4913 features |= dev->features & NETIF_F_RXCSUM;
4914 }
4915
4916 if (changed & NETIF_F_LOOPBACK) {
4917 features &= ~NETIF_F_LOOPBACK;
4918 features |= dev->features & NETIF_F_LOOPBACK;
4919 }
4920 }
4921
4922 /* TPA requires Rx CSUM offloading */
4923 if (!(features & NETIF_F_RXCSUM))
4924 features &= ~NETIF_F_LRO;
4925
4926 if (!(features & NETIF_F_GRO) || !bnx2x_mtu_allows_gro(dev->mtu))
4927 features &= ~NETIF_F_GRO_HW;
4928 if (features & NETIF_F_GRO_HW)
4929 features &= ~NETIF_F_LRO;
4930
4931 return features;
4932 }
4933
bnx2x_set_features(struct net_device * dev,netdev_features_t features)4934 int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
4935 {
4936 struct bnx2x *bp = netdev_priv(dev);
4937 netdev_features_t changes = features ^ dev->features;
4938 bool bnx2x_reload = false;
4939 int rc;
4940
4941 /* VFs or non SRIOV PFs should be able to change loopback feature */
4942 if (!pci_num_vf(bp->pdev)) {
4943 if (features & NETIF_F_LOOPBACK) {
4944 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4945 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4946 bnx2x_reload = true;
4947 }
4948 } else {
4949 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4950 bp->link_params.loopback_mode = LOOPBACK_NONE;
4951 bnx2x_reload = true;
4952 }
4953 }
4954 }
4955
4956 /* Don't care about GRO changes */
4957 changes &= ~NETIF_F_GRO;
4958
4959 if (changes)
4960 bnx2x_reload = true;
4961
4962 if (bnx2x_reload) {
4963 if (bp->recovery_state == BNX2X_RECOVERY_DONE) {
4964 dev->features = features;
4965 rc = bnx2x_reload_if_running(dev);
4966 return rc ? rc : 1;
4967 }
4968 /* else: bnx2x_nic_load() will be called at end of recovery */
4969 }
4970
4971 return 0;
4972 }
4973
bnx2x_tx_timeout(struct net_device * dev,unsigned int txqueue)4974 void bnx2x_tx_timeout(struct net_device *dev, unsigned int txqueue)
4975 {
4976 struct bnx2x *bp = netdev_priv(dev);
4977
4978 /* We want the information of the dump logged,
4979 * but calling bnx2x_panic() would kill all chances of recovery.
4980 */
4981 if (!bp->panic)
4982 #ifndef BNX2X_STOP_ON_ERROR
4983 bnx2x_panic_dump(bp, false);
4984 #else
4985 bnx2x_panic();
4986 #endif
4987
4988 /* This allows the netif to be shutdown gracefully before resetting */
4989 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_TX_TIMEOUT, 0);
4990 }
4991
bnx2x_suspend(struct device * dev_d)4992 static int __maybe_unused bnx2x_suspend(struct device *dev_d)
4993 {
4994 struct pci_dev *pdev = to_pci_dev(dev_d);
4995 struct net_device *dev = pci_get_drvdata(pdev);
4996 struct bnx2x *bp;
4997
4998 if (!dev) {
4999 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
5000 return -ENODEV;
5001 }
5002 bp = netdev_priv(dev);
5003
5004 rtnl_lock();
5005
5006 if (!netif_running(dev)) {
5007 rtnl_unlock();
5008 return 0;
5009 }
5010
5011 netif_device_detach(dev);
5012
5013 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
5014
5015 rtnl_unlock();
5016
5017 return 0;
5018 }
5019
bnx2x_resume(struct device * dev_d)5020 static int __maybe_unused bnx2x_resume(struct device *dev_d)
5021 {
5022 struct pci_dev *pdev = to_pci_dev(dev_d);
5023 struct net_device *dev = pci_get_drvdata(pdev);
5024 struct bnx2x *bp;
5025 int rc;
5026
5027 if (!dev) {
5028 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
5029 return -ENODEV;
5030 }
5031 bp = netdev_priv(dev);
5032
5033 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
5034 BNX2X_ERR("Handling parity error recovery. Try again later\n");
5035 return -EAGAIN;
5036 }
5037
5038 rtnl_lock();
5039
5040 if (!netif_running(dev)) {
5041 rtnl_unlock();
5042 return 0;
5043 }
5044
5045 netif_device_attach(dev);
5046
5047 rc = bnx2x_nic_load(bp, LOAD_OPEN);
5048
5049 rtnl_unlock();
5050
5051 return rc;
5052 }
5053
5054 SIMPLE_DEV_PM_OPS(bnx2x_pm_ops, bnx2x_suspend, bnx2x_resume);
5055
bnx2x_set_ctx_validation(struct bnx2x * bp,struct eth_context * cxt,u32 cid)5056 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
5057 u32 cid)
5058 {
5059 if (!cxt) {
5060 BNX2X_ERR("bad context pointer %p\n", cxt);
5061 return;
5062 }
5063
5064 /* ustorm cxt validation */
5065 cxt->ustorm_ag_context.cdu_usage =
5066 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
5067 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
5068 /* xcontext validation */
5069 cxt->xstorm_ag_context.cdu_reserved =
5070 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
5071 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
5072 }
5073
storm_memset_hc_timeout(struct bnx2x * bp,u8 port,u8 fw_sb_id,u8 sb_index,u8 ticks)5074 static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
5075 u8 fw_sb_id, u8 sb_index,
5076 u8 ticks)
5077 {
5078 u32 addr = BAR_CSTRORM_INTMEM +
5079 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
5080 REG_WR8(bp, addr, ticks);
5081 DP(NETIF_MSG_IFUP,
5082 "port %x fw_sb_id %d sb_index %d ticks %d\n",
5083 port, fw_sb_id, sb_index, ticks);
5084 }
5085
storm_memset_hc_disable(struct bnx2x * bp,u8 port,u16 fw_sb_id,u8 sb_index,u8 disable)5086 static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
5087 u16 fw_sb_id, u8 sb_index,
5088 u8 disable)
5089 {
5090 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
5091 u32 addr = BAR_CSTRORM_INTMEM +
5092 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
5093 u8 flags = REG_RD8(bp, addr);
5094 /* clear and set */
5095 flags &= ~HC_INDEX_DATA_HC_ENABLED;
5096 flags |= enable_flag;
5097 REG_WR8(bp, addr, flags);
5098 DP(NETIF_MSG_IFUP,
5099 "port %x fw_sb_id %d sb_index %d disable %d\n",
5100 port, fw_sb_id, sb_index, disable);
5101 }
5102
bnx2x_update_coalesce_sb_index(struct bnx2x * bp,u8 fw_sb_id,u8 sb_index,u8 disable,u16 usec)5103 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
5104 u8 sb_index, u8 disable, u16 usec)
5105 {
5106 int port = BP_PORT(bp);
5107 u8 ticks = usec / BNX2X_BTR;
5108
5109 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
5110
5111 disable = disable ? 1 : (usec ? 0 : 1);
5112 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
5113 }
5114
bnx2x_schedule_sp_rtnl(struct bnx2x * bp,enum sp_rtnl_flag flag,u32 verbose)5115 void bnx2x_schedule_sp_rtnl(struct bnx2x *bp, enum sp_rtnl_flag flag,
5116 u32 verbose)
5117 {
5118 smp_mb__before_atomic();
5119 set_bit(flag, &bp->sp_rtnl_state);
5120 smp_mb__after_atomic();
5121 DP((BNX2X_MSG_SP | verbose), "Scheduling sp_rtnl task [Flag: %d]\n",
5122 flag);
5123 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5124 }
5125