1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/ctype.h>
12 #include <linux/stringify.h>
13 #include <linux/ethtool.h>
14 #include <linux/ethtool_netlink.h>
15 #include <linux/linkmode.h>
16 #include <linux/interrupt.h>
17 #include <linux/pci.h>
18 #include <linux/etherdevice.h>
19 #include <linux/crc32.h>
20 #include <linux/firmware.h>
21 #include <linux/utsname.h>
22 #include <linux/time.h>
23 #include <linux/ptp_clock_kernel.h>
24 #include <linux/net_tstamp.h>
25 #include <linux/timecounter.h>
26 #include <net/netlink.h>
27 #include "bnxt_hsi.h"
28 #include "bnxt.h"
29 #include "bnxt_hwrm.h"
30 #include "bnxt_ulp.h"
31 #include "bnxt_xdp.h"
32 #include "bnxt_ptp.h"
33 #include "bnxt_ethtool.h"
34 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
35 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
36 #include "bnxt_coredump.h"
37
38 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \
39 do { \
40 if (extack) \
41 NL_SET_ERR_MSG_MOD(extack, msg); \
42 netdev_err(dev, "%s\n", msg); \
43 } while (0)
44
bnxt_get_msglevel(struct net_device * dev)45 static u32 bnxt_get_msglevel(struct net_device *dev)
46 {
47 struct bnxt *bp = netdev_priv(dev);
48
49 return bp->msg_enable;
50 }
51
bnxt_set_msglevel(struct net_device * dev,u32 value)52 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
53 {
54 struct bnxt *bp = netdev_priv(dev);
55
56 bp->msg_enable = value;
57 }
58
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)59 static int bnxt_get_coalesce(struct net_device *dev,
60 struct ethtool_coalesce *coal,
61 struct kernel_ethtool_coalesce *kernel_coal,
62 struct netlink_ext_ack *extack)
63 {
64 struct bnxt *bp = netdev_priv(dev);
65 struct bnxt_coal *hw_coal;
66 u16 mult;
67
68 memset(coal, 0, sizeof(*coal));
69
70 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
71
72 hw_coal = &bp->rx_coal;
73 mult = hw_coal->bufs_per_record;
74 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
75 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
76 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
77 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
78 if (hw_coal->flags &
79 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
80 kernel_coal->use_cqe_mode_rx = true;
81
82 hw_coal = &bp->tx_coal;
83 mult = hw_coal->bufs_per_record;
84 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
85 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
86 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
87 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
88 if (hw_coal->flags &
89 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
90 kernel_coal->use_cqe_mode_tx = true;
91
92 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
93
94 return 0;
95 }
96
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)97 static int bnxt_set_coalesce(struct net_device *dev,
98 struct ethtool_coalesce *coal,
99 struct kernel_ethtool_coalesce *kernel_coal,
100 struct netlink_ext_ack *extack)
101 {
102 struct bnxt *bp = netdev_priv(dev);
103 bool update_stats = false;
104 struct bnxt_coal *hw_coal;
105 int rc = 0;
106 u16 mult;
107
108 if (coal->use_adaptive_rx_coalesce) {
109 bp->flags |= BNXT_FLAG_DIM;
110 } else {
111 if (bp->flags & BNXT_FLAG_DIM) {
112 bp->flags &= ~(BNXT_FLAG_DIM);
113 goto reset_coalesce;
114 }
115 }
116
117 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
118 !(bp->coal_cap.cmpl_params &
119 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
120 return -EOPNOTSUPP;
121
122 hw_coal = &bp->rx_coal;
123 mult = hw_coal->bufs_per_record;
124 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
125 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
126 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
127 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
128 hw_coal->flags &=
129 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
130 if (kernel_coal->use_cqe_mode_rx)
131 hw_coal->flags |=
132 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
133
134 hw_coal = &bp->tx_coal;
135 mult = hw_coal->bufs_per_record;
136 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
137 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
138 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
139 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
140 hw_coal->flags &=
141 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
142 if (kernel_coal->use_cqe_mode_tx)
143 hw_coal->flags |=
144 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
145
146 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
147 u32 stats_ticks = coal->stats_block_coalesce_usecs;
148
149 /* Allow 0, which means disable. */
150 if (stats_ticks)
151 stats_ticks = clamp_t(u32, stats_ticks,
152 BNXT_MIN_STATS_COAL_TICKS,
153 BNXT_MAX_STATS_COAL_TICKS);
154 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
155 bp->stats_coal_ticks = stats_ticks;
156 if (bp->stats_coal_ticks)
157 bp->current_interval =
158 bp->stats_coal_ticks * HZ / 1000000;
159 else
160 bp->current_interval = BNXT_TIMER_INTERVAL;
161 update_stats = true;
162 }
163
164 reset_coalesce:
165 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
166 if (update_stats) {
167 bnxt_close_nic(bp, true, false);
168 rc = bnxt_open_nic(bp, true, false);
169 } else {
170 rc = bnxt_hwrm_set_coal(bp);
171 }
172 }
173
174 return rc;
175 }
176
177 static const char * const bnxt_ring_rx_stats_str[] = {
178 "rx_ucast_packets",
179 "rx_mcast_packets",
180 "rx_bcast_packets",
181 "rx_discards",
182 "rx_errors",
183 "rx_ucast_bytes",
184 "rx_mcast_bytes",
185 "rx_bcast_bytes",
186 };
187
188 static const char * const bnxt_ring_tx_stats_str[] = {
189 "tx_ucast_packets",
190 "tx_mcast_packets",
191 "tx_bcast_packets",
192 "tx_errors",
193 "tx_discards",
194 "tx_ucast_bytes",
195 "tx_mcast_bytes",
196 "tx_bcast_bytes",
197 };
198
199 static const char * const bnxt_ring_tpa_stats_str[] = {
200 "tpa_packets",
201 "tpa_bytes",
202 "tpa_events",
203 "tpa_aborts",
204 };
205
206 static const char * const bnxt_ring_tpa2_stats_str[] = {
207 "rx_tpa_eligible_pkt",
208 "rx_tpa_eligible_bytes",
209 "rx_tpa_pkt",
210 "rx_tpa_bytes",
211 "rx_tpa_errors",
212 "rx_tpa_events",
213 };
214
215 static const char * const bnxt_rx_sw_stats_str[] = {
216 "rx_l4_csum_errors",
217 "rx_resets",
218 "rx_buf_errors",
219 };
220
221 static const char * const bnxt_cmn_sw_stats_str[] = {
222 "missed_irqs",
223 };
224
225 #define BNXT_RX_STATS_ENTRY(counter) \
226 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
227
228 #define BNXT_TX_STATS_ENTRY(counter) \
229 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
230
231 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
232 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
233
234 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
235 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
236
237 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
238 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
240
241 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
242 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
244
245 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
246 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
247 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
248 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
254
255 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
256 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
257 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
258 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
264
265 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
266 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
267 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
268
269 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
270 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
271 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
272
273 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
274 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
275 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
276 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
277 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
282
283 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
284 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
285 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
286 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
287 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
292
293 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
294 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
296
297 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
298 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
306
307 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
308 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
309 __stringify(counter##_pri##n) }
310
311 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
312 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
313 __stringify(counter##_pri##n) }
314
315 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
316 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
317 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
318 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
324
325 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
326 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
327 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
328 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
334
335 enum {
336 RX_TOTAL_DISCARDS,
337 TX_TOTAL_DISCARDS,
338 RX_NETPOLL_DISCARDS,
339 };
340
341 static struct {
342 u64 counter;
343 char string[ETH_GSTRING_LEN];
344 } bnxt_sw_func_stats[] = {
345 {0, "rx_total_discard_pkts"},
346 {0, "tx_total_discard_pkts"},
347 {0, "rx_total_netpoll_discards"},
348 };
349
350 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
351 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
352 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
353 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
354
355 static const struct {
356 long offset;
357 char string[ETH_GSTRING_LEN];
358 } bnxt_port_stats_arr[] = {
359 BNXT_RX_STATS_ENTRY(rx_64b_frames),
360 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
361 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
362 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
363 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
364 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
365 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
366 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
367 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
368 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
369 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
370 BNXT_RX_STATS_ENTRY(rx_total_frames),
371 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
372 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
373 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
374 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
375 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
376 BNXT_RX_STATS_ENTRY(rx_pause_frames),
377 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
378 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
379 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
380 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
381 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
382 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
383 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
384 BNXT_RX_STATS_ENTRY(rx_good_frames),
385 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
386 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
387 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
388 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
393 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
394 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
395 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
396 BNXT_RX_STATS_ENTRY(rx_bytes),
397 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
398 BNXT_RX_STATS_ENTRY(rx_runt_frames),
399 BNXT_RX_STATS_ENTRY(rx_stat_discard),
400 BNXT_RX_STATS_ENTRY(rx_stat_err),
401
402 BNXT_TX_STATS_ENTRY(tx_64b_frames),
403 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
404 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
405 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
406 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
407 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
408 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
409 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
410 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
411 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
412 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
413 BNXT_TX_STATS_ENTRY(tx_good_frames),
414 BNXT_TX_STATS_ENTRY(tx_total_frames),
415 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
416 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
417 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
418 BNXT_TX_STATS_ENTRY(tx_pause_frames),
419 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
420 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
421 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
422 BNXT_TX_STATS_ENTRY(tx_err),
423 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
424 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
425 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
426 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
427 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
432 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
433 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
434 BNXT_TX_STATS_ENTRY(tx_total_collisions),
435 BNXT_TX_STATS_ENTRY(tx_bytes),
436 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
437 BNXT_TX_STATS_ENTRY(tx_stat_discard),
438 BNXT_TX_STATS_ENTRY(tx_stat_error),
439 };
440
441 static const struct {
442 long offset;
443 char string[ETH_GSTRING_LEN];
444 } bnxt_port_stats_ext_arr[] = {
445 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
446 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
447 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
448 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
449 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
450 BNXT_RX_STATS_EXT_COS_ENTRIES,
451 BNXT_RX_STATS_EXT_PFC_ENTRIES,
452 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
453 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
454 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
455 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
456 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
457 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
458 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
459 };
460
461 static const struct {
462 long offset;
463 char string[ETH_GSTRING_LEN];
464 } bnxt_tx_port_stats_ext_arr[] = {
465 BNXT_TX_STATS_EXT_COS_ENTRIES,
466 BNXT_TX_STATS_EXT_PFC_ENTRIES,
467 };
468
469 static const struct {
470 long base_off;
471 char string[ETH_GSTRING_LEN];
472 } bnxt_rx_bytes_pri_arr[] = {
473 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
474 };
475
476 static const struct {
477 long base_off;
478 char string[ETH_GSTRING_LEN];
479 } bnxt_rx_pkts_pri_arr[] = {
480 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
481 };
482
483 static const struct {
484 long base_off;
485 char string[ETH_GSTRING_LEN];
486 } bnxt_tx_bytes_pri_arr[] = {
487 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
488 };
489
490 static const struct {
491 long base_off;
492 char string[ETH_GSTRING_LEN];
493 } bnxt_tx_pkts_pri_arr[] = {
494 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
495 };
496
497 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
498 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
499 #define BNXT_NUM_STATS_PRI \
500 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
501 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
502 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
503 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
504
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)505 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
506 {
507 if (BNXT_SUPPORTS_TPA(bp)) {
508 if (bp->max_tpa_v2) {
509 if (BNXT_CHIP_P5_THOR(bp))
510 return BNXT_NUM_TPA_RING_STATS_P5;
511 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
512 }
513 return BNXT_NUM_TPA_RING_STATS;
514 }
515 return 0;
516 }
517
bnxt_get_num_ring_stats(struct bnxt * bp)518 static int bnxt_get_num_ring_stats(struct bnxt *bp)
519 {
520 int rx, tx, cmn;
521
522 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
523 bnxt_get_num_tpa_ring_stats(bp);
524 tx = NUM_RING_TX_HW_STATS;
525 cmn = NUM_RING_CMN_SW_STATS;
526 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
527 cmn * bp->cp_nr_rings;
528 }
529
bnxt_get_num_stats(struct bnxt * bp)530 static int bnxt_get_num_stats(struct bnxt *bp)
531 {
532 int num_stats = bnxt_get_num_ring_stats(bp);
533
534 num_stats += BNXT_NUM_SW_FUNC_STATS;
535
536 if (bp->flags & BNXT_FLAG_PORT_STATS)
537 num_stats += BNXT_NUM_PORT_STATS;
538
539 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
540 num_stats += bp->fw_rx_stats_ext_size +
541 bp->fw_tx_stats_ext_size;
542 if (bp->pri2cos_valid)
543 num_stats += BNXT_NUM_STATS_PRI;
544 }
545
546 return num_stats;
547 }
548
bnxt_get_sset_count(struct net_device * dev,int sset)549 static int bnxt_get_sset_count(struct net_device *dev, int sset)
550 {
551 struct bnxt *bp = netdev_priv(dev);
552
553 switch (sset) {
554 case ETH_SS_STATS:
555 return bnxt_get_num_stats(bp);
556 case ETH_SS_TEST:
557 if (!bp->num_tests)
558 return -EOPNOTSUPP;
559 return bp->num_tests;
560 default:
561 return -EOPNOTSUPP;
562 }
563 }
564
is_rx_ring(struct bnxt * bp,int ring_num)565 static bool is_rx_ring(struct bnxt *bp, int ring_num)
566 {
567 return ring_num < bp->rx_nr_rings;
568 }
569
is_tx_ring(struct bnxt * bp,int ring_num)570 static bool is_tx_ring(struct bnxt *bp, int ring_num)
571 {
572 int tx_base = 0;
573
574 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
575 tx_base = bp->rx_nr_rings;
576
577 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
578 return true;
579 return false;
580 }
581
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)582 static void bnxt_get_ethtool_stats(struct net_device *dev,
583 struct ethtool_stats *stats, u64 *buf)
584 {
585 u32 i, j = 0;
586 struct bnxt *bp = netdev_priv(dev);
587 u32 tpa_stats;
588
589 if (!bp->bnapi) {
590 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
591 goto skip_ring_stats;
592 }
593
594 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
595 bnxt_sw_func_stats[i].counter = 0;
596
597 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
598 for (i = 0; i < bp->cp_nr_rings; i++) {
599 struct bnxt_napi *bnapi = bp->bnapi[i];
600 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
601 u64 *sw_stats = cpr->stats.sw_stats;
602 u64 *sw;
603 int k;
604
605 if (is_rx_ring(bp, i)) {
606 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
607 buf[j] = sw_stats[k];
608 }
609 if (is_tx_ring(bp, i)) {
610 k = NUM_RING_RX_HW_STATS;
611 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
612 j++, k++)
613 buf[j] = sw_stats[k];
614 }
615 if (!tpa_stats || !is_rx_ring(bp, i))
616 goto skip_tpa_ring_stats;
617
618 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
619 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
620 tpa_stats; j++, k++)
621 buf[j] = sw_stats[k];
622
623 skip_tpa_ring_stats:
624 sw = (u64 *)&cpr->sw_stats.rx;
625 if (is_rx_ring(bp, i)) {
626 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
627 buf[j] = sw[k];
628 }
629
630 sw = (u64 *)&cpr->sw_stats.cmn;
631 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
632 buf[j] = sw[k];
633
634 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
635 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts);
636 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
637 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts);
638 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter +=
639 cpr->sw_stats.rx.rx_netpoll_discards;
640 }
641
642 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
643 buf[j] = bnxt_sw_func_stats[i].counter;
644
645 skip_ring_stats:
646 if (bp->flags & BNXT_FLAG_PORT_STATS) {
647 u64 *port_stats = bp->port_stats.sw_stats;
648
649 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
650 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
651 }
652 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
653 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
654 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
655
656 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
657 buf[j] = *(rx_port_stats_ext +
658 bnxt_port_stats_ext_arr[i].offset);
659 }
660 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
661 buf[j] = *(tx_port_stats_ext +
662 bnxt_tx_port_stats_ext_arr[i].offset);
663 }
664 if (bp->pri2cos_valid) {
665 for (i = 0; i < 8; i++, j++) {
666 long n = bnxt_rx_bytes_pri_arr[i].base_off +
667 bp->pri2cos_idx[i];
668
669 buf[j] = *(rx_port_stats_ext + n);
670 }
671 for (i = 0; i < 8; i++, j++) {
672 long n = bnxt_rx_pkts_pri_arr[i].base_off +
673 bp->pri2cos_idx[i];
674
675 buf[j] = *(rx_port_stats_ext + n);
676 }
677 for (i = 0; i < 8; i++, j++) {
678 long n = bnxt_tx_bytes_pri_arr[i].base_off +
679 bp->pri2cos_idx[i];
680
681 buf[j] = *(tx_port_stats_ext + n);
682 }
683 for (i = 0; i < 8; i++, j++) {
684 long n = bnxt_tx_pkts_pri_arr[i].base_off +
685 bp->pri2cos_idx[i];
686
687 buf[j] = *(tx_port_stats_ext + n);
688 }
689 }
690 }
691 }
692
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)693 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
694 {
695 struct bnxt *bp = netdev_priv(dev);
696 static const char * const *str;
697 u32 i, j, num_str;
698
699 switch (stringset) {
700 case ETH_SS_STATS:
701 for (i = 0; i < bp->cp_nr_rings; i++) {
702 if (is_rx_ring(bp, i)) {
703 num_str = NUM_RING_RX_HW_STATS;
704 for (j = 0; j < num_str; j++) {
705 sprintf(buf, "[%d]: %s", i,
706 bnxt_ring_rx_stats_str[j]);
707 buf += ETH_GSTRING_LEN;
708 }
709 }
710 if (is_tx_ring(bp, i)) {
711 num_str = NUM_RING_TX_HW_STATS;
712 for (j = 0; j < num_str; j++) {
713 sprintf(buf, "[%d]: %s", i,
714 bnxt_ring_tx_stats_str[j]);
715 buf += ETH_GSTRING_LEN;
716 }
717 }
718 num_str = bnxt_get_num_tpa_ring_stats(bp);
719 if (!num_str || !is_rx_ring(bp, i))
720 goto skip_tpa_stats;
721
722 if (bp->max_tpa_v2)
723 str = bnxt_ring_tpa2_stats_str;
724 else
725 str = bnxt_ring_tpa_stats_str;
726
727 for (j = 0; j < num_str; j++) {
728 sprintf(buf, "[%d]: %s", i, str[j]);
729 buf += ETH_GSTRING_LEN;
730 }
731 skip_tpa_stats:
732 if (is_rx_ring(bp, i)) {
733 num_str = NUM_RING_RX_SW_STATS;
734 for (j = 0; j < num_str; j++) {
735 sprintf(buf, "[%d]: %s", i,
736 bnxt_rx_sw_stats_str[j]);
737 buf += ETH_GSTRING_LEN;
738 }
739 }
740 num_str = NUM_RING_CMN_SW_STATS;
741 for (j = 0; j < num_str; j++) {
742 sprintf(buf, "[%d]: %s", i,
743 bnxt_cmn_sw_stats_str[j]);
744 buf += ETH_GSTRING_LEN;
745 }
746 }
747 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
748 strcpy(buf, bnxt_sw_func_stats[i].string);
749 buf += ETH_GSTRING_LEN;
750 }
751
752 if (bp->flags & BNXT_FLAG_PORT_STATS) {
753 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
754 strcpy(buf, bnxt_port_stats_arr[i].string);
755 buf += ETH_GSTRING_LEN;
756 }
757 }
758 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
759 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
760 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
761 buf += ETH_GSTRING_LEN;
762 }
763 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
764 strcpy(buf,
765 bnxt_tx_port_stats_ext_arr[i].string);
766 buf += ETH_GSTRING_LEN;
767 }
768 if (bp->pri2cos_valid) {
769 for (i = 0; i < 8; i++) {
770 strcpy(buf,
771 bnxt_rx_bytes_pri_arr[i].string);
772 buf += ETH_GSTRING_LEN;
773 }
774 for (i = 0; i < 8; i++) {
775 strcpy(buf,
776 bnxt_rx_pkts_pri_arr[i].string);
777 buf += ETH_GSTRING_LEN;
778 }
779 for (i = 0; i < 8; i++) {
780 strcpy(buf,
781 bnxt_tx_bytes_pri_arr[i].string);
782 buf += ETH_GSTRING_LEN;
783 }
784 for (i = 0; i < 8; i++) {
785 strcpy(buf,
786 bnxt_tx_pkts_pri_arr[i].string);
787 buf += ETH_GSTRING_LEN;
788 }
789 }
790 }
791 break;
792 case ETH_SS_TEST:
793 if (bp->num_tests)
794 memcpy(buf, bp->test_info->string,
795 bp->num_tests * ETH_GSTRING_LEN);
796 break;
797 default:
798 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
799 stringset);
800 break;
801 }
802 }
803
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)804 static void bnxt_get_ringparam(struct net_device *dev,
805 struct ethtool_ringparam *ering,
806 struct kernel_ethtool_ringparam *kernel_ering,
807 struct netlink_ext_ack *extack)
808 {
809 struct bnxt *bp = netdev_priv(dev);
810
811 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
812 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
813 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
814 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
815 } else {
816 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
817 ering->rx_jumbo_max_pending = 0;
818 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
819 }
820 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
821
822 ering->rx_pending = bp->rx_ring_size;
823 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
824 ering->tx_pending = bp->tx_ring_size;
825 }
826
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)827 static int bnxt_set_ringparam(struct net_device *dev,
828 struct ethtool_ringparam *ering,
829 struct kernel_ethtool_ringparam *kernel_ering,
830 struct netlink_ext_ack *extack)
831 {
832 struct bnxt *bp = netdev_priv(dev);
833
834 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
835 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
836 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
837 return -EINVAL;
838
839 if (netif_running(dev))
840 bnxt_close_nic(bp, false, false);
841
842 bp->rx_ring_size = ering->rx_pending;
843 bp->tx_ring_size = ering->tx_pending;
844 bnxt_set_ring_params(bp);
845
846 if (netif_running(dev))
847 return bnxt_open_nic(bp, false, false);
848
849 return 0;
850 }
851
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)852 static void bnxt_get_channels(struct net_device *dev,
853 struct ethtool_channels *channel)
854 {
855 struct bnxt *bp = netdev_priv(dev);
856 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
857 int max_rx_rings, max_tx_rings, tcs;
858 int max_tx_sch_inputs, tx_grps;
859
860 /* Get the most up-to-date max_tx_sch_inputs. */
861 if (netif_running(dev) && BNXT_NEW_RM(bp))
862 bnxt_hwrm_func_resc_qcaps(bp, false);
863 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
864
865 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
866 if (max_tx_sch_inputs)
867 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
868
869 tcs = netdev_get_num_tc(dev);
870 tx_grps = max(tcs, 1);
871 if (bp->tx_nr_rings_xdp)
872 tx_grps++;
873 max_tx_rings /= tx_grps;
874 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
875
876 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
877 max_rx_rings = 0;
878 max_tx_rings = 0;
879 }
880 if (max_tx_sch_inputs)
881 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
882
883 if (tcs > 1)
884 max_tx_rings /= tcs;
885
886 channel->max_rx = max_rx_rings;
887 channel->max_tx = max_tx_rings;
888 channel->max_other = 0;
889 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
890 channel->combined_count = bp->rx_nr_rings;
891 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
892 channel->combined_count--;
893 } else {
894 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
895 channel->rx_count = bp->rx_nr_rings;
896 channel->tx_count = bp->tx_nr_rings_per_tc;
897 }
898 }
899 }
900
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)901 static int bnxt_set_channels(struct net_device *dev,
902 struct ethtool_channels *channel)
903 {
904 struct bnxt *bp = netdev_priv(dev);
905 int req_tx_rings, req_rx_rings, tcs;
906 bool sh = false;
907 int tx_xdp = 0;
908 int rc = 0;
909
910 if (channel->other_count)
911 return -EINVAL;
912
913 if (!channel->combined_count &&
914 (!channel->rx_count || !channel->tx_count))
915 return -EINVAL;
916
917 if (channel->combined_count &&
918 (channel->rx_count || channel->tx_count))
919 return -EINVAL;
920
921 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
922 channel->tx_count))
923 return -EINVAL;
924
925 if (channel->combined_count)
926 sh = true;
927
928 tcs = netdev_get_num_tc(dev);
929
930 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
931 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
932 if (bp->tx_nr_rings_xdp) {
933 if (!sh) {
934 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
935 return -EINVAL;
936 }
937 tx_xdp = req_rx_rings;
938 }
939 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
940 if (rc) {
941 netdev_warn(dev, "Unable to allocate the requested rings\n");
942 return rc;
943 }
944
945 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
946 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
947 netif_is_rxfh_configured(dev)) {
948 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
949 return -EINVAL;
950 }
951
952 if (netif_running(dev)) {
953 if (BNXT_PF(bp)) {
954 /* TODO CHIMP_FW: Send message to all VF's
955 * before PF unload
956 */
957 }
958 bnxt_close_nic(bp, true, false);
959 }
960
961 if (sh) {
962 bp->flags |= BNXT_FLAG_SHARED_RINGS;
963 bp->rx_nr_rings = channel->combined_count;
964 bp->tx_nr_rings_per_tc = channel->combined_count;
965 } else {
966 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
967 bp->rx_nr_rings = channel->rx_count;
968 bp->tx_nr_rings_per_tc = channel->tx_count;
969 }
970 bp->tx_nr_rings_xdp = tx_xdp;
971 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
972 if (tcs > 1)
973 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
974
975 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
976 bp->tx_nr_rings + bp->rx_nr_rings;
977
978 /* After changing number of rx channels, update NTUPLE feature. */
979 netdev_update_features(dev);
980 if (netif_running(dev)) {
981 rc = bnxt_open_nic(bp, true, false);
982 if ((!rc) && BNXT_PF(bp)) {
983 /* TODO CHIMP_FW: Send message to all VF's
984 * to renable
985 */
986 }
987 } else {
988 rc = bnxt_reserve_rings(bp, true);
989 }
990
991 return rc;
992 }
993
994 #ifdef CONFIG_RFS_ACCEL
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)995 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
996 u32 *rule_locs)
997 {
998 int i, j = 0;
999
1000 cmd->data = bp->ntp_fltr_count;
1001 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1002 struct hlist_head *head;
1003 struct bnxt_ntuple_filter *fltr;
1004
1005 head = &bp->ntp_fltr_hash_tbl[i];
1006 rcu_read_lock();
1007 hlist_for_each_entry_rcu(fltr, head, hash) {
1008 if (j == cmd->rule_cnt)
1009 break;
1010 rule_locs[j++] = fltr->sw_id;
1011 }
1012 rcu_read_unlock();
1013 if (j == cmd->rule_cnt)
1014 break;
1015 }
1016 cmd->rule_cnt = j;
1017 return 0;
1018 }
1019
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1020 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1021 {
1022 struct ethtool_rx_flow_spec *fs =
1023 (struct ethtool_rx_flow_spec *)&cmd->fs;
1024 struct bnxt_ntuple_filter *fltr;
1025 struct flow_keys *fkeys;
1026 int i, rc = -EINVAL;
1027
1028 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
1029 return rc;
1030
1031 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1032 struct hlist_head *head;
1033
1034 head = &bp->ntp_fltr_hash_tbl[i];
1035 rcu_read_lock();
1036 hlist_for_each_entry_rcu(fltr, head, hash) {
1037 if (fltr->sw_id == fs->location)
1038 goto fltr_found;
1039 }
1040 rcu_read_unlock();
1041 }
1042 return rc;
1043
1044 fltr_found:
1045 fkeys = &fltr->fkeys;
1046 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1047 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1048 fs->flow_type = TCP_V4_FLOW;
1049 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1050 fs->flow_type = UDP_V4_FLOW;
1051 else
1052 goto fltr_err;
1053
1054 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1055 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1056
1057 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1058 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1059
1060 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1061 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1062
1063 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1064 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1065 } else {
1066 int i;
1067
1068 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1069 fs->flow_type = TCP_V6_FLOW;
1070 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1071 fs->flow_type = UDP_V6_FLOW;
1072 else
1073 goto fltr_err;
1074
1075 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1076 fkeys->addrs.v6addrs.src;
1077 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1078 fkeys->addrs.v6addrs.dst;
1079 for (i = 0; i < 4; i++) {
1080 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1081 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1082 }
1083 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1084 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1085
1086 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1087 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1088 }
1089
1090 fs->ring_cookie = fltr->rxq;
1091 rc = 0;
1092
1093 fltr_err:
1094 rcu_read_unlock();
1095
1096 return rc;
1097 }
1098 #endif
1099
get_ethtool_ipv4_rss(struct bnxt * bp)1100 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1101 {
1102 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1103 return RXH_IP_SRC | RXH_IP_DST;
1104 return 0;
1105 }
1106
get_ethtool_ipv6_rss(struct bnxt * bp)1107 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1108 {
1109 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1110 return RXH_IP_SRC | RXH_IP_DST;
1111 return 0;
1112 }
1113
bnxt_grxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1114 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1115 {
1116 cmd->data = 0;
1117 switch (cmd->flow_type) {
1118 case TCP_V4_FLOW:
1119 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1120 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1121 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1122 cmd->data |= get_ethtool_ipv4_rss(bp);
1123 break;
1124 case UDP_V4_FLOW:
1125 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1126 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1127 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1128 fallthrough;
1129 case SCTP_V4_FLOW:
1130 case AH_ESP_V4_FLOW:
1131 case AH_V4_FLOW:
1132 case ESP_V4_FLOW:
1133 case IPV4_FLOW:
1134 cmd->data |= get_ethtool_ipv4_rss(bp);
1135 break;
1136
1137 case TCP_V6_FLOW:
1138 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1139 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1140 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1141 cmd->data |= get_ethtool_ipv6_rss(bp);
1142 break;
1143 case UDP_V6_FLOW:
1144 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1145 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1146 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1147 fallthrough;
1148 case SCTP_V6_FLOW:
1149 case AH_ESP_V6_FLOW:
1150 case AH_V6_FLOW:
1151 case ESP_V6_FLOW:
1152 case IPV6_FLOW:
1153 cmd->data |= get_ethtool_ipv6_rss(bp);
1154 break;
1155 }
1156 return 0;
1157 }
1158
1159 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1160 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1161
bnxt_srxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1162 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1163 {
1164 u32 rss_hash_cfg = bp->rss_hash_cfg;
1165 int tuple, rc = 0;
1166
1167 if (cmd->data == RXH_4TUPLE)
1168 tuple = 4;
1169 else if (cmd->data == RXH_2TUPLE)
1170 tuple = 2;
1171 else if (!cmd->data)
1172 tuple = 0;
1173 else
1174 return -EINVAL;
1175
1176 if (cmd->flow_type == TCP_V4_FLOW) {
1177 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1178 if (tuple == 4)
1179 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1180 } else if (cmd->flow_type == UDP_V4_FLOW) {
1181 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1182 return -EINVAL;
1183 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1184 if (tuple == 4)
1185 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1186 } else if (cmd->flow_type == TCP_V6_FLOW) {
1187 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1188 if (tuple == 4)
1189 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1190 } else if (cmd->flow_type == UDP_V6_FLOW) {
1191 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1192 return -EINVAL;
1193 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1194 if (tuple == 4)
1195 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1196 } else if (tuple == 4) {
1197 return -EINVAL;
1198 }
1199
1200 switch (cmd->flow_type) {
1201 case TCP_V4_FLOW:
1202 case UDP_V4_FLOW:
1203 case SCTP_V4_FLOW:
1204 case AH_ESP_V4_FLOW:
1205 case AH_V4_FLOW:
1206 case ESP_V4_FLOW:
1207 case IPV4_FLOW:
1208 if (tuple == 2)
1209 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1210 else if (!tuple)
1211 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1212 break;
1213
1214 case TCP_V6_FLOW:
1215 case UDP_V6_FLOW:
1216 case SCTP_V6_FLOW:
1217 case AH_ESP_V6_FLOW:
1218 case AH_V6_FLOW:
1219 case ESP_V6_FLOW:
1220 case IPV6_FLOW:
1221 if (tuple == 2)
1222 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1223 else if (!tuple)
1224 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1225 break;
1226 }
1227
1228 if (bp->rss_hash_cfg == rss_hash_cfg)
1229 return 0;
1230
1231 bp->rss_hash_cfg = rss_hash_cfg;
1232 if (netif_running(bp->dev)) {
1233 bnxt_close_nic(bp, false, false);
1234 rc = bnxt_open_nic(bp, false, false);
1235 }
1236 return rc;
1237 }
1238
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1239 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1240 u32 *rule_locs)
1241 {
1242 struct bnxt *bp = netdev_priv(dev);
1243 int rc = 0;
1244
1245 switch (cmd->cmd) {
1246 #ifdef CONFIG_RFS_ACCEL
1247 case ETHTOOL_GRXRINGS:
1248 cmd->data = bp->rx_nr_rings;
1249 break;
1250
1251 case ETHTOOL_GRXCLSRLCNT:
1252 cmd->rule_cnt = bp->ntp_fltr_count;
1253 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1254 break;
1255
1256 case ETHTOOL_GRXCLSRLALL:
1257 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1258 break;
1259
1260 case ETHTOOL_GRXCLSRULE:
1261 rc = bnxt_grxclsrule(bp, cmd);
1262 break;
1263 #endif
1264
1265 case ETHTOOL_GRXFH:
1266 rc = bnxt_grxfh(bp, cmd);
1267 break;
1268
1269 default:
1270 rc = -EOPNOTSUPP;
1271 break;
1272 }
1273
1274 return rc;
1275 }
1276
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1277 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1278 {
1279 struct bnxt *bp = netdev_priv(dev);
1280 int rc;
1281
1282 switch (cmd->cmd) {
1283 case ETHTOOL_SRXFH:
1284 rc = bnxt_srxfh(bp, cmd);
1285 break;
1286
1287 default:
1288 rc = -EOPNOTSUPP;
1289 break;
1290 }
1291 return rc;
1292 }
1293
bnxt_get_rxfh_indir_size(struct net_device * dev)1294 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1295 {
1296 struct bnxt *bp = netdev_priv(dev);
1297
1298 if (bp->flags & BNXT_FLAG_CHIP_P5)
1299 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1300 return HW_HASH_INDEX_SIZE;
1301 }
1302
bnxt_get_rxfh_key_size(struct net_device * dev)1303 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1304 {
1305 return HW_HASH_KEY_SIZE;
1306 }
1307
bnxt_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)1308 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1309 u8 *hfunc)
1310 {
1311 struct bnxt *bp = netdev_priv(dev);
1312 struct bnxt_vnic_info *vnic;
1313 u32 i, tbl_size;
1314
1315 if (hfunc)
1316 *hfunc = ETH_RSS_HASH_TOP;
1317
1318 if (!bp->vnic_info)
1319 return 0;
1320
1321 vnic = &bp->vnic_info[0];
1322 if (indir && bp->rss_indir_tbl) {
1323 tbl_size = bnxt_get_rxfh_indir_size(dev);
1324 for (i = 0; i < tbl_size; i++)
1325 indir[i] = bp->rss_indir_tbl[i];
1326 }
1327
1328 if (key && vnic->rss_hash_key)
1329 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1330
1331 return 0;
1332 }
1333
bnxt_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1334 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1335 const u8 *key, const u8 hfunc)
1336 {
1337 struct bnxt *bp = netdev_priv(dev);
1338 int rc = 0;
1339
1340 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1341 return -EOPNOTSUPP;
1342
1343 if (key)
1344 return -EOPNOTSUPP;
1345
1346 if (indir) {
1347 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1348
1349 for (i = 0; i < tbl_size; i++)
1350 bp->rss_indir_tbl[i] = indir[i];
1351 pad = bp->rss_indir_tbl_entries - tbl_size;
1352 if (pad)
1353 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1354 }
1355
1356 if (netif_running(bp->dev)) {
1357 bnxt_close_nic(bp, false, false);
1358 rc = bnxt_open_nic(bp, false, false);
1359 }
1360 return rc;
1361 }
1362
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1363 static void bnxt_get_drvinfo(struct net_device *dev,
1364 struct ethtool_drvinfo *info)
1365 {
1366 struct bnxt *bp = netdev_priv(dev);
1367
1368 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1369 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1370 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1371 info->n_stats = bnxt_get_num_stats(bp);
1372 info->testinfo_len = bp->num_tests;
1373 /* TODO CHIMP_FW: eeprom dump details */
1374 info->eedump_len = 0;
1375 /* TODO CHIMP FW: reg dump details */
1376 info->regdump_len = 0;
1377 }
1378
bnxt_get_regs_len(struct net_device * dev)1379 static int bnxt_get_regs_len(struct net_device *dev)
1380 {
1381 struct bnxt *bp = netdev_priv(dev);
1382 int reg_len;
1383
1384 if (!BNXT_PF(bp))
1385 return -EOPNOTSUPP;
1386
1387 reg_len = BNXT_PXP_REG_LEN;
1388
1389 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1390 reg_len += sizeof(struct pcie_ctx_hw_stats);
1391
1392 return reg_len;
1393 }
1394
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)1395 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1396 void *_p)
1397 {
1398 struct pcie_ctx_hw_stats *hw_pcie_stats;
1399 struct hwrm_pcie_qstats_input *req;
1400 struct bnxt *bp = netdev_priv(dev);
1401 dma_addr_t hw_pcie_stats_addr;
1402 int rc;
1403
1404 regs->version = 0;
1405 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1406
1407 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1408 return;
1409
1410 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
1411 return;
1412
1413 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
1414 &hw_pcie_stats_addr);
1415 if (!hw_pcie_stats) {
1416 hwrm_req_drop(bp, req);
1417 return;
1418 }
1419
1420 regs->version = 1;
1421 hwrm_req_hold(bp, req); /* hold on to slice */
1422 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1423 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1424 rc = hwrm_req_send(bp, req);
1425 if (!rc) {
1426 __le64 *src = (__le64 *)hw_pcie_stats;
1427 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1428 int i;
1429
1430 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1431 dst[i] = le64_to_cpu(src[i]);
1432 }
1433 hwrm_req_drop(bp, req);
1434 }
1435
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1436 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1437 {
1438 struct bnxt *bp = netdev_priv(dev);
1439
1440 wol->supported = 0;
1441 wol->wolopts = 0;
1442 memset(&wol->sopass, 0, sizeof(wol->sopass));
1443 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1444 wol->supported = WAKE_MAGIC;
1445 if (bp->wol)
1446 wol->wolopts = WAKE_MAGIC;
1447 }
1448 }
1449
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1450 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1451 {
1452 struct bnxt *bp = netdev_priv(dev);
1453
1454 if (wol->wolopts & ~WAKE_MAGIC)
1455 return -EINVAL;
1456
1457 if (wol->wolopts & WAKE_MAGIC) {
1458 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1459 return -EINVAL;
1460 if (!bp->wol) {
1461 if (bnxt_hwrm_alloc_wol_fltr(bp))
1462 return -EBUSY;
1463 bp->wol = 1;
1464 }
1465 } else {
1466 if (bp->wol) {
1467 if (bnxt_hwrm_free_wol_fltr(bp))
1468 return -EBUSY;
1469 bp->wol = 0;
1470 }
1471 }
1472 return 0;
1473 }
1474
_bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds,u8 fw_pause)1475 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1476 {
1477 u32 speed_mask = 0;
1478
1479 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1480 /* set the advertised speeds */
1481 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1482 speed_mask |= ADVERTISED_100baseT_Full;
1483 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1484 speed_mask |= ADVERTISED_1000baseT_Full;
1485 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1486 speed_mask |= ADVERTISED_2500baseX_Full;
1487 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1488 speed_mask |= ADVERTISED_10000baseT_Full;
1489 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1490 speed_mask |= ADVERTISED_40000baseCR4_Full;
1491
1492 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1493 speed_mask |= ADVERTISED_Pause;
1494 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1495 speed_mask |= ADVERTISED_Asym_Pause;
1496 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1497 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1498
1499 return speed_mask;
1500 }
1501
1502 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1503 { \
1504 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1505 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1506 100baseT_Full); \
1507 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1508 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1509 1000baseT_Full); \
1510 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1511 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1512 10000baseT_Full); \
1513 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1514 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1515 25000baseCR_Full); \
1516 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1517 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1518 40000baseCR4_Full);\
1519 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1521 50000baseCR2_Full);\
1522 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1524 100000baseCR4_Full);\
1525 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1527 Pause); \
1528 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1529 ethtool_link_ksettings_add_link_mode( \
1530 lk_ksettings, name, Asym_Pause);\
1531 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1532 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1533 Asym_Pause); \
1534 } \
1535 }
1536
1537 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1538 { \
1539 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1540 100baseT_Full) || \
1541 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1542 100baseT_Half)) \
1543 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1544 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1545 1000baseT_Full) || \
1546 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1547 1000baseT_Half)) \
1548 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1549 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1550 10000baseT_Full)) \
1551 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1552 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1553 25000baseCR_Full)) \
1554 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1555 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1556 40000baseCR4_Full)) \
1557 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1558 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1559 50000baseCR2_Full)) \
1560 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1561 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1562 100000baseCR4_Full)) \
1563 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1564 }
1565
1566 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1567 { \
1568 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1569 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1570 50000baseCR_Full); \
1571 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1572 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1573 100000baseCR2_Full);\
1574 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1575 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1576 200000baseCR4_Full);\
1577 }
1578
1579 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1580 { \
1581 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1582 50000baseCR_Full)) \
1583 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1584 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1585 100000baseCR2_Full)) \
1586 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1587 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1588 200000baseCR4_Full)) \
1589 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1590 }
1591
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1592 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1593 struct ethtool_link_ksettings *lk_ksettings)
1594 {
1595 u16 fec_cfg = link_info->fec_cfg;
1596
1597 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1598 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1599 lk_ksettings->link_modes.advertising);
1600 return;
1601 }
1602 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1603 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1604 lk_ksettings->link_modes.advertising);
1605 if (fec_cfg & BNXT_FEC_ENC_RS)
1606 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1607 lk_ksettings->link_modes.advertising);
1608 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1609 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1610 lk_ksettings->link_modes.advertising);
1611 }
1612
bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1613 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1614 struct ethtool_link_ksettings *lk_ksettings)
1615 {
1616 u16 fw_speeds = link_info->advertising;
1617 u8 fw_pause = 0;
1618
1619 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1620 fw_pause = link_info->auto_pause_setting;
1621
1622 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1623 fw_speeds = link_info->advertising_pam4;
1624 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1625 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1626 }
1627
bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1628 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1629 struct ethtool_link_ksettings *lk_ksettings)
1630 {
1631 u16 fw_speeds = link_info->lp_auto_link_speeds;
1632 u8 fw_pause = 0;
1633
1634 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1635 fw_pause = link_info->lp_pause;
1636
1637 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1638 lp_advertising);
1639 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1640 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1641 }
1642
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1643 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1644 struct ethtool_link_ksettings *lk_ksettings)
1645 {
1646 u16 fec_cfg = link_info->fec_cfg;
1647
1648 if (fec_cfg & BNXT_FEC_NONE) {
1649 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1650 lk_ksettings->link_modes.supported);
1651 return;
1652 }
1653 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1654 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1655 lk_ksettings->link_modes.supported);
1656 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1657 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1658 lk_ksettings->link_modes.supported);
1659 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1660 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1661 lk_ksettings->link_modes.supported);
1662 }
1663
bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1664 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1665 struct ethtool_link_ksettings *lk_ksettings)
1666 {
1667 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
1668 u16 fw_speeds = link_info->support_speeds;
1669
1670 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1671 fw_speeds = link_info->support_pam4_speeds;
1672 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1673
1674 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
1675 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1676 Pause);
1677 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1678 Asym_Pause);
1679 }
1680
1681 if (link_info->support_auto_speeds ||
1682 link_info->support_pam4_auto_speeds)
1683 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1684 Autoneg);
1685 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1686 }
1687
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)1688 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1689 {
1690 switch (fw_link_speed) {
1691 case BNXT_LINK_SPEED_100MB:
1692 return SPEED_100;
1693 case BNXT_LINK_SPEED_1GB:
1694 return SPEED_1000;
1695 case BNXT_LINK_SPEED_2_5GB:
1696 return SPEED_2500;
1697 case BNXT_LINK_SPEED_10GB:
1698 return SPEED_10000;
1699 case BNXT_LINK_SPEED_20GB:
1700 return SPEED_20000;
1701 case BNXT_LINK_SPEED_25GB:
1702 return SPEED_25000;
1703 case BNXT_LINK_SPEED_40GB:
1704 return SPEED_40000;
1705 case BNXT_LINK_SPEED_50GB:
1706 return SPEED_50000;
1707 case BNXT_LINK_SPEED_100GB:
1708 return SPEED_100000;
1709 case BNXT_LINK_SPEED_200GB:
1710 return SPEED_200000;
1711 default:
1712 return SPEED_UNKNOWN;
1713 }
1714 }
1715
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)1716 static int bnxt_get_link_ksettings(struct net_device *dev,
1717 struct ethtool_link_ksettings *lk_ksettings)
1718 {
1719 struct bnxt *bp = netdev_priv(dev);
1720 struct bnxt_link_info *link_info = &bp->link_info;
1721 struct ethtool_link_settings *base = &lk_ksettings->base;
1722 u32 ethtool_speed;
1723
1724 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1725 mutex_lock(&bp->link_lock);
1726 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1727
1728 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1729 if (link_info->autoneg) {
1730 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1731 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1732 advertising, Autoneg);
1733 base->autoneg = AUTONEG_ENABLE;
1734 base->duplex = DUPLEX_UNKNOWN;
1735 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1736 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1737 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1738 base->duplex = DUPLEX_FULL;
1739 else
1740 base->duplex = DUPLEX_HALF;
1741 }
1742 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1743 } else {
1744 base->autoneg = AUTONEG_DISABLE;
1745 ethtool_speed =
1746 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1747 base->duplex = DUPLEX_HALF;
1748 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1749 base->duplex = DUPLEX_FULL;
1750 }
1751 base->speed = ethtool_speed;
1752
1753 base->port = PORT_NONE;
1754 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1755 base->port = PORT_TP;
1756 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1757 TP);
1758 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1759 TP);
1760 } else {
1761 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1762 FIBRE);
1763 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1764 FIBRE);
1765
1766 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1767 base->port = PORT_DA;
1768 else if (link_info->media_type ==
1769 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1770 base->port = PORT_FIBRE;
1771 }
1772 base->phy_address = link_info->phy_addr;
1773 mutex_unlock(&bp->link_lock);
1774
1775 return 0;
1776 }
1777
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed)1778 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1779 {
1780 struct bnxt *bp = netdev_priv(dev);
1781 struct bnxt_link_info *link_info = &bp->link_info;
1782 u16 support_pam4_spds = link_info->support_pam4_speeds;
1783 u16 support_spds = link_info->support_speeds;
1784 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1785 u16 fw_speed = 0;
1786
1787 switch (ethtool_speed) {
1788 case SPEED_100:
1789 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1790 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1791 break;
1792 case SPEED_1000:
1793 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1794 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1795 break;
1796 case SPEED_2500:
1797 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1798 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1799 break;
1800 case SPEED_10000:
1801 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1802 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1803 break;
1804 case SPEED_20000:
1805 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1806 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1807 break;
1808 case SPEED_25000:
1809 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1810 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1811 break;
1812 case SPEED_40000:
1813 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1814 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1815 break;
1816 case SPEED_50000:
1817 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1818 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1819 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1820 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1821 sig_mode = BNXT_SIG_MODE_PAM4;
1822 }
1823 break;
1824 case SPEED_100000:
1825 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1826 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1827 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1828 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1829 sig_mode = BNXT_SIG_MODE_PAM4;
1830 }
1831 break;
1832 case SPEED_200000:
1833 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1834 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1835 sig_mode = BNXT_SIG_MODE_PAM4;
1836 }
1837 break;
1838 }
1839
1840 if (!fw_speed) {
1841 netdev_err(dev, "unsupported speed!\n");
1842 return -EINVAL;
1843 }
1844
1845 if (link_info->req_link_speed == fw_speed &&
1846 link_info->req_signal_mode == sig_mode &&
1847 link_info->autoneg == 0)
1848 return -EALREADY;
1849
1850 link_info->req_link_speed = fw_speed;
1851 link_info->req_signal_mode = sig_mode;
1852 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1853 link_info->autoneg = 0;
1854 link_info->advertising = 0;
1855 link_info->advertising_pam4 = 0;
1856
1857 return 0;
1858 }
1859
bnxt_get_fw_auto_link_speeds(u32 advertising)1860 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1861 {
1862 u16 fw_speed_mask = 0;
1863
1864 /* only support autoneg at speed 100, 1000, and 10000 */
1865 if (advertising & (ADVERTISED_100baseT_Full |
1866 ADVERTISED_100baseT_Half)) {
1867 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1868 }
1869 if (advertising & (ADVERTISED_1000baseT_Full |
1870 ADVERTISED_1000baseT_Half)) {
1871 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1872 }
1873 if (advertising & ADVERTISED_10000baseT_Full)
1874 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1875
1876 if (advertising & ADVERTISED_40000baseCR4_Full)
1877 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1878
1879 return fw_speed_mask;
1880 }
1881
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)1882 static int bnxt_set_link_ksettings(struct net_device *dev,
1883 const struct ethtool_link_ksettings *lk_ksettings)
1884 {
1885 struct bnxt *bp = netdev_priv(dev);
1886 struct bnxt_link_info *link_info = &bp->link_info;
1887 const struct ethtool_link_settings *base = &lk_ksettings->base;
1888 bool set_pause = false;
1889 u32 speed;
1890 int rc = 0;
1891
1892 if (!BNXT_PHY_CFG_ABLE(bp))
1893 return -EOPNOTSUPP;
1894
1895 mutex_lock(&bp->link_lock);
1896 if (base->autoneg == AUTONEG_ENABLE) {
1897 link_info->advertising = 0;
1898 link_info->advertising_pam4 = 0;
1899 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1900 advertising);
1901 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1902 lk_ksettings, advertising);
1903 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1904 if (!link_info->advertising && !link_info->advertising_pam4) {
1905 link_info->advertising = link_info->support_auto_speeds;
1906 link_info->advertising_pam4 =
1907 link_info->support_pam4_auto_speeds;
1908 }
1909 /* any change to autoneg will cause link change, therefore the
1910 * driver should put back the original pause setting in autoneg
1911 */
1912 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
1913 set_pause = true;
1914 } else {
1915 u8 phy_type = link_info->phy_type;
1916
1917 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1918 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1919 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1920 netdev_err(dev, "10GBase-T devices must autoneg\n");
1921 rc = -EINVAL;
1922 goto set_setting_exit;
1923 }
1924 if (base->duplex == DUPLEX_HALF) {
1925 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1926 rc = -EINVAL;
1927 goto set_setting_exit;
1928 }
1929 speed = base->speed;
1930 rc = bnxt_force_link_speed(dev, speed);
1931 if (rc) {
1932 if (rc == -EALREADY)
1933 rc = 0;
1934 goto set_setting_exit;
1935 }
1936 }
1937
1938 if (netif_running(dev))
1939 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1940
1941 set_setting_exit:
1942 mutex_unlock(&bp->link_lock);
1943 return rc;
1944 }
1945
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)1946 static int bnxt_get_fecparam(struct net_device *dev,
1947 struct ethtool_fecparam *fec)
1948 {
1949 struct bnxt *bp = netdev_priv(dev);
1950 struct bnxt_link_info *link_info;
1951 u8 active_fec;
1952 u16 fec_cfg;
1953
1954 link_info = &bp->link_info;
1955 fec_cfg = link_info->fec_cfg;
1956 active_fec = link_info->active_fec_sig_mode &
1957 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1958 if (fec_cfg & BNXT_FEC_NONE) {
1959 fec->fec = ETHTOOL_FEC_NONE;
1960 fec->active_fec = ETHTOOL_FEC_NONE;
1961 return 0;
1962 }
1963 if (fec_cfg & BNXT_FEC_AUTONEG)
1964 fec->fec |= ETHTOOL_FEC_AUTO;
1965 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1966 fec->fec |= ETHTOOL_FEC_BASER;
1967 if (fec_cfg & BNXT_FEC_ENC_RS)
1968 fec->fec |= ETHTOOL_FEC_RS;
1969 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1970 fec->fec |= ETHTOOL_FEC_LLRS;
1971
1972 switch (active_fec) {
1973 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
1974 fec->active_fec |= ETHTOOL_FEC_BASER;
1975 break;
1976 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
1977 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
1978 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
1979 fec->active_fec |= ETHTOOL_FEC_RS;
1980 break;
1981 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
1982 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
1983 fec->active_fec |= ETHTOOL_FEC_LLRS;
1984 break;
1985 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
1986 fec->active_fec |= ETHTOOL_FEC_OFF;
1987 break;
1988 }
1989 return 0;
1990 }
1991
bnxt_get_fec_stats(struct net_device * dev,struct ethtool_fec_stats * fec_stats)1992 static void bnxt_get_fec_stats(struct net_device *dev,
1993 struct ethtool_fec_stats *fec_stats)
1994 {
1995 struct bnxt *bp = netdev_priv(dev);
1996 u64 *rx;
1997
1998 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
1999 return;
2000
2001 rx = bp->rx_port_stats_ext.sw_stats;
2002 fec_stats->corrected_bits.total =
2003 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
2004 }
2005
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)2006 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
2007 u32 fec)
2008 {
2009 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
2010
2011 if (fec & ETHTOOL_FEC_BASER)
2012 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
2013 else if (fec & ETHTOOL_FEC_RS)
2014 fw_fec |= BNXT_FEC_RS_ON(link_info);
2015 else if (fec & ETHTOOL_FEC_LLRS)
2016 fw_fec |= BNXT_FEC_LLRS_ON;
2017 return fw_fec;
2018 }
2019
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)2020 static int bnxt_set_fecparam(struct net_device *dev,
2021 struct ethtool_fecparam *fecparam)
2022 {
2023 struct hwrm_port_phy_cfg_input *req;
2024 struct bnxt *bp = netdev_priv(dev);
2025 struct bnxt_link_info *link_info;
2026 u32 new_cfg, fec = fecparam->fec;
2027 u16 fec_cfg;
2028 int rc;
2029
2030 link_info = &bp->link_info;
2031 fec_cfg = link_info->fec_cfg;
2032 if (fec_cfg & BNXT_FEC_NONE)
2033 return -EOPNOTSUPP;
2034
2035 if (fec & ETHTOOL_FEC_OFF) {
2036 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
2037 BNXT_FEC_ALL_OFF(link_info);
2038 goto apply_fec;
2039 }
2040 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
2041 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
2042 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
2043 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
2044 return -EINVAL;
2045
2046 if (fec & ETHTOOL_FEC_AUTO) {
2047 if (!link_info->autoneg)
2048 return -EINVAL;
2049 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
2050 } else {
2051 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
2052 }
2053
2054 apply_fec:
2055 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
2056 if (rc)
2057 return rc;
2058 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
2059 rc = hwrm_req_send(bp, req);
2060 /* update current settings */
2061 if (!rc) {
2062 mutex_lock(&bp->link_lock);
2063 bnxt_update_link(bp, false);
2064 mutex_unlock(&bp->link_lock);
2065 }
2066 return rc;
2067 }
2068
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2069 static void bnxt_get_pauseparam(struct net_device *dev,
2070 struct ethtool_pauseparam *epause)
2071 {
2072 struct bnxt *bp = netdev_priv(dev);
2073 struct bnxt_link_info *link_info = &bp->link_info;
2074
2075 if (BNXT_VF(bp))
2076 return;
2077 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2078 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2079 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2080 }
2081
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)2082 static void bnxt_get_pause_stats(struct net_device *dev,
2083 struct ethtool_pause_stats *epstat)
2084 {
2085 struct bnxt *bp = netdev_priv(dev);
2086 u64 *rx, *tx;
2087
2088 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2089 return;
2090
2091 rx = bp->port_stats.sw_stats;
2092 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2093
2094 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2095 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2096 }
2097
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2098 static int bnxt_set_pauseparam(struct net_device *dev,
2099 struct ethtool_pauseparam *epause)
2100 {
2101 int rc = 0;
2102 struct bnxt *bp = netdev_priv(dev);
2103 struct bnxt_link_info *link_info = &bp->link_info;
2104
2105 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
2106 return -EOPNOTSUPP;
2107
2108 mutex_lock(&bp->link_lock);
2109 if (epause->autoneg) {
2110 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2111 rc = -EINVAL;
2112 goto pause_exit;
2113 }
2114
2115 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2116 link_info->req_flow_ctrl = 0;
2117 } else {
2118 /* when transition from auto pause to force pause,
2119 * force a link change
2120 */
2121 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2122 link_info->force_link_chng = true;
2123 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2124 link_info->req_flow_ctrl = 0;
2125 }
2126 if (epause->rx_pause)
2127 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2128
2129 if (epause->tx_pause)
2130 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2131
2132 if (netif_running(dev))
2133 rc = bnxt_hwrm_set_pause(bp);
2134
2135 pause_exit:
2136 mutex_unlock(&bp->link_lock);
2137 return rc;
2138 }
2139
bnxt_get_link(struct net_device * dev)2140 static u32 bnxt_get_link(struct net_device *dev)
2141 {
2142 struct bnxt *bp = netdev_priv(dev);
2143
2144 /* TODO: handle MF, VF, driver close case */
2145 return BNXT_LINK_IS_UP(bp);
2146 }
2147
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)2148 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2149 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2150 {
2151 struct hwrm_nvm_get_dev_info_output *resp;
2152 struct hwrm_nvm_get_dev_info_input *req;
2153 int rc;
2154
2155 if (BNXT_VF(bp))
2156 return -EOPNOTSUPP;
2157
2158 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
2159 if (rc)
2160 return rc;
2161
2162 resp = hwrm_req_hold(bp, req);
2163 rc = hwrm_req_send(bp, req);
2164 if (!rc)
2165 memcpy(nvm_dev_info, resp, sizeof(*resp));
2166 hwrm_req_drop(bp, req);
2167 return rc;
2168 }
2169
bnxt_print_admin_err(struct bnxt * bp)2170 static void bnxt_print_admin_err(struct bnxt *bp)
2171 {
2172 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2173 }
2174
2175 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2176 u16 ext, u16 *index, u32 *item_length,
2177 u32 *data_length);
2178
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,u32 dir_item_len,const u8 * data,size_t data_len)2179 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2180 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2181 u32 dir_item_len, const u8 *data,
2182 size_t data_len)
2183 {
2184 struct bnxt *bp = netdev_priv(dev);
2185 struct hwrm_nvm_write_input *req;
2186 int rc;
2187
2188 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
2189 if (rc)
2190 return rc;
2191
2192 if (data_len && data) {
2193 dma_addr_t dma_handle;
2194 u8 *kmem;
2195
2196 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
2197 if (!kmem) {
2198 hwrm_req_drop(bp, req);
2199 return -ENOMEM;
2200 }
2201
2202 req->dir_data_length = cpu_to_le32(data_len);
2203
2204 memcpy(kmem, data, data_len);
2205 req->host_src_addr = cpu_to_le64(dma_handle);
2206 }
2207
2208 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
2209 req->dir_type = cpu_to_le16(dir_type);
2210 req->dir_ordinal = cpu_to_le16(dir_ordinal);
2211 req->dir_ext = cpu_to_le16(dir_ext);
2212 req->dir_attr = cpu_to_le16(dir_attr);
2213 req->dir_item_length = cpu_to_le32(dir_item_len);
2214 rc = hwrm_req_send(bp, req);
2215
2216 if (rc == -EACCES)
2217 bnxt_print_admin_err(bp);
2218 return rc;
2219 }
2220
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)2221 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2222 u8 self_reset, u8 flags)
2223 {
2224 struct bnxt *bp = netdev_priv(dev);
2225 struct hwrm_fw_reset_input *req;
2226 int rc;
2227
2228 if (!bnxt_hwrm_reset_permitted(bp)) {
2229 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
2230 return -EPERM;
2231 }
2232
2233 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
2234 if (rc)
2235 return rc;
2236
2237 req->embedded_proc_type = proc_type;
2238 req->selfrst_status = self_reset;
2239 req->flags = flags;
2240
2241 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2242 rc = hwrm_req_send_silent(bp, req);
2243 } else {
2244 rc = hwrm_req_send(bp, req);
2245 if (rc == -EACCES)
2246 bnxt_print_admin_err(bp);
2247 }
2248 return rc;
2249 }
2250
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)2251 static int bnxt_firmware_reset(struct net_device *dev,
2252 enum bnxt_nvm_directory_type dir_type)
2253 {
2254 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2255 u8 proc_type, flags = 0;
2256
2257 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
2258 /* (e.g. when firmware isn't already running) */
2259 switch (dir_type) {
2260 case BNX_DIR_TYPE_CHIMP_PATCH:
2261 case BNX_DIR_TYPE_BOOTCODE:
2262 case BNX_DIR_TYPE_BOOTCODE_2:
2263 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2264 /* Self-reset ChiMP upon next PCIe reset: */
2265 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2266 break;
2267 case BNX_DIR_TYPE_APE_FW:
2268 case BNX_DIR_TYPE_APE_PATCH:
2269 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2270 /* Self-reset APE upon next PCIe reset: */
2271 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2272 break;
2273 case BNX_DIR_TYPE_KONG_FW:
2274 case BNX_DIR_TYPE_KONG_PATCH:
2275 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2276 break;
2277 case BNX_DIR_TYPE_BONO_FW:
2278 case BNX_DIR_TYPE_BONO_PATCH:
2279 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2280 break;
2281 default:
2282 return -EINVAL;
2283 }
2284
2285 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2286 }
2287
bnxt_firmware_reset_chip(struct net_device * dev)2288 static int bnxt_firmware_reset_chip(struct net_device *dev)
2289 {
2290 struct bnxt *bp = netdev_priv(dev);
2291 u8 flags = 0;
2292
2293 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2294 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2295
2296 return bnxt_hwrm_firmware_reset(dev,
2297 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2298 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2299 flags);
2300 }
2301
bnxt_firmware_reset_ap(struct net_device * dev)2302 static int bnxt_firmware_reset_ap(struct net_device *dev)
2303 {
2304 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2305 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2306 0);
2307 }
2308
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2309 static int bnxt_flash_firmware(struct net_device *dev,
2310 u16 dir_type,
2311 const u8 *fw_data,
2312 size_t fw_size)
2313 {
2314 int rc = 0;
2315 u16 code_type;
2316 u32 stored_crc;
2317 u32 calculated_crc;
2318 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2319
2320 switch (dir_type) {
2321 case BNX_DIR_TYPE_BOOTCODE:
2322 case BNX_DIR_TYPE_BOOTCODE_2:
2323 code_type = CODE_BOOT;
2324 break;
2325 case BNX_DIR_TYPE_CHIMP_PATCH:
2326 code_type = CODE_CHIMP_PATCH;
2327 break;
2328 case BNX_DIR_TYPE_APE_FW:
2329 code_type = CODE_MCTP_PASSTHRU;
2330 break;
2331 case BNX_DIR_TYPE_APE_PATCH:
2332 code_type = CODE_APE_PATCH;
2333 break;
2334 case BNX_DIR_TYPE_KONG_FW:
2335 code_type = CODE_KONG_FW;
2336 break;
2337 case BNX_DIR_TYPE_KONG_PATCH:
2338 code_type = CODE_KONG_PATCH;
2339 break;
2340 case BNX_DIR_TYPE_BONO_FW:
2341 code_type = CODE_BONO_FW;
2342 break;
2343 case BNX_DIR_TYPE_BONO_PATCH:
2344 code_type = CODE_BONO_PATCH;
2345 break;
2346 default:
2347 netdev_err(dev, "Unsupported directory entry type: %u\n",
2348 dir_type);
2349 return -EINVAL;
2350 }
2351 if (fw_size < sizeof(struct bnxt_fw_header)) {
2352 netdev_err(dev, "Invalid firmware file size: %u\n",
2353 (unsigned int)fw_size);
2354 return -EINVAL;
2355 }
2356 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2357 netdev_err(dev, "Invalid firmware signature: %08X\n",
2358 le32_to_cpu(header->signature));
2359 return -EINVAL;
2360 }
2361 if (header->code_type != code_type) {
2362 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2363 code_type, header->code_type);
2364 return -EINVAL;
2365 }
2366 if (header->device != DEVICE_CUMULUS_FAMILY) {
2367 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2368 DEVICE_CUMULUS_FAMILY, header->device);
2369 return -EINVAL;
2370 }
2371 /* Confirm the CRC32 checksum of the file: */
2372 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2373 sizeof(stored_crc)));
2374 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2375 if (calculated_crc != stored_crc) {
2376 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2377 (unsigned long)stored_crc,
2378 (unsigned long)calculated_crc);
2379 return -EINVAL;
2380 }
2381 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2382 0, 0, 0, fw_data, fw_size);
2383 if (rc == 0) /* Firmware update successful */
2384 rc = bnxt_firmware_reset(dev, dir_type);
2385
2386 return rc;
2387 }
2388
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2389 static int bnxt_flash_microcode(struct net_device *dev,
2390 u16 dir_type,
2391 const u8 *fw_data,
2392 size_t fw_size)
2393 {
2394 struct bnxt_ucode_trailer *trailer;
2395 u32 calculated_crc;
2396 u32 stored_crc;
2397 int rc = 0;
2398
2399 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2400 netdev_err(dev, "Invalid microcode file size: %u\n",
2401 (unsigned int)fw_size);
2402 return -EINVAL;
2403 }
2404 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2405 sizeof(*trailer)));
2406 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2407 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2408 le32_to_cpu(trailer->sig));
2409 return -EINVAL;
2410 }
2411 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2412 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2413 dir_type, le16_to_cpu(trailer->dir_type));
2414 return -EINVAL;
2415 }
2416 if (le16_to_cpu(trailer->trailer_length) <
2417 sizeof(struct bnxt_ucode_trailer)) {
2418 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2419 le16_to_cpu(trailer->trailer_length));
2420 return -EINVAL;
2421 }
2422
2423 /* Confirm the CRC32 checksum of the file: */
2424 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2425 sizeof(stored_crc)));
2426 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2427 if (calculated_crc != stored_crc) {
2428 netdev_err(dev,
2429 "CRC32 (%08lX) does not match calculated: %08lX\n",
2430 (unsigned long)stored_crc,
2431 (unsigned long)calculated_crc);
2432 return -EINVAL;
2433 }
2434 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2435 0, 0, 0, fw_data, fw_size);
2436
2437 return rc;
2438 }
2439
bnxt_dir_type_is_ape_bin_format(u16 dir_type)2440 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2441 {
2442 switch (dir_type) {
2443 case BNX_DIR_TYPE_CHIMP_PATCH:
2444 case BNX_DIR_TYPE_BOOTCODE:
2445 case BNX_DIR_TYPE_BOOTCODE_2:
2446 case BNX_DIR_TYPE_APE_FW:
2447 case BNX_DIR_TYPE_APE_PATCH:
2448 case BNX_DIR_TYPE_KONG_FW:
2449 case BNX_DIR_TYPE_KONG_PATCH:
2450 case BNX_DIR_TYPE_BONO_FW:
2451 case BNX_DIR_TYPE_BONO_PATCH:
2452 return true;
2453 }
2454
2455 return false;
2456 }
2457
bnxt_dir_type_is_other_exec_format(u16 dir_type)2458 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2459 {
2460 switch (dir_type) {
2461 case BNX_DIR_TYPE_AVS:
2462 case BNX_DIR_TYPE_EXP_ROM_MBA:
2463 case BNX_DIR_TYPE_PCIE:
2464 case BNX_DIR_TYPE_TSCF_UCODE:
2465 case BNX_DIR_TYPE_EXT_PHY:
2466 case BNX_DIR_TYPE_CCM:
2467 case BNX_DIR_TYPE_ISCSI_BOOT:
2468 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2469 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2470 return true;
2471 }
2472
2473 return false;
2474 }
2475
bnxt_dir_type_is_executable(u16 dir_type)2476 static bool bnxt_dir_type_is_executable(u16 dir_type)
2477 {
2478 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2479 bnxt_dir_type_is_other_exec_format(dir_type);
2480 }
2481
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)2482 static int bnxt_flash_firmware_from_file(struct net_device *dev,
2483 u16 dir_type,
2484 const char *filename)
2485 {
2486 const struct firmware *fw;
2487 int rc;
2488
2489 rc = request_firmware(&fw, filename, &dev->dev);
2490 if (rc != 0) {
2491 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2492 rc, filename);
2493 return rc;
2494 }
2495 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2496 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2497 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2498 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2499 else
2500 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2501 0, 0, 0, fw->data, fw->size);
2502 release_firmware(fw);
2503 return rc;
2504 }
2505
2506 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
2507 #define MSG_INVALID_PKG "PKG install error : Invalid package"
2508 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
2509 #define MSG_INVALID_DEV "PKG install error : Invalid device"
2510 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
2511 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
2512 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
2513 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
2514 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
2515
nvm_update_err_to_stderr(struct net_device * dev,u8 result,struct netlink_ext_ack * extack)2516 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
2517 struct netlink_ext_ack *extack)
2518 {
2519 switch (result) {
2520 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
2521 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
2522 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
2523 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
2524 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
2525 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
2526 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
2527 return -EINVAL;
2528 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
2529 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
2530 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
2531 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
2532 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
2533 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
2534 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
2535 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
2536 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
2537 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
2538 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
2539 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
2540 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
2541 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
2542 return -ENOPKG;
2543 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
2544 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
2545 return -EPERM;
2546 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
2547 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
2548 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
2549 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
2550 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
2551 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
2552 return -EOPNOTSUPP;
2553 default:
2554 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
2555 return -EIO;
2556 }
2557 }
2558
2559 #define BNXT_PKG_DMA_SIZE 0x40000
2560 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
2561 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
2562
bnxt_flash_package_from_fw_obj(struct net_device * dev,const struct firmware * fw,u32 install_type,struct netlink_ext_ack * extack)2563 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
2564 u32 install_type, struct netlink_ext_ack *extack)
2565 {
2566 struct hwrm_nvm_install_update_input *install;
2567 struct hwrm_nvm_install_update_output *resp;
2568 struct hwrm_nvm_modify_input *modify;
2569 struct bnxt *bp = netdev_priv(dev);
2570 bool defrag_attempted = false;
2571 dma_addr_t dma_handle;
2572 u8 *kmem = NULL;
2573 u32 modify_len;
2574 u32 item_len;
2575 u8 cmd_err;
2576 u16 index;
2577 int rc;
2578
2579 bnxt_hwrm_fw_set_time(bp);
2580
2581 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
2582 if (rc)
2583 return rc;
2584
2585 /* Try allocating a large DMA buffer first. Older fw will
2586 * cause excessive NVRAM erases when using small blocks.
2587 */
2588 modify_len = roundup_pow_of_two(fw->size);
2589 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
2590 while (1) {
2591 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
2592 if (!kmem && modify_len > PAGE_SIZE)
2593 modify_len /= 2;
2594 else
2595 break;
2596 }
2597 if (!kmem) {
2598 hwrm_req_drop(bp, modify);
2599 return -ENOMEM;
2600 }
2601
2602 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
2603 if (rc) {
2604 hwrm_req_drop(bp, modify);
2605 return rc;
2606 }
2607
2608 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
2609 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
2610
2611 hwrm_req_hold(bp, modify);
2612 modify->host_src_addr = cpu_to_le64(dma_handle);
2613
2614 resp = hwrm_req_hold(bp, install);
2615 if ((install_type & 0xffff) == 0)
2616 install_type >>= 16;
2617 install->install_type = cpu_to_le32(install_type);
2618
2619 do {
2620 u32 copied = 0, len = modify_len;
2621
2622 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2623 BNX_DIR_ORDINAL_FIRST,
2624 BNX_DIR_EXT_NONE,
2625 &index, &item_len, NULL);
2626 if (rc) {
2627 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
2628 break;
2629 }
2630 if (fw->size > item_len) {
2631 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
2632 rc = -EFBIG;
2633 break;
2634 }
2635
2636 modify->dir_idx = cpu_to_le16(index);
2637
2638 if (fw->size > modify_len)
2639 modify->flags = BNXT_NVM_MORE_FLAG;
2640 while (copied < fw->size) {
2641 u32 balance = fw->size - copied;
2642
2643 if (balance <= modify_len) {
2644 len = balance;
2645 if (copied)
2646 modify->flags |= BNXT_NVM_LAST_FLAG;
2647 }
2648 memcpy(kmem, fw->data + copied, len);
2649 modify->len = cpu_to_le32(len);
2650 modify->offset = cpu_to_le32(copied);
2651 rc = hwrm_req_send(bp, modify);
2652 if (rc)
2653 goto pkg_abort;
2654 copied += len;
2655 }
2656
2657 rc = hwrm_req_send_silent(bp, install);
2658 if (!rc)
2659 break;
2660
2661 if (defrag_attempted) {
2662 /* We have tried to defragment already in the previous
2663 * iteration. Return with the result for INSTALL_UPDATE
2664 */
2665 break;
2666 }
2667
2668 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2669
2670 switch (cmd_err) {
2671 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
2672 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
2673 rc = -EALREADY;
2674 break;
2675 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
2676 install->flags =
2677 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2678
2679 rc = hwrm_req_send_silent(bp, install);
2680 if (!rc)
2681 break;
2682
2683 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2684
2685 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
2686 /* FW has cleared NVM area, driver will create
2687 * UPDATE directory and try the flash again
2688 */
2689 defrag_attempted = true;
2690 install->flags = 0;
2691 rc = bnxt_flash_nvram(bp->dev,
2692 BNX_DIR_TYPE_UPDATE,
2693 BNX_DIR_ORDINAL_FIRST,
2694 0, 0, item_len, NULL, 0);
2695 if (!rc)
2696 break;
2697 }
2698 fallthrough;
2699 default:
2700 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
2701 }
2702 } while (defrag_attempted && !rc);
2703
2704 pkg_abort:
2705 hwrm_req_drop(bp, modify);
2706 hwrm_req_drop(bp, install);
2707
2708 if (resp->result) {
2709 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2710 (s8)resp->result, (int)resp->problem_item);
2711 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
2712 }
2713 if (rc == -EACCES)
2714 bnxt_print_admin_err(bp);
2715 return rc;
2716 }
2717
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type,struct netlink_ext_ack * extack)2718 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2719 u32 install_type, struct netlink_ext_ack *extack)
2720 {
2721 const struct firmware *fw;
2722 int rc;
2723
2724 rc = request_firmware(&fw, filename, &dev->dev);
2725 if (rc != 0) {
2726 netdev_err(dev, "PKG error %d requesting file: %s\n",
2727 rc, filename);
2728 return rc;
2729 }
2730
2731 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
2732
2733 release_firmware(fw);
2734
2735 return rc;
2736 }
2737
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)2738 static int bnxt_flash_device(struct net_device *dev,
2739 struct ethtool_flash *flash)
2740 {
2741 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2742 netdev_err(dev, "flashdev not supported from a virtual function\n");
2743 return -EINVAL;
2744 }
2745
2746 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2747 flash->region > 0xffff)
2748 return bnxt_flash_package_from_file(dev, flash->data,
2749 flash->region, NULL);
2750
2751 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2752 }
2753
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)2754 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2755 {
2756 struct hwrm_nvm_get_dir_info_output *output;
2757 struct hwrm_nvm_get_dir_info_input *req;
2758 struct bnxt *bp = netdev_priv(dev);
2759 int rc;
2760
2761 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
2762 if (rc)
2763 return rc;
2764
2765 output = hwrm_req_hold(bp, req);
2766 rc = hwrm_req_send(bp, req);
2767 if (!rc) {
2768 *entries = le32_to_cpu(output->entries);
2769 *length = le32_to_cpu(output->entry_length);
2770 }
2771 hwrm_req_drop(bp, req);
2772 return rc;
2773 }
2774
bnxt_get_eeprom_len(struct net_device * dev)2775 static int bnxt_get_eeprom_len(struct net_device *dev)
2776 {
2777 struct bnxt *bp = netdev_priv(dev);
2778
2779 if (BNXT_VF(bp))
2780 return 0;
2781
2782 /* The -1 return value allows the entire 32-bit range of offsets to be
2783 * passed via the ethtool command-line utility.
2784 */
2785 return -1;
2786 }
2787
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)2788 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2789 {
2790 struct bnxt *bp = netdev_priv(dev);
2791 int rc;
2792 u32 dir_entries;
2793 u32 entry_length;
2794 u8 *buf;
2795 size_t buflen;
2796 dma_addr_t dma_handle;
2797 struct hwrm_nvm_get_dir_entries_input *req;
2798
2799 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2800 if (rc != 0)
2801 return rc;
2802
2803 if (!dir_entries || !entry_length)
2804 return -EIO;
2805
2806 /* Insert 2 bytes of directory info (count and size of entries) */
2807 if (len < 2)
2808 return -EINVAL;
2809
2810 *data++ = dir_entries;
2811 *data++ = entry_length;
2812 len -= 2;
2813 memset(data, 0xff, len);
2814
2815 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
2816 if (rc)
2817 return rc;
2818
2819 buflen = mul_u32_u32(dir_entries, entry_length);
2820 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
2821 if (!buf) {
2822 hwrm_req_drop(bp, req);
2823 return -ENOMEM;
2824 }
2825 req->host_dest_addr = cpu_to_le64(dma_handle);
2826
2827 hwrm_req_hold(bp, req); /* hold the slice */
2828 rc = hwrm_req_send(bp, req);
2829 if (rc == 0)
2830 memcpy(data, buf, len > buflen ? buflen : len);
2831 hwrm_req_drop(bp, req);
2832 return rc;
2833 }
2834
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)2835 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2836 u32 length, u8 *data)
2837 {
2838 struct bnxt *bp = netdev_priv(dev);
2839 int rc;
2840 u8 *buf;
2841 dma_addr_t dma_handle;
2842 struct hwrm_nvm_read_input *req;
2843
2844 if (!length)
2845 return -EINVAL;
2846
2847 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
2848 if (rc)
2849 return rc;
2850
2851 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
2852 if (!buf) {
2853 hwrm_req_drop(bp, req);
2854 return -ENOMEM;
2855 }
2856
2857 req->host_dest_addr = cpu_to_le64(dma_handle);
2858 req->dir_idx = cpu_to_le16(index);
2859 req->offset = cpu_to_le32(offset);
2860 req->len = cpu_to_le32(length);
2861
2862 hwrm_req_hold(bp, req); /* hold the slice */
2863 rc = hwrm_req_send(bp, req);
2864 if (rc == 0)
2865 memcpy(data, buf, length);
2866 hwrm_req_drop(bp, req);
2867 return rc;
2868 }
2869
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)2870 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2871 u16 ext, u16 *index, u32 *item_length,
2872 u32 *data_length)
2873 {
2874 struct hwrm_nvm_find_dir_entry_output *output;
2875 struct hwrm_nvm_find_dir_entry_input *req;
2876 struct bnxt *bp = netdev_priv(dev);
2877 int rc;
2878
2879 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
2880 if (rc)
2881 return rc;
2882
2883 req->enables = 0;
2884 req->dir_idx = 0;
2885 req->dir_type = cpu_to_le16(type);
2886 req->dir_ordinal = cpu_to_le16(ordinal);
2887 req->dir_ext = cpu_to_le16(ext);
2888 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2889 output = hwrm_req_hold(bp, req);
2890 rc = hwrm_req_send_silent(bp, req);
2891 if (rc == 0) {
2892 if (index)
2893 *index = le16_to_cpu(output->dir_idx);
2894 if (item_length)
2895 *item_length = le32_to_cpu(output->dir_item_length);
2896 if (data_length)
2897 *data_length = le32_to_cpu(output->dir_data_length);
2898 }
2899 hwrm_req_drop(bp, req);
2900 return rc;
2901 }
2902
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)2903 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2904 {
2905 char *retval = NULL;
2906 char *p;
2907 char *value;
2908 int field = 0;
2909
2910 if (datalen < 1)
2911 return NULL;
2912 /* null-terminate the log data (removing last '\n'): */
2913 data[datalen - 1] = 0;
2914 for (p = data; *p != 0; p++) {
2915 field = 0;
2916 retval = NULL;
2917 while (*p != 0 && *p != '\n') {
2918 value = p;
2919 while (*p != 0 && *p != '\t' && *p != '\n')
2920 p++;
2921 if (field == desired_field)
2922 retval = value;
2923 if (*p != '\t')
2924 break;
2925 *p = 0;
2926 field++;
2927 p++;
2928 }
2929 if (*p == 0)
2930 break;
2931 *p = 0;
2932 }
2933 return retval;
2934 }
2935
bnxt_get_pkginfo(struct net_device * dev,char * ver,int size)2936 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
2937 {
2938 struct bnxt *bp = netdev_priv(dev);
2939 u16 index = 0;
2940 char *pkgver;
2941 u32 pkglen;
2942 u8 *pkgbuf;
2943 int rc;
2944
2945 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2946 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2947 &index, NULL, &pkglen);
2948 if (rc)
2949 return rc;
2950
2951 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2952 if (!pkgbuf) {
2953 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2954 pkglen);
2955 return -ENOMEM;
2956 }
2957
2958 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
2959 if (rc)
2960 goto err;
2961
2962 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2963 pkglen);
2964 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
2965 strscpy(ver, pkgver, size);
2966 else
2967 rc = -ENOENT;
2968
2969 err:
2970 kfree(pkgbuf);
2971
2972 return rc;
2973 }
2974
bnxt_get_pkgver(struct net_device * dev)2975 static void bnxt_get_pkgver(struct net_device *dev)
2976 {
2977 struct bnxt *bp = netdev_priv(dev);
2978 char buf[FW_VER_STR_LEN];
2979 int len;
2980
2981 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
2982 len = strlen(bp->fw_ver_str);
2983 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2984 "/pkg %s", buf);
2985 }
2986 }
2987
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2988 static int bnxt_get_eeprom(struct net_device *dev,
2989 struct ethtool_eeprom *eeprom,
2990 u8 *data)
2991 {
2992 u32 index;
2993 u32 offset;
2994
2995 if (eeprom->offset == 0) /* special offset value to get directory */
2996 return bnxt_get_nvram_directory(dev, eeprom->len, data);
2997
2998 index = eeprom->offset >> 24;
2999 offset = eeprom->offset & 0xffffff;
3000
3001 if (index == 0) {
3002 netdev_err(dev, "unsupported index value: %d\n", index);
3003 return -EINVAL;
3004 }
3005
3006 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
3007 }
3008
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)3009 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
3010 {
3011 struct hwrm_nvm_erase_dir_entry_input *req;
3012 struct bnxt *bp = netdev_priv(dev);
3013 int rc;
3014
3015 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
3016 if (rc)
3017 return rc;
3018
3019 req->dir_idx = cpu_to_le16(index);
3020 return hwrm_req_send(bp, req);
3021 }
3022
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3023 static int bnxt_set_eeprom(struct net_device *dev,
3024 struct ethtool_eeprom *eeprom,
3025 u8 *data)
3026 {
3027 struct bnxt *bp = netdev_priv(dev);
3028 u8 index, dir_op;
3029 u16 type, ext, ordinal, attr;
3030
3031 if (!BNXT_PF(bp)) {
3032 netdev_err(dev, "NVM write not supported from a virtual function\n");
3033 return -EINVAL;
3034 }
3035
3036 type = eeprom->magic >> 16;
3037
3038 if (type == 0xffff) { /* special value for directory operations */
3039 index = eeprom->magic & 0xff;
3040 dir_op = eeprom->magic >> 8;
3041 if (index == 0)
3042 return -EINVAL;
3043 switch (dir_op) {
3044 case 0x0e: /* erase */
3045 if (eeprom->offset != ~eeprom->magic)
3046 return -EINVAL;
3047 return bnxt_erase_nvram_directory(dev, index - 1);
3048 default:
3049 return -EINVAL;
3050 }
3051 }
3052
3053 /* Create or re-write an NVM item: */
3054 if (bnxt_dir_type_is_executable(type))
3055 return -EOPNOTSUPP;
3056 ext = eeprom->magic & 0xffff;
3057 ordinal = eeprom->offset >> 16;
3058 attr = eeprom->offset & 0xffff;
3059
3060 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
3061 eeprom->len);
3062 }
3063
bnxt_set_eee(struct net_device * dev,struct ethtool_eee * edata)3064 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
3065 {
3066 struct bnxt *bp = netdev_priv(dev);
3067 struct ethtool_eee *eee = &bp->eee;
3068 struct bnxt_link_info *link_info = &bp->link_info;
3069 u32 advertising;
3070 int rc = 0;
3071
3072 if (!BNXT_PHY_CFG_ABLE(bp))
3073 return -EOPNOTSUPP;
3074
3075 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3076 return -EOPNOTSUPP;
3077
3078 mutex_lock(&bp->link_lock);
3079 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
3080 if (!edata->eee_enabled)
3081 goto eee_ok;
3082
3083 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3084 netdev_warn(dev, "EEE requires autoneg\n");
3085 rc = -EINVAL;
3086 goto eee_exit;
3087 }
3088 if (edata->tx_lpi_enabled) {
3089 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
3090 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
3091 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
3092 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
3093 rc = -EINVAL;
3094 goto eee_exit;
3095 } else if (!bp->lpi_tmr_hi) {
3096 edata->tx_lpi_timer = eee->tx_lpi_timer;
3097 }
3098 }
3099 if (!edata->advertised) {
3100 edata->advertised = advertising & eee->supported;
3101 } else if (edata->advertised & ~advertising) {
3102 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
3103 edata->advertised, advertising);
3104 rc = -EINVAL;
3105 goto eee_exit;
3106 }
3107
3108 eee->advertised = edata->advertised;
3109 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
3110 eee->tx_lpi_timer = edata->tx_lpi_timer;
3111 eee_ok:
3112 eee->eee_enabled = edata->eee_enabled;
3113
3114 if (netif_running(dev))
3115 rc = bnxt_hwrm_set_link_setting(bp, false, true);
3116
3117 eee_exit:
3118 mutex_unlock(&bp->link_lock);
3119 return rc;
3120 }
3121
bnxt_get_eee(struct net_device * dev,struct ethtool_eee * edata)3122 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
3123 {
3124 struct bnxt *bp = netdev_priv(dev);
3125
3126 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3127 return -EOPNOTSUPP;
3128
3129 *edata = bp->eee;
3130 if (!bp->eee.eee_enabled) {
3131 /* Preserve tx_lpi_timer so that the last value will be used
3132 * by default when it is re-enabled.
3133 */
3134 edata->advertised = 0;
3135 edata->tx_lpi_enabled = 0;
3136 }
3137
3138 if (!bp->eee.eee_active)
3139 edata->lp_advertised = 0;
3140
3141 return 0;
3142 }
3143
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u16 start_addr,u16 data_length,u8 * buf)3144 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
3145 u16 page_number, u16 start_addr,
3146 u16 data_length, u8 *buf)
3147 {
3148 struct hwrm_port_phy_i2c_read_output *output;
3149 struct hwrm_port_phy_i2c_read_input *req;
3150 int rc, byte_offset = 0;
3151
3152 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
3153 if (rc)
3154 return rc;
3155
3156 output = hwrm_req_hold(bp, req);
3157 req->i2c_slave_addr = i2c_addr;
3158 req->page_number = cpu_to_le16(page_number);
3159 req->port_id = cpu_to_le16(bp->pf.port_id);
3160 do {
3161 u16 xfer_size;
3162
3163 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
3164 data_length -= xfer_size;
3165 req->page_offset = cpu_to_le16(start_addr + byte_offset);
3166 req->data_length = xfer_size;
3167 req->enables = cpu_to_le32(start_addr + byte_offset ?
3168 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
3169 rc = hwrm_req_send(bp, req);
3170 if (!rc)
3171 memcpy(buf + byte_offset, output->data, xfer_size);
3172 byte_offset += xfer_size;
3173 } while (!rc && data_length > 0);
3174 hwrm_req_drop(bp, req);
3175
3176 return rc;
3177 }
3178
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)3179 static int bnxt_get_module_info(struct net_device *dev,
3180 struct ethtool_modinfo *modinfo)
3181 {
3182 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
3183 struct bnxt *bp = netdev_priv(dev);
3184 int rc;
3185
3186 /* No point in going further if phy status indicates
3187 * module is not inserted or if it is powered down or
3188 * if it is of type 10GBase-T
3189 */
3190 if (bp->link_info.module_status >
3191 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
3192 return -EOPNOTSUPP;
3193
3194 /* This feature is not supported in older firmware versions */
3195 if (bp->hwrm_spec_code < 0x10202)
3196 return -EOPNOTSUPP;
3197
3198 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3199 SFF_DIAG_SUPPORT_OFFSET + 1,
3200 data);
3201 if (!rc) {
3202 u8 module_id = data[0];
3203 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
3204
3205 switch (module_id) {
3206 case SFF_MODULE_ID_SFP:
3207 modinfo->type = ETH_MODULE_SFF_8472;
3208 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3209 if (!diag_supported)
3210 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3211 break;
3212 case SFF_MODULE_ID_QSFP:
3213 case SFF_MODULE_ID_QSFP_PLUS:
3214 modinfo->type = ETH_MODULE_SFF_8436;
3215 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3216 break;
3217 case SFF_MODULE_ID_QSFP28:
3218 modinfo->type = ETH_MODULE_SFF_8636;
3219 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
3220 break;
3221 default:
3222 rc = -EOPNOTSUPP;
3223 break;
3224 }
3225 }
3226 return rc;
3227 }
3228
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3229 static int bnxt_get_module_eeprom(struct net_device *dev,
3230 struct ethtool_eeprom *eeprom,
3231 u8 *data)
3232 {
3233 struct bnxt *bp = netdev_priv(dev);
3234 u16 start = eeprom->offset, length = eeprom->len;
3235 int rc = 0;
3236
3237 memset(data, 0, eeprom->len);
3238
3239 /* Read A0 portion of the EEPROM */
3240 if (start < ETH_MODULE_SFF_8436_LEN) {
3241 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
3242 length = ETH_MODULE_SFF_8436_LEN - start;
3243 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3244 start, length, data);
3245 if (rc)
3246 return rc;
3247 start += length;
3248 data += length;
3249 length = eeprom->len - length;
3250 }
3251
3252 /* Read A2 portion of the EEPROM */
3253 if (length) {
3254 start -= ETH_MODULE_SFF_8436_LEN;
3255 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0,
3256 start, length, data);
3257 }
3258 return rc;
3259 }
3260
bnxt_nway_reset(struct net_device * dev)3261 static int bnxt_nway_reset(struct net_device *dev)
3262 {
3263 int rc = 0;
3264
3265 struct bnxt *bp = netdev_priv(dev);
3266 struct bnxt_link_info *link_info = &bp->link_info;
3267
3268 if (!BNXT_PHY_CFG_ABLE(bp))
3269 return -EOPNOTSUPP;
3270
3271 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3272 return -EINVAL;
3273
3274 if (netif_running(dev))
3275 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3276
3277 return rc;
3278 }
3279
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)3280 static int bnxt_set_phys_id(struct net_device *dev,
3281 enum ethtool_phys_id_state state)
3282 {
3283 struct hwrm_port_led_cfg_input *req;
3284 struct bnxt *bp = netdev_priv(dev);
3285 struct bnxt_pf_info *pf = &bp->pf;
3286 struct bnxt_led_cfg *led_cfg;
3287 u8 led_state;
3288 __le16 duration;
3289 int rc, i;
3290
3291 if (!bp->num_leds || BNXT_VF(bp))
3292 return -EOPNOTSUPP;
3293
3294 if (state == ETHTOOL_ID_ACTIVE) {
3295 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3296 duration = cpu_to_le16(500);
3297 } else if (state == ETHTOOL_ID_INACTIVE) {
3298 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3299 duration = cpu_to_le16(0);
3300 } else {
3301 return -EINVAL;
3302 }
3303 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
3304 if (rc)
3305 return rc;
3306
3307 req->port_id = cpu_to_le16(pf->port_id);
3308 req->num_leds = bp->num_leds;
3309 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
3310 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3311 req->enables |= BNXT_LED_DFLT_ENABLES(i);
3312 led_cfg->led_id = bp->leds[i].led_id;
3313 led_cfg->led_state = led_state;
3314 led_cfg->led_blink_on = duration;
3315 led_cfg->led_blink_off = duration;
3316 led_cfg->led_group_id = bp->leds[i].led_group_id;
3317 }
3318 return hwrm_req_send(bp, req);
3319 }
3320
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)3321 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3322 {
3323 struct hwrm_selftest_irq_input *req;
3324 int rc;
3325
3326 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
3327 if (rc)
3328 return rc;
3329
3330 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3331 return hwrm_req_send(bp, req);
3332 }
3333
bnxt_test_irq(struct bnxt * bp)3334 static int bnxt_test_irq(struct bnxt *bp)
3335 {
3336 int i;
3337
3338 for (i = 0; i < bp->cp_nr_rings; i++) {
3339 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3340 int rc;
3341
3342 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3343 if (rc)
3344 return rc;
3345 }
3346 return 0;
3347 }
3348
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)3349 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3350 {
3351 struct hwrm_port_mac_cfg_input *req;
3352 int rc;
3353
3354 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
3355 if (rc)
3356 return rc;
3357
3358 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3359 if (enable)
3360 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3361 else
3362 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3363 return hwrm_req_send(bp, req);
3364 }
3365
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)3366 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3367 {
3368 struct hwrm_port_phy_qcaps_output *resp;
3369 struct hwrm_port_phy_qcaps_input *req;
3370 int rc;
3371
3372 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
3373 if (rc)
3374 return rc;
3375
3376 resp = hwrm_req_hold(bp, req);
3377 rc = hwrm_req_send(bp, req);
3378 if (!rc)
3379 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3380
3381 hwrm_req_drop(bp, req);
3382 return rc;
3383 }
3384
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)3385 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3386 struct hwrm_port_phy_cfg_input *req)
3387 {
3388 struct bnxt_link_info *link_info = &bp->link_info;
3389 u16 fw_advertising;
3390 u16 fw_speed;
3391 int rc;
3392
3393 if (!link_info->autoneg ||
3394 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
3395 return 0;
3396
3397 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3398 if (rc)
3399 return rc;
3400
3401 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3402 if (BNXT_LINK_IS_UP(bp))
3403 fw_speed = bp->link_info.link_speed;
3404 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3405 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3406 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3407 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3408 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3409 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3410 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3411 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3412
3413 req->force_link_speed = cpu_to_le16(fw_speed);
3414 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3415 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3416 rc = hwrm_req_send(bp, req);
3417 req->flags = 0;
3418 req->force_link_speed = cpu_to_le16(0);
3419 return rc;
3420 }
3421
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)3422 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3423 {
3424 struct hwrm_port_phy_cfg_input *req;
3425 int rc;
3426
3427 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3428 if (rc)
3429 return rc;
3430
3431 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */
3432 hwrm_req_hold(bp, req);
3433
3434 if (enable) {
3435 bnxt_disable_an_for_lpbk(bp, req);
3436 if (ext)
3437 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3438 else
3439 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3440 } else {
3441 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3442 }
3443 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3444 rc = hwrm_req_send(bp, req);
3445 hwrm_req_drop(bp, req);
3446 return rc;
3447 }
3448
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)3449 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3450 u32 raw_cons, int pkt_size)
3451 {
3452 struct bnxt_napi *bnapi = cpr->bnapi;
3453 struct bnxt_rx_ring_info *rxr;
3454 struct bnxt_sw_rx_bd *rx_buf;
3455 struct rx_cmp *rxcmp;
3456 u16 cp_cons, cons;
3457 u8 *data;
3458 u32 len;
3459 int i;
3460
3461 rxr = bnapi->rx_ring;
3462 cp_cons = RING_CMP(raw_cons);
3463 rxcmp = (struct rx_cmp *)
3464 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3465 cons = rxcmp->rx_cmp_opaque;
3466 rx_buf = &rxr->rx_buf_ring[cons];
3467 data = rx_buf->data_ptr;
3468 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3469 if (len != pkt_size)
3470 return -EIO;
3471 i = ETH_ALEN;
3472 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3473 return -EIO;
3474 i += ETH_ALEN;
3475 for ( ; i < pkt_size; i++) {
3476 if (data[i] != (u8)(i & 0xff))
3477 return -EIO;
3478 }
3479 return 0;
3480 }
3481
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)3482 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3483 int pkt_size)
3484 {
3485 struct tx_cmp *txcmp;
3486 int rc = -EIO;
3487 u32 raw_cons;
3488 u32 cons;
3489 int i;
3490
3491 raw_cons = cpr->cp_raw_cons;
3492 for (i = 0; i < 200; i++) {
3493 cons = RING_CMP(raw_cons);
3494 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3495
3496 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3497 udelay(5);
3498 continue;
3499 }
3500
3501 /* The valid test of the entry must be done first before
3502 * reading any further.
3503 */
3504 dma_rmb();
3505 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3506 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3507 raw_cons = NEXT_RAW_CMP(raw_cons);
3508 raw_cons = NEXT_RAW_CMP(raw_cons);
3509 break;
3510 }
3511 raw_cons = NEXT_RAW_CMP(raw_cons);
3512 }
3513 cpr->cp_raw_cons = raw_cons;
3514 return rc;
3515 }
3516
bnxt_run_loopback(struct bnxt * bp)3517 static int bnxt_run_loopback(struct bnxt *bp)
3518 {
3519 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3520 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3521 struct bnxt_cp_ring_info *cpr;
3522 int pkt_size, i = 0;
3523 struct sk_buff *skb;
3524 dma_addr_t map;
3525 u8 *data;
3526 int rc;
3527
3528 cpr = &rxr->bnapi->cp_ring;
3529 if (bp->flags & BNXT_FLAG_CHIP_P5)
3530 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3531 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3532 skb = netdev_alloc_skb(bp->dev, pkt_size);
3533 if (!skb)
3534 return -ENOMEM;
3535 data = skb_put(skb, pkt_size);
3536 ether_addr_copy(&data[i], bp->dev->dev_addr);
3537 i += ETH_ALEN;
3538 ether_addr_copy(&data[i], bp->dev->dev_addr);
3539 i += ETH_ALEN;
3540 for ( ; i < pkt_size; i++)
3541 data[i] = (u8)(i & 0xff);
3542
3543 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3544 DMA_TO_DEVICE);
3545 if (dma_mapping_error(&bp->pdev->dev, map)) {
3546 dev_kfree_skb(skb);
3547 return -EIO;
3548 }
3549 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
3550
3551 /* Sync BD data before updating doorbell */
3552 wmb();
3553
3554 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3555 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3556
3557 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
3558 dev_kfree_skb(skb);
3559 return rc;
3560 }
3561
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)3562 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3563 {
3564 struct hwrm_selftest_exec_output *resp;
3565 struct hwrm_selftest_exec_input *req;
3566 int rc;
3567
3568 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
3569 if (rc)
3570 return rc;
3571
3572 hwrm_req_timeout(bp, req, bp->test_info->timeout);
3573 req->flags = test_mask;
3574
3575 resp = hwrm_req_hold(bp, req);
3576 rc = hwrm_req_send(bp, req);
3577 *test_results = resp->test_success;
3578 hwrm_req_drop(bp, req);
3579 return rc;
3580 }
3581
3582 #define BNXT_DRV_TESTS 4
3583 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3584 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3585 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3586 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3587
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)3588 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3589 u64 *buf)
3590 {
3591 struct bnxt *bp = netdev_priv(dev);
3592 bool do_ext_lpbk = false;
3593 bool offline = false;
3594 u8 test_results = 0;
3595 u8 test_mask = 0;
3596 int rc = 0, i;
3597
3598 if (!bp->num_tests || !BNXT_PF(bp))
3599 return;
3600 memset(buf, 0, sizeof(u64) * bp->num_tests);
3601 if (!netif_running(dev)) {
3602 etest->flags |= ETH_TEST_FL_FAILED;
3603 return;
3604 }
3605
3606 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3607 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
3608 do_ext_lpbk = true;
3609
3610 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3611 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3612 etest->flags |= ETH_TEST_FL_FAILED;
3613 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3614 return;
3615 }
3616 offline = true;
3617 }
3618
3619 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3620 u8 bit_val = 1 << i;
3621
3622 if (!(bp->test_info->offline_mask & bit_val))
3623 test_mask |= bit_val;
3624 else if (offline)
3625 test_mask |= bit_val;
3626 }
3627 if (!offline) {
3628 bnxt_run_fw_tests(bp, test_mask, &test_results);
3629 } else {
3630 bnxt_ulp_stop(bp);
3631 bnxt_close_nic(bp, true, false);
3632 bnxt_run_fw_tests(bp, test_mask, &test_results);
3633
3634 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3635 bnxt_hwrm_mac_loopback(bp, true);
3636 msleep(250);
3637 rc = bnxt_half_open_nic(bp);
3638 if (rc) {
3639 bnxt_hwrm_mac_loopback(bp, false);
3640 etest->flags |= ETH_TEST_FL_FAILED;
3641 bnxt_ulp_start(bp, rc);
3642 return;
3643 }
3644 if (bnxt_run_loopback(bp))
3645 etest->flags |= ETH_TEST_FL_FAILED;
3646 else
3647 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3648
3649 bnxt_hwrm_mac_loopback(bp, false);
3650 bnxt_hwrm_phy_loopback(bp, true, false);
3651 msleep(1000);
3652 if (bnxt_run_loopback(bp)) {
3653 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3654 etest->flags |= ETH_TEST_FL_FAILED;
3655 }
3656 if (do_ext_lpbk) {
3657 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3658 bnxt_hwrm_phy_loopback(bp, true, true);
3659 msleep(1000);
3660 if (bnxt_run_loopback(bp)) {
3661 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3662 etest->flags |= ETH_TEST_FL_FAILED;
3663 }
3664 }
3665 bnxt_hwrm_phy_loopback(bp, false, false);
3666 bnxt_half_close_nic(bp);
3667 rc = bnxt_open_nic(bp, true, true);
3668 bnxt_ulp_start(bp, rc);
3669 }
3670 if (rc || bnxt_test_irq(bp)) {
3671 buf[BNXT_IRQ_TEST_IDX] = 1;
3672 etest->flags |= ETH_TEST_FL_FAILED;
3673 }
3674 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3675 u8 bit_val = 1 << i;
3676
3677 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3678 buf[i] = 1;
3679 etest->flags |= ETH_TEST_FL_FAILED;
3680 }
3681 }
3682 }
3683
bnxt_reset(struct net_device * dev,u32 * flags)3684 static int bnxt_reset(struct net_device *dev, u32 *flags)
3685 {
3686 struct bnxt *bp = netdev_priv(dev);
3687 bool reload = false;
3688 u32 req = *flags;
3689
3690 if (!req)
3691 return -EINVAL;
3692
3693 if (!BNXT_PF(bp)) {
3694 netdev_err(dev, "Reset is not supported from a VF\n");
3695 return -EOPNOTSUPP;
3696 }
3697
3698 if (pci_vfs_assigned(bp->pdev) &&
3699 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3700 netdev_err(dev,
3701 "Reset not allowed when VFs are assigned to VMs\n");
3702 return -EBUSY;
3703 }
3704
3705 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3706 /* This feature is not supported in older firmware versions */
3707 if (bp->hwrm_spec_code >= 0x10803) {
3708 if (!bnxt_firmware_reset_chip(dev)) {
3709 netdev_info(dev, "Firmware reset request successful.\n");
3710 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3711 reload = true;
3712 *flags &= ~BNXT_FW_RESET_CHIP;
3713 }
3714 } else if (req == BNXT_FW_RESET_CHIP) {
3715 return -EOPNOTSUPP; /* only request, fail hard */
3716 }
3717 }
3718
3719 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
3720 /* This feature is not supported in older firmware versions */
3721 if (bp->hwrm_spec_code >= 0x10803) {
3722 if (!bnxt_firmware_reset_ap(dev)) {
3723 netdev_info(dev, "Reset application processor successful.\n");
3724 reload = true;
3725 *flags &= ~BNXT_FW_RESET_AP;
3726 }
3727 } else if (req == BNXT_FW_RESET_AP) {
3728 return -EOPNOTSUPP; /* only request, fail hard */
3729 }
3730 }
3731
3732 if (reload)
3733 netdev_info(dev, "Reload driver to complete reset\n");
3734
3735 return 0;
3736 }
3737
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)3738 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3739 {
3740 struct bnxt *bp = netdev_priv(dev);
3741
3742 if (dump->flag > BNXT_DUMP_CRASH) {
3743 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3744 return -EINVAL;
3745 }
3746
3747 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3748 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3749 return -EOPNOTSUPP;
3750 }
3751
3752 bp->dump_flag = dump->flag;
3753 return 0;
3754 }
3755
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)3756 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3757 {
3758 struct bnxt *bp = netdev_priv(dev);
3759
3760 if (bp->hwrm_spec_code < 0x10801)
3761 return -EOPNOTSUPP;
3762
3763 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3764 bp->ver_resp.hwrm_fw_min_8b << 16 |
3765 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3766 bp->ver_resp.hwrm_fw_rsvd_8b;
3767
3768 dump->flag = bp->dump_flag;
3769 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
3770 return 0;
3771 }
3772
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)3773 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3774 void *buf)
3775 {
3776 struct bnxt *bp = netdev_priv(dev);
3777
3778 if (bp->hwrm_spec_code < 0x10801)
3779 return -EOPNOTSUPP;
3780
3781 memset(buf, 0, dump->len);
3782
3783 dump->flag = bp->dump_flag;
3784 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
3785 }
3786
bnxt_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)3787 static int bnxt_get_ts_info(struct net_device *dev,
3788 struct ethtool_ts_info *info)
3789 {
3790 struct bnxt *bp = netdev_priv(dev);
3791 struct bnxt_ptp_cfg *ptp;
3792
3793 ptp = bp->ptp_cfg;
3794 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3795 SOF_TIMESTAMPING_RX_SOFTWARE |
3796 SOF_TIMESTAMPING_SOFTWARE;
3797
3798 info->phc_index = -1;
3799 if (!ptp)
3800 return 0;
3801
3802 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
3803 SOF_TIMESTAMPING_RX_HARDWARE |
3804 SOF_TIMESTAMPING_RAW_HARDWARE;
3805 if (ptp->ptp_clock)
3806 info->phc_index = ptp_clock_index(ptp->ptp_clock);
3807
3808 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
3809
3810 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3811 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3812 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
3813
3814 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
3815 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
3816 return 0;
3817 }
3818
bnxt_ethtool_init(struct bnxt * bp)3819 void bnxt_ethtool_init(struct bnxt *bp)
3820 {
3821 struct hwrm_selftest_qlist_output *resp;
3822 struct hwrm_selftest_qlist_input *req;
3823 struct bnxt_test_info *test_info;
3824 struct net_device *dev = bp->dev;
3825 int i, rc;
3826
3827 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3828 bnxt_get_pkgver(dev);
3829
3830 bp->num_tests = 0;
3831 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3832 return;
3833
3834 test_info = bp->test_info;
3835 if (!test_info) {
3836 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3837 if (!test_info)
3838 return;
3839 bp->test_info = test_info;
3840 }
3841
3842 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
3843 return;
3844
3845 resp = hwrm_req_hold(bp, req);
3846 rc = hwrm_req_send_silent(bp, req);
3847 if (rc)
3848 goto ethtool_init_exit;
3849
3850 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3851 if (bp->num_tests > BNXT_MAX_TEST)
3852 bp->num_tests = BNXT_MAX_TEST;
3853
3854 test_info->offline_mask = resp->offline_tests;
3855 test_info->timeout = le16_to_cpu(resp->test_timeout);
3856 if (!test_info->timeout)
3857 test_info->timeout = HWRM_CMD_TIMEOUT;
3858 for (i = 0; i < bp->num_tests; i++) {
3859 char *str = test_info->string[i];
3860 char *fw_str = resp->test_name[i];
3861
3862 if (i == BNXT_MACLPBK_TEST_IDX) {
3863 strcpy(str, "Mac loopback test (offline)");
3864 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3865 strcpy(str, "Phy loopback test (offline)");
3866 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3867 strcpy(str, "Ext loopback test (offline)");
3868 } else if (i == BNXT_IRQ_TEST_IDX) {
3869 strcpy(str, "Interrupt_test (offline)");
3870 } else {
3871 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
3872 fw_str, test_info->offline_mask & (1 << i) ?
3873 "offline" : "online");
3874 }
3875 }
3876
3877 ethtool_init_exit:
3878 hwrm_req_drop(bp, req);
3879 }
3880
bnxt_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)3881 static void bnxt_get_eth_phy_stats(struct net_device *dev,
3882 struct ethtool_eth_phy_stats *phy_stats)
3883 {
3884 struct bnxt *bp = netdev_priv(dev);
3885 u64 *rx;
3886
3887 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3888 return;
3889
3890 rx = bp->rx_port_stats_ext.sw_stats;
3891 phy_stats->SymbolErrorDuringCarrier =
3892 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
3893 }
3894
bnxt_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)3895 static void bnxt_get_eth_mac_stats(struct net_device *dev,
3896 struct ethtool_eth_mac_stats *mac_stats)
3897 {
3898 struct bnxt *bp = netdev_priv(dev);
3899 u64 *rx, *tx;
3900
3901 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3902 return;
3903
3904 rx = bp->port_stats.sw_stats;
3905 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3906
3907 mac_stats->FramesReceivedOK =
3908 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
3909 mac_stats->FramesTransmittedOK =
3910 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
3911 mac_stats->FrameCheckSequenceErrors =
3912 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
3913 mac_stats->AlignmentErrors =
3914 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
3915 mac_stats->OutOfRangeLengthField =
3916 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
3917 }
3918
bnxt_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)3919 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
3920 struct ethtool_eth_ctrl_stats *ctrl_stats)
3921 {
3922 struct bnxt *bp = netdev_priv(dev);
3923 u64 *rx;
3924
3925 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3926 return;
3927
3928 rx = bp->port_stats.sw_stats;
3929 ctrl_stats->MACControlFramesReceived =
3930 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
3931 }
3932
3933 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
3934 { 0, 64 },
3935 { 65, 127 },
3936 { 128, 255 },
3937 { 256, 511 },
3938 { 512, 1023 },
3939 { 1024, 1518 },
3940 { 1519, 2047 },
3941 { 2048, 4095 },
3942 { 4096, 9216 },
3943 { 9217, 16383 },
3944 {}
3945 };
3946
bnxt_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)3947 static void bnxt_get_rmon_stats(struct net_device *dev,
3948 struct ethtool_rmon_stats *rmon_stats,
3949 const struct ethtool_rmon_hist_range **ranges)
3950 {
3951 struct bnxt *bp = netdev_priv(dev);
3952 u64 *rx, *tx;
3953
3954 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3955 return;
3956
3957 rx = bp->port_stats.sw_stats;
3958 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3959
3960 rmon_stats->jabbers =
3961 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
3962 rmon_stats->oversize_pkts =
3963 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
3964 rmon_stats->undersize_pkts =
3965 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
3966
3967 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
3968 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
3969 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
3970 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
3971 rmon_stats->hist[4] =
3972 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
3973 rmon_stats->hist[5] =
3974 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
3975 rmon_stats->hist[6] =
3976 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
3977 rmon_stats->hist[7] =
3978 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
3979 rmon_stats->hist[8] =
3980 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
3981 rmon_stats->hist[9] =
3982 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
3983
3984 rmon_stats->hist_tx[0] =
3985 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
3986 rmon_stats->hist_tx[1] =
3987 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
3988 rmon_stats->hist_tx[2] =
3989 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
3990 rmon_stats->hist_tx[3] =
3991 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
3992 rmon_stats->hist_tx[4] =
3993 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
3994 rmon_stats->hist_tx[5] =
3995 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
3996 rmon_stats->hist_tx[6] =
3997 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
3998 rmon_stats->hist_tx[7] =
3999 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
4000 rmon_stats->hist_tx[8] =
4001 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
4002 rmon_stats->hist_tx[9] =
4003 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
4004
4005 *ranges = bnxt_rmon_ranges;
4006 }
4007
bnxt_ethtool_free(struct bnxt * bp)4008 void bnxt_ethtool_free(struct bnxt *bp)
4009 {
4010 kfree(bp->test_info);
4011 bp->test_info = NULL;
4012 }
4013
4014 const struct ethtool_ops bnxt_ethtool_ops = {
4015 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4016 ETHTOOL_COALESCE_MAX_FRAMES |
4017 ETHTOOL_COALESCE_USECS_IRQ |
4018 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
4019 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
4020 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
4021 ETHTOOL_COALESCE_USE_CQE,
4022 .get_link_ksettings = bnxt_get_link_ksettings,
4023 .set_link_ksettings = bnxt_set_link_ksettings,
4024 .get_fec_stats = bnxt_get_fec_stats,
4025 .get_fecparam = bnxt_get_fecparam,
4026 .set_fecparam = bnxt_set_fecparam,
4027 .get_pause_stats = bnxt_get_pause_stats,
4028 .get_pauseparam = bnxt_get_pauseparam,
4029 .set_pauseparam = bnxt_set_pauseparam,
4030 .get_drvinfo = bnxt_get_drvinfo,
4031 .get_regs_len = bnxt_get_regs_len,
4032 .get_regs = bnxt_get_regs,
4033 .get_wol = bnxt_get_wol,
4034 .set_wol = bnxt_set_wol,
4035 .get_coalesce = bnxt_get_coalesce,
4036 .set_coalesce = bnxt_set_coalesce,
4037 .get_msglevel = bnxt_get_msglevel,
4038 .set_msglevel = bnxt_set_msglevel,
4039 .get_sset_count = bnxt_get_sset_count,
4040 .get_strings = bnxt_get_strings,
4041 .get_ethtool_stats = bnxt_get_ethtool_stats,
4042 .set_ringparam = bnxt_set_ringparam,
4043 .get_ringparam = bnxt_get_ringparam,
4044 .get_channels = bnxt_get_channels,
4045 .set_channels = bnxt_set_channels,
4046 .get_rxnfc = bnxt_get_rxnfc,
4047 .set_rxnfc = bnxt_set_rxnfc,
4048 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
4049 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
4050 .get_rxfh = bnxt_get_rxfh,
4051 .set_rxfh = bnxt_set_rxfh,
4052 .flash_device = bnxt_flash_device,
4053 .get_eeprom_len = bnxt_get_eeprom_len,
4054 .get_eeprom = bnxt_get_eeprom,
4055 .set_eeprom = bnxt_set_eeprom,
4056 .get_link = bnxt_get_link,
4057 .get_eee = bnxt_get_eee,
4058 .set_eee = bnxt_set_eee,
4059 .get_module_info = bnxt_get_module_info,
4060 .get_module_eeprom = bnxt_get_module_eeprom,
4061 .nway_reset = bnxt_nway_reset,
4062 .set_phys_id = bnxt_set_phys_id,
4063 .self_test = bnxt_self_test,
4064 .get_ts_info = bnxt_get_ts_info,
4065 .reset = bnxt_reset,
4066 .set_dump = bnxt_set_dump,
4067 .get_dump_flag = bnxt_get_dump_flag,
4068 .get_dump_data = bnxt_get_dump_data,
4069 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
4070 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
4071 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
4072 .get_rmon_stats = bnxt_get_rmon_stats,
4073 };
4074