1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/uverbs_ioctl.h>
53
54 #include "bnxt_ulp.h"
55
56 #include "roce_hsi.h"
57 #include "qplib_res.h"
58 #include "qplib_sp.h"
59 #include "qplib_fp.h"
60 #include "qplib_rcfw.h"
61
62 #include "bnxt_re.h"
63 #include "ib_verbs.h"
64 #include <rdma/bnxt_re-abi.h>
65
__from_ib_access_flags(int iflags)66 static int __from_ib_access_flags(int iflags)
67 {
68 int qflags = 0;
69
70 if (iflags & IB_ACCESS_LOCAL_WRITE)
71 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
72 if (iflags & IB_ACCESS_REMOTE_READ)
73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
74 if (iflags & IB_ACCESS_REMOTE_WRITE)
75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
76 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
77 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
78 if (iflags & IB_ACCESS_MW_BIND)
79 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
80 if (iflags & IB_ZERO_BASED)
81 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
82 if (iflags & IB_ACCESS_ON_DEMAND)
83 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
84 return qflags;
85 };
86
__to_ib_access_flags(int qflags)87 static enum ib_access_flags __to_ib_access_flags(int qflags)
88 {
89 enum ib_access_flags iflags = 0;
90
91 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
92 iflags |= IB_ACCESS_LOCAL_WRITE;
93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
94 iflags |= IB_ACCESS_REMOTE_WRITE;
95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
96 iflags |= IB_ACCESS_REMOTE_READ;
97 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
98 iflags |= IB_ACCESS_REMOTE_ATOMIC;
99 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
100 iflags |= IB_ACCESS_MW_BIND;
101 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
102 iflags |= IB_ZERO_BASED;
103 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
104 iflags |= IB_ACCESS_ON_DEMAND;
105 return iflags;
106 };
107
bnxt_re_build_sgl(struct ib_sge * ib_sg_list,struct bnxt_qplib_sge * sg_list,int num)108 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
109 struct bnxt_qplib_sge *sg_list, int num)
110 {
111 int i, total = 0;
112
113 for (i = 0; i < num; i++) {
114 sg_list[i].addr = ib_sg_list[i].addr;
115 sg_list[i].lkey = ib_sg_list[i].lkey;
116 sg_list[i].size = ib_sg_list[i].length;
117 total += sg_list[i].size;
118 }
119 return total;
120 }
121
122 /* Device */
bnxt_re_query_device(struct ib_device * ibdev,struct ib_device_attr * ib_attr,struct ib_udata * udata)123 int bnxt_re_query_device(struct ib_device *ibdev,
124 struct ib_device_attr *ib_attr,
125 struct ib_udata *udata)
126 {
127 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
128 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
129
130 memset(ib_attr, 0, sizeof(*ib_attr));
131 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
132 min(sizeof(dev_attr->fw_ver),
133 sizeof(ib_attr->fw_ver)));
134 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
135 rdev->netdev->dev_addr);
136 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
137 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
138
139 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
140 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
141 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
142 ib_attr->max_qp = dev_attr->max_qp;
143 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
144 ib_attr->device_cap_flags =
145 IB_DEVICE_CURR_QP_STATE_MOD
146 | IB_DEVICE_RC_RNR_NAK_GEN
147 | IB_DEVICE_SHUTDOWN_PORT
148 | IB_DEVICE_SYS_IMAGE_GUID
149 | IB_DEVICE_RESIZE_MAX_WR
150 | IB_DEVICE_PORT_ACTIVE_EVENT
151 | IB_DEVICE_N_NOTIFY_CQ
152 | IB_DEVICE_MEM_WINDOW
153 | IB_DEVICE_MEM_WINDOW_TYPE_2B
154 | IB_DEVICE_MEM_MGT_EXTENSIONS;
155 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
156 ib_attr->max_send_sge = dev_attr->max_qp_sges;
157 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
158 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
159 ib_attr->max_cq = dev_attr->max_cq;
160 ib_attr->max_cqe = dev_attr->max_cq_wqes;
161 ib_attr->max_mr = dev_attr->max_mr;
162 ib_attr->max_pd = dev_attr->max_pd;
163 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
164 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
165 ib_attr->atomic_cap = IB_ATOMIC_NONE;
166 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
167 if (dev_attr->is_atomic) {
168 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
169 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
170 }
171
172 ib_attr->max_ee_rd_atom = 0;
173 ib_attr->max_res_rd_atom = 0;
174 ib_attr->max_ee_init_rd_atom = 0;
175 ib_attr->max_ee = 0;
176 ib_attr->max_rdd = 0;
177 ib_attr->max_mw = dev_attr->max_mw;
178 ib_attr->max_raw_ipv6_qp = 0;
179 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
180 ib_attr->max_mcast_grp = 0;
181 ib_attr->max_mcast_qp_attach = 0;
182 ib_attr->max_total_mcast_qp_attach = 0;
183 ib_attr->max_ah = dev_attr->max_ah;
184
185 ib_attr->max_srq = dev_attr->max_srq;
186 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
187 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
188
189 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
190
191 ib_attr->max_pkeys = 1;
192 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
193 return 0;
194 }
195
196 /* Port */
bnxt_re_query_port(struct ib_device * ibdev,u32 port_num,struct ib_port_attr * port_attr)197 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
198 struct ib_port_attr *port_attr)
199 {
200 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
201 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
202
203 memset(port_attr, 0, sizeof(*port_attr));
204
205 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
206 port_attr->state = IB_PORT_ACTIVE;
207 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
208 } else {
209 port_attr->state = IB_PORT_DOWN;
210 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
211 }
212 port_attr->max_mtu = IB_MTU_4096;
213 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
214 port_attr->gid_tbl_len = dev_attr->max_sgid;
215 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
216 IB_PORT_DEVICE_MGMT_SUP |
217 IB_PORT_VENDOR_CLASS_SUP;
218 port_attr->ip_gids = true;
219
220 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
221 port_attr->bad_pkey_cntr = 0;
222 port_attr->qkey_viol_cntr = 0;
223 port_attr->pkey_tbl_len = dev_attr->max_pkey;
224 port_attr->lid = 0;
225 port_attr->sm_lid = 0;
226 port_attr->lmc = 0;
227 port_attr->max_vl_num = 4;
228 port_attr->sm_sl = 0;
229 port_attr->subnet_timeout = 0;
230 port_attr->init_type_reply = 0;
231 port_attr->active_speed = rdev->active_speed;
232 port_attr->active_width = rdev->active_width;
233
234 return 0;
235 }
236
bnxt_re_get_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)237 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
238 struct ib_port_immutable *immutable)
239 {
240 struct ib_port_attr port_attr;
241
242 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
243 return -EINVAL;
244
245 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
246 immutable->gid_tbl_len = port_attr.gid_tbl_len;
247 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
248 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
249 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
250 return 0;
251 }
252
bnxt_re_query_fw_str(struct ib_device * ibdev,char * str)253 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
254 {
255 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
256
257 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
258 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
259 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
260 }
261
bnxt_re_query_pkey(struct ib_device * ibdev,u32 port_num,u16 index,u16 * pkey)262 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
263 u16 index, u16 *pkey)
264 {
265 if (index > 0)
266 return -EINVAL;
267
268 *pkey = IB_DEFAULT_PKEY_FULL;
269
270 return 0;
271 }
272
bnxt_re_query_gid(struct ib_device * ibdev,u32 port_num,int index,union ib_gid * gid)273 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
274 int index, union ib_gid *gid)
275 {
276 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
277 int rc = 0;
278
279 /* Ignore port_num */
280 memset(gid, 0, sizeof(*gid));
281 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
282 &rdev->qplib_res.sgid_tbl, index,
283 (struct bnxt_qplib_gid *)gid);
284 return rc;
285 }
286
bnxt_re_del_gid(const struct ib_gid_attr * attr,void ** context)287 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
288 {
289 int rc = 0;
290 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
291 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
292 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
293 struct bnxt_qplib_gid *gid_to_del;
294 u16 vlan_id = 0xFFFF;
295
296 /* Delete the entry from the hardware */
297 ctx = *context;
298 if (!ctx)
299 return -EINVAL;
300
301 if (sgid_tbl && sgid_tbl->active) {
302 if (ctx->idx >= sgid_tbl->max)
303 return -EINVAL;
304 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
305 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
306 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
307 * or via the ib_unregister_device path. In the former case QP1
308 * may not be destroyed yet, in which case just return as FW
309 * needs that entry to be present and will fail it's deletion.
310 * We could get invoked again after QP1 is destroyed OR get an
311 * ADD_GID call with a different GID value for the same index
312 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
313 */
314 if (ctx->idx == 0 &&
315 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
316 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
317 ibdev_dbg(&rdev->ibdev,
318 "Trying to delete GID0 while QP1 is alive\n");
319 return -EFAULT;
320 }
321 ctx->refcnt--;
322 if (!ctx->refcnt) {
323 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
324 vlan_id, true);
325 if (rc) {
326 ibdev_err(&rdev->ibdev,
327 "Failed to remove GID: %#x", rc);
328 } else {
329 ctx_tbl = sgid_tbl->ctx;
330 ctx_tbl[ctx->idx] = NULL;
331 kfree(ctx);
332 }
333 }
334 } else {
335 return -EINVAL;
336 }
337 return rc;
338 }
339
bnxt_re_add_gid(const struct ib_gid_attr * attr,void ** context)340 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
341 {
342 int rc;
343 u32 tbl_idx = 0;
344 u16 vlan_id = 0xFFFF;
345 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
346 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
347 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
348
349 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
350 if (rc)
351 return rc;
352
353 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
354 rdev->qplib_res.netdev->dev_addr,
355 vlan_id, true, &tbl_idx);
356 if (rc == -EALREADY) {
357 ctx_tbl = sgid_tbl->ctx;
358 ctx_tbl[tbl_idx]->refcnt++;
359 *context = ctx_tbl[tbl_idx];
360 return 0;
361 }
362
363 if (rc < 0) {
364 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
365 return rc;
366 }
367
368 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
369 if (!ctx)
370 return -ENOMEM;
371 ctx_tbl = sgid_tbl->ctx;
372 ctx->idx = tbl_idx;
373 ctx->refcnt = 1;
374 ctx_tbl[tbl_idx] = ctx;
375 *context = ctx;
376
377 return rc;
378 }
379
bnxt_re_get_link_layer(struct ib_device * ibdev,u32 port_num)380 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
381 u32 port_num)
382 {
383 return IB_LINK_LAYER_ETHERNET;
384 }
385
386 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
387
bnxt_re_create_fence_wqe(struct bnxt_re_pd * pd)388 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
389 {
390 struct bnxt_re_fence_data *fence = &pd->fence;
391 struct ib_mr *ib_mr = &fence->mr->ib_mr;
392 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
393
394 memset(wqe, 0, sizeof(*wqe));
395 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
396 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
398 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
399 wqe->bind.zero_based = false;
400 wqe->bind.parent_l_key = ib_mr->lkey;
401 wqe->bind.va = (u64)(unsigned long)fence->va;
402 wqe->bind.length = fence->size;
403 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
404 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
405
406 /* Save the initial rkey in fence structure for now;
407 * wqe->bind.r_key will be set at (re)bind time.
408 */
409 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
410 }
411
bnxt_re_bind_fence_mw(struct bnxt_qplib_qp * qplib_qp)412 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
413 {
414 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
415 qplib_qp);
416 struct ib_pd *ib_pd = qp->ib_qp.pd;
417 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
418 struct bnxt_re_fence_data *fence = &pd->fence;
419 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
420 struct bnxt_qplib_swqe wqe;
421 int rc;
422
423 memcpy(&wqe, fence_wqe, sizeof(wqe));
424 wqe.bind.r_key = fence->bind_rkey;
425 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
426
427 ibdev_dbg(&qp->rdev->ibdev,
428 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
429 wqe.bind.r_key, qp->qplib_qp.id, pd);
430 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
431 if (rc) {
432 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
433 return rc;
434 }
435 bnxt_qplib_post_send_db(&qp->qplib_qp);
436
437 return rc;
438 }
439
bnxt_re_destroy_fence_mr(struct bnxt_re_pd * pd)440 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
441 {
442 struct bnxt_re_fence_data *fence = &pd->fence;
443 struct bnxt_re_dev *rdev = pd->rdev;
444 struct device *dev = &rdev->en_dev->pdev->dev;
445 struct bnxt_re_mr *mr = fence->mr;
446
447 if (fence->mw) {
448 bnxt_re_dealloc_mw(fence->mw);
449 fence->mw = NULL;
450 }
451 if (mr) {
452 if (mr->ib_mr.rkey)
453 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
454 true);
455 if (mr->ib_mr.lkey)
456 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
457 kfree(mr);
458 fence->mr = NULL;
459 }
460 if (fence->dma_addr) {
461 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
462 DMA_BIDIRECTIONAL);
463 fence->dma_addr = 0;
464 }
465 }
466
bnxt_re_create_fence_mr(struct bnxt_re_pd * pd)467 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
468 {
469 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
470 struct bnxt_re_fence_data *fence = &pd->fence;
471 struct bnxt_re_dev *rdev = pd->rdev;
472 struct device *dev = &rdev->en_dev->pdev->dev;
473 struct bnxt_re_mr *mr = NULL;
474 dma_addr_t dma_addr = 0;
475 struct ib_mw *mw;
476 int rc;
477
478 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
479 DMA_BIDIRECTIONAL);
480 rc = dma_mapping_error(dev, dma_addr);
481 if (rc) {
482 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
483 rc = -EIO;
484 fence->dma_addr = 0;
485 goto fail;
486 }
487 fence->dma_addr = dma_addr;
488
489 /* Allocate a MR */
490 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
491 if (!mr) {
492 rc = -ENOMEM;
493 goto fail;
494 }
495 fence->mr = mr;
496 mr->rdev = rdev;
497 mr->qplib_mr.pd = &pd->qplib_pd;
498 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
499 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
500 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
501 if (rc) {
502 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
503 goto fail;
504 }
505
506 /* Register MR */
507 mr->ib_mr.lkey = mr->qplib_mr.lkey;
508 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
509 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
510 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
511 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
512 if (rc) {
513 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
514 goto fail;
515 }
516 mr->ib_mr.rkey = mr->qplib_mr.rkey;
517
518 /* Create a fence MW only for kernel consumers */
519 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
520 if (IS_ERR(mw)) {
521 ibdev_err(&rdev->ibdev,
522 "Failed to create fence-MW for PD: %p\n", pd);
523 rc = PTR_ERR(mw);
524 goto fail;
525 }
526 fence->mw = mw;
527
528 bnxt_re_create_fence_wqe(pd);
529 return 0;
530
531 fail:
532 bnxt_re_destroy_fence_mr(pd);
533 return rc;
534 }
535
536 /* Protection Domains */
bnxt_re_dealloc_pd(struct ib_pd * ib_pd,struct ib_udata * udata)537 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
538 {
539 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
540 struct bnxt_re_dev *rdev = pd->rdev;
541
542 bnxt_re_destroy_fence_mr(pd);
543
544 if (pd->qplib_pd.id) {
545 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
546 &rdev->qplib_res.pd_tbl,
547 &pd->qplib_pd))
548 atomic_dec(&rdev->pd_count);
549 }
550 return 0;
551 }
552
bnxt_re_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)553 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
554 {
555 struct ib_device *ibdev = ibpd->device;
556 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
557 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
558 udata, struct bnxt_re_ucontext, ib_uctx);
559 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
560 int rc;
561
562 pd->rdev = rdev;
563 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
564 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
565 rc = -ENOMEM;
566 goto fail;
567 }
568
569 if (udata) {
570 struct bnxt_re_pd_resp resp;
571
572 if (!ucntx->dpi.dbr) {
573 /* Allocate DPI in alloc_pd to avoid failing of
574 * ibv_devinfo and family of application when DPIs
575 * are depleted.
576 */
577 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
578 &ucntx->dpi, ucntx)) {
579 rc = -ENOMEM;
580 goto dbfail;
581 }
582 }
583
584 resp.pdid = pd->qplib_pd.id;
585 /* Still allow mapping this DBR to the new user PD. */
586 resp.dpi = ucntx->dpi.dpi;
587 resp.dbr = (u64)ucntx->dpi.umdbr;
588
589 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
590 if (rc) {
591 ibdev_err(&rdev->ibdev,
592 "Failed to copy user response\n");
593 goto dbfail;
594 }
595 }
596
597 if (!udata)
598 if (bnxt_re_create_fence_mr(pd))
599 ibdev_warn(&rdev->ibdev,
600 "Failed to create Fence-MR\n");
601 atomic_inc(&rdev->pd_count);
602
603 return 0;
604 dbfail:
605 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
606 &pd->qplib_pd);
607 fail:
608 return rc;
609 }
610
611 /* Address Handles */
bnxt_re_destroy_ah(struct ib_ah * ib_ah,u32 flags)612 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
613 {
614 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
615 struct bnxt_re_dev *rdev = ah->rdev;
616
617 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
618 !(flags & RDMA_DESTROY_AH_SLEEPABLE));
619 atomic_dec(&rdev->ah_count);
620
621 return 0;
622 }
623
bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)624 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
625 {
626 u8 nw_type;
627
628 switch (ntype) {
629 case RDMA_NETWORK_IPV4:
630 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
631 break;
632 case RDMA_NETWORK_IPV6:
633 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
634 break;
635 default:
636 nw_type = CMDQ_CREATE_AH_TYPE_V1;
637 break;
638 }
639 return nw_type;
640 }
641
bnxt_re_create_ah(struct ib_ah * ib_ah,struct rdma_ah_init_attr * init_attr,struct ib_udata * udata)642 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
643 struct ib_udata *udata)
644 {
645 struct ib_pd *ib_pd = ib_ah->pd;
646 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
647 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
648 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
649 struct bnxt_re_dev *rdev = pd->rdev;
650 const struct ib_gid_attr *sgid_attr;
651 struct bnxt_re_gid_ctx *ctx;
652 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
653 u8 nw_type;
654 int rc;
655
656 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
657 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
658 return -EINVAL;
659 }
660
661 ah->rdev = rdev;
662 ah->qplib_ah.pd = &pd->qplib_pd;
663
664 /* Supply the configuration for the HW */
665 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
666 sizeof(union ib_gid));
667 sgid_attr = grh->sgid_attr;
668 /* Get the HW context of the GID. The reference
669 * of GID table entry is already taken by the caller.
670 */
671 ctx = rdma_read_gid_hw_context(sgid_attr);
672 ah->qplib_ah.sgid_index = ctx->idx;
673 ah->qplib_ah.host_sgid_index = grh->sgid_index;
674 ah->qplib_ah.traffic_class = grh->traffic_class;
675 ah->qplib_ah.flow_label = grh->flow_label;
676 ah->qplib_ah.hop_limit = grh->hop_limit;
677 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
678
679 /* Get network header type for this GID */
680 nw_type = rdma_gid_attr_network_type(sgid_attr);
681 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
682
683 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
684 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
685 !(init_attr->flags &
686 RDMA_CREATE_AH_SLEEPABLE));
687 if (rc) {
688 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
689 return rc;
690 }
691
692 /* Write AVID to shared page. */
693 if (udata) {
694 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
695 udata, struct bnxt_re_ucontext, ib_uctx);
696 unsigned long flag;
697 u32 *wrptr;
698
699 spin_lock_irqsave(&uctx->sh_lock, flag);
700 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
701 *wrptr = ah->qplib_ah.id;
702 wmb(); /* make sure cache is updated. */
703 spin_unlock_irqrestore(&uctx->sh_lock, flag);
704 }
705 atomic_inc(&rdev->ah_count);
706
707 return 0;
708 }
709
bnxt_re_query_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)710 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
711 {
712 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
713
714 ah_attr->type = ib_ah->type;
715 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
716 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
717 rdma_ah_set_grh(ah_attr, NULL, 0,
718 ah->qplib_ah.host_sgid_index,
719 0, ah->qplib_ah.traffic_class);
720 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
721 rdma_ah_set_port_num(ah_attr, 1);
722 rdma_ah_set_static_rate(ah_attr, 0);
723 return 0;
724 }
725
bnxt_re_lock_cqs(struct bnxt_re_qp * qp)726 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
727 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
728 {
729 unsigned long flags;
730
731 spin_lock_irqsave(&qp->scq->cq_lock, flags);
732 if (qp->rcq != qp->scq)
733 spin_lock(&qp->rcq->cq_lock);
734 else
735 __acquire(&qp->rcq->cq_lock);
736
737 return flags;
738 }
739
bnxt_re_unlock_cqs(struct bnxt_re_qp * qp,unsigned long flags)740 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
741 unsigned long flags)
742 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
743 {
744 if (qp->rcq != qp->scq)
745 spin_unlock(&qp->rcq->cq_lock);
746 else
747 __release(&qp->rcq->cq_lock);
748 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
749 }
750
bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp * qp)751 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
752 {
753 struct bnxt_re_qp *gsi_sqp;
754 struct bnxt_re_ah *gsi_sah;
755 struct bnxt_re_dev *rdev;
756 int rc = 0;
757
758 rdev = qp->rdev;
759 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
760 gsi_sah = rdev->gsi_ctx.gsi_sah;
761
762 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
763 bnxt_qplib_destroy_ah(&rdev->qplib_res,
764 &gsi_sah->qplib_ah,
765 true);
766 atomic_dec(&rdev->ah_count);
767 bnxt_qplib_clean_qp(&qp->qplib_qp);
768
769 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
770 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
771 if (rc) {
772 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
773 goto fail;
774 }
775 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
776
777 /* remove from active qp list */
778 mutex_lock(&rdev->qp_lock);
779 list_del(&gsi_sqp->list);
780 mutex_unlock(&rdev->qp_lock);
781 atomic_dec(&rdev->qp_count);
782
783 kfree(rdev->gsi_ctx.sqp_tbl);
784 kfree(gsi_sah);
785 kfree(gsi_sqp);
786 rdev->gsi_ctx.gsi_sqp = NULL;
787 rdev->gsi_ctx.gsi_sah = NULL;
788 rdev->gsi_ctx.sqp_tbl = NULL;
789
790 return 0;
791 fail:
792 return rc;
793 }
794
795 /* Queue Pairs */
bnxt_re_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)796 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
797 {
798 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
799 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
800 struct bnxt_re_dev *rdev = qp->rdev;
801 struct bnxt_qplib_nq *scq_nq = NULL;
802 struct bnxt_qplib_nq *rcq_nq = NULL;
803 unsigned int flags;
804 int rc;
805
806 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
807
808 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
809 if (rc) {
810 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
811 return rc;
812 }
813
814 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
815 flags = bnxt_re_lock_cqs(qp);
816 bnxt_qplib_clean_qp(&qp->qplib_qp);
817 bnxt_re_unlock_cqs(qp, flags);
818 }
819
820 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
821
822 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
823 rc = bnxt_re_destroy_gsi_sqp(qp);
824 if (rc)
825 return rc;
826 }
827
828 mutex_lock(&rdev->qp_lock);
829 list_del(&qp->list);
830 mutex_unlock(&rdev->qp_lock);
831 atomic_dec(&rdev->qp_count);
832
833 ib_umem_release(qp->rumem);
834 ib_umem_release(qp->sumem);
835
836 /* Flush all the entries of notification queue associated with
837 * given qp.
838 */
839 scq_nq = qplib_qp->scq->nq;
840 rcq_nq = qplib_qp->rcq->nq;
841 bnxt_re_synchronize_nq(scq_nq);
842 if (scq_nq != rcq_nq)
843 bnxt_re_synchronize_nq(rcq_nq);
844
845 return 0;
846 }
847
__from_ib_qp_type(enum ib_qp_type type)848 static u8 __from_ib_qp_type(enum ib_qp_type type)
849 {
850 switch (type) {
851 case IB_QPT_GSI:
852 return CMDQ_CREATE_QP1_TYPE_GSI;
853 case IB_QPT_RC:
854 return CMDQ_CREATE_QP_TYPE_RC;
855 case IB_QPT_UD:
856 return CMDQ_CREATE_QP_TYPE_UD;
857 default:
858 return IB_QPT_MAX;
859 }
860 }
861
bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp * qplqp,int rsge,int max)862 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
863 int rsge, int max)
864 {
865 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
866 rsge = max;
867 return bnxt_re_get_rwqe_size(rsge);
868 }
869
bnxt_re_get_wqe_size(int ilsize,int nsge)870 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
871 {
872 u16 wqe_size, calc_ils;
873
874 wqe_size = bnxt_re_get_swqe_size(nsge);
875 if (ilsize) {
876 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
877 wqe_size = max_t(u16, calc_ils, wqe_size);
878 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
879 }
880 return wqe_size;
881 }
882
bnxt_re_setup_swqe_size(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)883 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
884 struct ib_qp_init_attr *init_attr)
885 {
886 struct bnxt_qplib_dev_attr *dev_attr;
887 struct bnxt_qplib_qp *qplqp;
888 struct bnxt_re_dev *rdev;
889 struct bnxt_qplib_q *sq;
890 int align, ilsize;
891
892 rdev = qp->rdev;
893 qplqp = &qp->qplib_qp;
894 sq = &qplqp->sq;
895 dev_attr = &rdev->dev_attr;
896
897 align = sizeof(struct sq_send_hdr);
898 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
899
900 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
901 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
902 return -EINVAL;
903 /* For gen p4 and gen p5 backward compatibility mode
904 * wqe size is fixed to 128 bytes
905 */
906 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) &&
907 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
908 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges);
909
910 if (init_attr->cap.max_inline_data) {
911 qplqp->max_inline_data = sq->wqe_size -
912 sizeof(struct sq_send_hdr);
913 init_attr->cap.max_inline_data = qplqp->max_inline_data;
914 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
915 sq->max_sge = qplqp->max_inline_data /
916 sizeof(struct sq_sge);
917 }
918
919 return 0;
920 }
921
bnxt_re_init_user_qp(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_qp * qp,struct ib_udata * udata)922 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
923 struct bnxt_re_qp *qp, struct ib_udata *udata)
924 {
925 struct bnxt_qplib_qp *qplib_qp;
926 struct bnxt_re_ucontext *cntx;
927 struct bnxt_re_qp_req ureq;
928 int bytes = 0, psn_sz;
929 struct ib_umem *umem;
930 int psn_nume;
931
932 qplib_qp = &qp->qplib_qp;
933 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,
934 ib_uctx);
935 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
936 return -EFAULT;
937
938 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
939 /* Consider mapping PSN search memory only for RC QPs. */
940 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
941 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
942 sizeof(struct sq_psn_search_ext) :
943 sizeof(struct sq_psn_search);
944 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
945 qplib_qp->sq.max_wqe :
946 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
947 sizeof(struct bnxt_qplib_sge));
948 bytes += (psn_nume * psn_sz);
949 }
950
951 bytes = PAGE_ALIGN(bytes);
952 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
953 IB_ACCESS_LOCAL_WRITE);
954 if (IS_ERR(umem))
955 return PTR_ERR(umem);
956
957 qp->sumem = umem;
958 qplib_qp->sq.sg_info.umem = umem;
959 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
960 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
961 qplib_qp->qp_handle = ureq.qp_handle;
962
963 if (!qp->qplib_qp.srq) {
964 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
965 bytes = PAGE_ALIGN(bytes);
966 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
967 IB_ACCESS_LOCAL_WRITE);
968 if (IS_ERR(umem))
969 goto rqfail;
970 qp->rumem = umem;
971 qplib_qp->rq.sg_info.umem = umem;
972 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
973 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
974 }
975
976 qplib_qp->dpi = &cntx->dpi;
977 return 0;
978 rqfail:
979 ib_umem_release(qp->sumem);
980 qp->sumem = NULL;
981 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
982
983 return PTR_ERR(umem);
984 }
985
bnxt_re_create_shadow_qp_ah(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)986 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
987 (struct bnxt_re_pd *pd,
988 struct bnxt_qplib_res *qp1_res,
989 struct bnxt_qplib_qp *qp1_qp)
990 {
991 struct bnxt_re_dev *rdev = pd->rdev;
992 struct bnxt_re_ah *ah;
993 union ib_gid sgid;
994 int rc;
995
996 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
997 if (!ah)
998 return NULL;
999
1000 ah->rdev = rdev;
1001 ah->qplib_ah.pd = &pd->qplib_pd;
1002
1003 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1004 if (rc)
1005 goto fail;
1006
1007 /* supply the dgid data same as sgid */
1008 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1009 sizeof(union ib_gid));
1010 ah->qplib_ah.sgid_index = 0;
1011
1012 ah->qplib_ah.traffic_class = 0;
1013 ah->qplib_ah.flow_label = 0;
1014 ah->qplib_ah.hop_limit = 1;
1015 ah->qplib_ah.sl = 0;
1016 /* Have DMAC same as SMAC */
1017 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1018
1019 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1020 if (rc) {
1021 ibdev_err(&rdev->ibdev,
1022 "Failed to allocate HW AH for Shadow QP");
1023 goto fail;
1024 }
1025 atomic_inc(&rdev->ah_count);
1026
1027 return ah;
1028
1029 fail:
1030 kfree(ah);
1031 return NULL;
1032 }
1033
bnxt_re_create_shadow_qp(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1034 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1035 (struct bnxt_re_pd *pd,
1036 struct bnxt_qplib_res *qp1_res,
1037 struct bnxt_qplib_qp *qp1_qp)
1038 {
1039 struct bnxt_re_dev *rdev = pd->rdev;
1040 struct bnxt_re_qp *qp;
1041 int rc;
1042
1043 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1044 if (!qp)
1045 return NULL;
1046
1047 qp->rdev = rdev;
1048
1049 /* Initialize the shadow QP structure from the QP1 values */
1050 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1051
1052 qp->qplib_qp.pd = &pd->qplib_pd;
1053 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1054 qp->qplib_qp.type = IB_QPT_UD;
1055
1056 qp->qplib_qp.max_inline_data = 0;
1057 qp->qplib_qp.sig_type = true;
1058
1059 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1060 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1061 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1062 qp->qplib_qp.sq.max_sge = 2;
1063 /* Q full delta can be 1 since it is internal QP */
1064 qp->qplib_qp.sq.q_full_delta = 1;
1065 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1066 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1067
1068 qp->qplib_qp.scq = qp1_qp->scq;
1069 qp->qplib_qp.rcq = qp1_qp->rcq;
1070
1071 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1072 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1073 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1074 /* Q full delta can be 1 since it is internal QP */
1075 qp->qplib_qp.rq.q_full_delta = 1;
1076 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1077 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1078
1079 qp->qplib_qp.mtu = qp1_qp->mtu;
1080
1081 qp->qplib_qp.sq_hdr_buf_size = 0;
1082 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1083 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1084
1085 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1086 if (rc)
1087 goto fail;
1088
1089 spin_lock_init(&qp->sq_lock);
1090 INIT_LIST_HEAD(&qp->list);
1091 mutex_lock(&rdev->qp_lock);
1092 list_add_tail(&qp->list, &rdev->qp_list);
1093 atomic_inc(&rdev->qp_count);
1094 mutex_unlock(&rdev->qp_lock);
1095 return qp;
1096 fail:
1097 kfree(qp);
1098 return NULL;
1099 }
1100
bnxt_re_init_rq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1101 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1102 struct ib_qp_init_attr *init_attr)
1103 {
1104 struct bnxt_qplib_dev_attr *dev_attr;
1105 struct bnxt_qplib_qp *qplqp;
1106 struct bnxt_re_dev *rdev;
1107 struct bnxt_qplib_q *rq;
1108 int entries;
1109
1110 rdev = qp->rdev;
1111 qplqp = &qp->qplib_qp;
1112 rq = &qplqp->rq;
1113 dev_attr = &rdev->dev_attr;
1114
1115 if (init_attr->srq) {
1116 struct bnxt_re_srq *srq;
1117
1118 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1119 qplqp->srq = &srq->qplib_srq;
1120 rq->max_wqe = 0;
1121 } else {
1122 rq->max_sge = init_attr->cap.max_recv_sge;
1123 if (rq->max_sge > dev_attr->max_qp_sges)
1124 rq->max_sge = dev_attr->max_qp_sges;
1125 init_attr->cap.max_recv_sge = rq->max_sge;
1126 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1127 dev_attr->max_qp_sges);
1128 /* Allocate 1 more than what's provided so posting max doesn't
1129 * mean empty.
1130 */
1131 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1132 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1133 rq->q_full_delta = 0;
1134 rq->sg_info.pgsize = PAGE_SIZE;
1135 rq->sg_info.pgshft = PAGE_SHIFT;
1136 }
1137
1138 return 0;
1139 }
1140
bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp * qp)1141 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1142 {
1143 struct bnxt_qplib_dev_attr *dev_attr;
1144 struct bnxt_qplib_qp *qplqp;
1145 struct bnxt_re_dev *rdev;
1146
1147 rdev = qp->rdev;
1148 qplqp = &qp->qplib_qp;
1149 dev_attr = &rdev->dev_attr;
1150
1151 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1152 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1153 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1154 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1155 qplqp->rq.max_sge = 6;
1156 }
1157 }
1158
bnxt_re_init_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1159 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1160 struct ib_qp_init_attr *init_attr,
1161 struct ib_udata *udata)
1162 {
1163 struct bnxt_qplib_dev_attr *dev_attr;
1164 struct bnxt_qplib_qp *qplqp;
1165 struct bnxt_re_dev *rdev;
1166 struct bnxt_qplib_q *sq;
1167 int entries;
1168 int diff;
1169 int rc;
1170
1171 rdev = qp->rdev;
1172 qplqp = &qp->qplib_qp;
1173 sq = &qplqp->sq;
1174 dev_attr = &rdev->dev_attr;
1175
1176 sq->max_sge = init_attr->cap.max_send_sge;
1177 if (sq->max_sge > dev_attr->max_qp_sges) {
1178 sq->max_sge = dev_attr->max_qp_sges;
1179 init_attr->cap.max_send_sge = sq->max_sge;
1180 }
1181
1182 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1183 if (rc)
1184 return rc;
1185
1186 entries = init_attr->cap.max_send_wr;
1187 /* Allocate 128 + 1 more than what's provided */
1188 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1189 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1190 entries = roundup_pow_of_two(entries + diff + 1);
1191 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1192 sq->q_full_delta = diff + 1;
1193 /*
1194 * Reserving one slot for Phantom WQE. Application can
1195 * post one extra entry in this case. But allowing this to avoid
1196 * unexpected Queue full condition
1197 */
1198 qplqp->sq.q_full_delta -= 1;
1199 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1200 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1201
1202 return 0;
1203 }
1204
bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1205 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1206 struct ib_qp_init_attr *init_attr)
1207 {
1208 struct bnxt_qplib_dev_attr *dev_attr;
1209 struct bnxt_qplib_qp *qplqp;
1210 struct bnxt_re_dev *rdev;
1211 int entries;
1212
1213 rdev = qp->rdev;
1214 qplqp = &qp->qplib_qp;
1215 dev_attr = &rdev->dev_attr;
1216
1217 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1218 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1219 qplqp->sq.max_wqe = min_t(u32, entries,
1220 dev_attr->max_qp_wqes + 1);
1221 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1222 init_attr->cap.max_send_wr;
1223 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1224 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1225 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1226 }
1227 }
1228
bnxt_re_init_qp_type(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr)1229 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1230 struct ib_qp_init_attr *init_attr)
1231 {
1232 struct bnxt_qplib_chip_ctx *chip_ctx;
1233 int qptype;
1234
1235 chip_ctx = rdev->chip_ctx;
1236
1237 qptype = __from_ib_qp_type(init_attr->qp_type);
1238 if (qptype == IB_QPT_MAX) {
1239 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1240 qptype = -EOPNOTSUPP;
1241 goto out;
1242 }
1243
1244 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1245 init_attr->qp_type == IB_QPT_GSI)
1246 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1247 out:
1248 return qptype;
1249 }
1250
bnxt_re_init_qp_attr(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1251 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1252 struct ib_qp_init_attr *init_attr,
1253 struct ib_udata *udata)
1254 {
1255 struct bnxt_qplib_dev_attr *dev_attr;
1256 struct bnxt_qplib_qp *qplqp;
1257 struct bnxt_re_dev *rdev;
1258 struct bnxt_re_cq *cq;
1259 int rc = 0, qptype;
1260
1261 rdev = qp->rdev;
1262 qplqp = &qp->qplib_qp;
1263 dev_attr = &rdev->dev_attr;
1264
1265 /* Setup misc params */
1266 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1267 qplqp->pd = &pd->qplib_pd;
1268 qplqp->qp_handle = (u64)qplqp;
1269 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1270 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1271 true : false);
1272 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1273 if (qptype < 0) {
1274 rc = qptype;
1275 goto out;
1276 }
1277 qplqp->type = (u8)qptype;
1278 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode;
1279
1280 if (init_attr->qp_type == IB_QPT_RC) {
1281 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1282 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1283 }
1284 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1285 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1286 if (init_attr->create_flags) {
1287 ibdev_dbg(&rdev->ibdev,
1288 "QP create flags 0x%x not supported",
1289 init_attr->create_flags);
1290 return -EOPNOTSUPP;
1291 }
1292
1293 /* Setup CQs */
1294 if (init_attr->send_cq) {
1295 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1296 qplqp->scq = &cq->qplib_cq;
1297 qp->scq = cq;
1298 }
1299
1300 if (init_attr->recv_cq) {
1301 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1302 qplqp->rcq = &cq->qplib_cq;
1303 qp->rcq = cq;
1304 }
1305
1306 /* Setup RQ/SRQ */
1307 rc = bnxt_re_init_rq_attr(qp, init_attr);
1308 if (rc)
1309 goto out;
1310 if (init_attr->qp_type == IB_QPT_GSI)
1311 bnxt_re_adjust_gsi_rq_attr(qp);
1312
1313 /* Setup SQ */
1314 rc = bnxt_re_init_sq_attr(qp, init_attr, udata);
1315 if (rc)
1316 goto out;
1317 if (init_attr->qp_type == IB_QPT_GSI)
1318 bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1319
1320 if (udata) /* This will update DPI and qp_handle */
1321 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1322 out:
1323 return rc;
1324 }
1325
bnxt_re_create_shadow_gsi(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd)1326 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1327 struct bnxt_re_pd *pd)
1328 {
1329 struct bnxt_re_sqp_entries *sqp_tbl;
1330 struct bnxt_re_dev *rdev;
1331 struct bnxt_re_qp *sqp;
1332 struct bnxt_re_ah *sah;
1333 int rc = 0;
1334
1335 rdev = qp->rdev;
1336 /* Create a shadow QP to handle the QP1 traffic */
1337 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1338 GFP_KERNEL);
1339 if (!sqp_tbl)
1340 return -ENOMEM;
1341 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1342
1343 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1344 if (!sqp) {
1345 rc = -ENODEV;
1346 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1347 goto out;
1348 }
1349 rdev->gsi_ctx.gsi_sqp = sqp;
1350
1351 sqp->rcq = qp->rcq;
1352 sqp->scq = qp->scq;
1353 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1354 &qp->qplib_qp);
1355 if (!sah) {
1356 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1357 &sqp->qplib_qp);
1358 rc = -ENODEV;
1359 ibdev_err(&rdev->ibdev,
1360 "Failed to create AH entry for ShadowQP");
1361 goto out;
1362 }
1363 rdev->gsi_ctx.gsi_sah = sah;
1364
1365 return 0;
1366 out:
1367 kfree(sqp_tbl);
1368 return rc;
1369 }
1370
bnxt_re_create_gsi_qp(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr)1371 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1372 struct ib_qp_init_attr *init_attr)
1373 {
1374 struct bnxt_re_dev *rdev;
1375 struct bnxt_qplib_qp *qplqp;
1376 int rc = 0;
1377
1378 rdev = qp->rdev;
1379 qplqp = &qp->qplib_qp;
1380
1381 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1382 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1383
1384 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1385 if (rc) {
1386 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1387 goto out;
1388 }
1389
1390 rc = bnxt_re_create_shadow_gsi(qp, pd);
1391 out:
1392 return rc;
1393 }
1394
bnxt_re_test_qp_limits(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr,struct bnxt_qplib_dev_attr * dev_attr)1395 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1396 struct ib_qp_init_attr *init_attr,
1397 struct bnxt_qplib_dev_attr *dev_attr)
1398 {
1399 bool rc = true;
1400
1401 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1402 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1403 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1404 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1405 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1406 ibdev_err(&rdev->ibdev,
1407 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1408 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1409 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1410 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1411 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1412 init_attr->cap.max_inline_data,
1413 dev_attr->max_inline_data);
1414 rc = false;
1415 }
1416 return rc;
1417 }
1418
bnxt_re_create_qp(struct ib_qp * ib_qp,struct ib_qp_init_attr * qp_init_attr,struct ib_udata * udata)1419 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1420 struct ib_udata *udata)
1421 {
1422 struct ib_pd *ib_pd = ib_qp->pd;
1423 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1424 struct bnxt_re_dev *rdev = pd->rdev;
1425 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1426 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1427 int rc;
1428
1429 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1430 if (!rc) {
1431 rc = -EINVAL;
1432 goto fail;
1433 }
1434
1435 qp->rdev = rdev;
1436 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1437 if (rc)
1438 goto fail;
1439
1440 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1441 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1442 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1443 if (rc == -ENODEV)
1444 goto qp_destroy;
1445 if (rc)
1446 goto fail;
1447 } else {
1448 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1449 if (rc) {
1450 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1451 goto free_umem;
1452 }
1453 if (udata) {
1454 struct bnxt_re_qp_resp resp;
1455
1456 resp.qpid = qp->qplib_qp.id;
1457 resp.rsvd = 0;
1458 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1459 if (rc) {
1460 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1461 goto qp_destroy;
1462 }
1463 }
1464 }
1465
1466 qp->ib_qp.qp_num = qp->qplib_qp.id;
1467 if (qp_init_attr->qp_type == IB_QPT_GSI)
1468 rdev->gsi_ctx.gsi_qp = qp;
1469 spin_lock_init(&qp->sq_lock);
1470 spin_lock_init(&qp->rq_lock);
1471 INIT_LIST_HEAD(&qp->list);
1472 mutex_lock(&rdev->qp_lock);
1473 list_add_tail(&qp->list, &rdev->qp_list);
1474 mutex_unlock(&rdev->qp_lock);
1475 atomic_inc(&rdev->qp_count);
1476
1477 return 0;
1478 qp_destroy:
1479 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1480 free_umem:
1481 ib_umem_release(qp->rumem);
1482 ib_umem_release(qp->sumem);
1483 fail:
1484 return rc;
1485 }
1486
__from_ib_qp_state(enum ib_qp_state state)1487 static u8 __from_ib_qp_state(enum ib_qp_state state)
1488 {
1489 switch (state) {
1490 case IB_QPS_RESET:
1491 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1492 case IB_QPS_INIT:
1493 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1494 case IB_QPS_RTR:
1495 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1496 case IB_QPS_RTS:
1497 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1498 case IB_QPS_SQD:
1499 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1500 case IB_QPS_SQE:
1501 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1502 case IB_QPS_ERR:
1503 default:
1504 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1505 }
1506 }
1507
__to_ib_qp_state(u8 state)1508 static enum ib_qp_state __to_ib_qp_state(u8 state)
1509 {
1510 switch (state) {
1511 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1512 return IB_QPS_RESET;
1513 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1514 return IB_QPS_INIT;
1515 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1516 return IB_QPS_RTR;
1517 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1518 return IB_QPS_RTS;
1519 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1520 return IB_QPS_SQD;
1521 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1522 return IB_QPS_SQE;
1523 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1524 default:
1525 return IB_QPS_ERR;
1526 }
1527 }
1528
__from_ib_mtu(enum ib_mtu mtu)1529 static u32 __from_ib_mtu(enum ib_mtu mtu)
1530 {
1531 switch (mtu) {
1532 case IB_MTU_256:
1533 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1534 case IB_MTU_512:
1535 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1536 case IB_MTU_1024:
1537 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1538 case IB_MTU_2048:
1539 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1540 case IB_MTU_4096:
1541 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1542 default:
1543 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1544 }
1545 }
1546
__to_ib_mtu(u32 mtu)1547 static enum ib_mtu __to_ib_mtu(u32 mtu)
1548 {
1549 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1550 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1551 return IB_MTU_256;
1552 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1553 return IB_MTU_512;
1554 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1555 return IB_MTU_1024;
1556 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1557 return IB_MTU_2048;
1558 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1559 return IB_MTU_4096;
1560 default:
1561 return IB_MTU_2048;
1562 }
1563 }
1564
1565 /* Shared Receive Queues */
bnxt_re_destroy_srq(struct ib_srq * ib_srq,struct ib_udata * udata)1566 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1567 {
1568 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1569 ib_srq);
1570 struct bnxt_re_dev *rdev = srq->rdev;
1571 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1572 struct bnxt_qplib_nq *nq = NULL;
1573
1574 if (qplib_srq->cq)
1575 nq = qplib_srq->cq->nq;
1576 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1577 ib_umem_release(srq->umem);
1578 atomic_dec(&rdev->srq_count);
1579 if (nq)
1580 nq->budget--;
1581 return 0;
1582 }
1583
bnxt_re_init_user_srq(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_srq * srq,struct ib_udata * udata)1584 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1585 struct bnxt_re_pd *pd,
1586 struct bnxt_re_srq *srq,
1587 struct ib_udata *udata)
1588 {
1589 struct bnxt_re_srq_req ureq;
1590 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1591 struct ib_umem *umem;
1592 int bytes = 0;
1593 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1594 udata, struct bnxt_re_ucontext, ib_uctx);
1595
1596 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1597 return -EFAULT;
1598
1599 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1600 bytes = PAGE_ALIGN(bytes);
1601 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1602 IB_ACCESS_LOCAL_WRITE);
1603 if (IS_ERR(umem))
1604 return PTR_ERR(umem);
1605
1606 srq->umem = umem;
1607 qplib_srq->sg_info.umem = umem;
1608 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1609 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1610 qplib_srq->srq_handle = ureq.srq_handle;
1611 qplib_srq->dpi = &cntx->dpi;
1612
1613 return 0;
1614 }
1615
bnxt_re_create_srq(struct ib_srq * ib_srq,struct ib_srq_init_attr * srq_init_attr,struct ib_udata * udata)1616 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1617 struct ib_srq_init_attr *srq_init_attr,
1618 struct ib_udata *udata)
1619 {
1620 struct bnxt_qplib_dev_attr *dev_attr;
1621 struct bnxt_qplib_nq *nq = NULL;
1622 struct bnxt_re_dev *rdev;
1623 struct bnxt_re_srq *srq;
1624 struct bnxt_re_pd *pd;
1625 struct ib_pd *ib_pd;
1626 int rc, entries;
1627
1628 ib_pd = ib_srq->pd;
1629 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1630 rdev = pd->rdev;
1631 dev_attr = &rdev->dev_attr;
1632 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1633
1634 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1635 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1636 rc = -EINVAL;
1637 goto exit;
1638 }
1639
1640 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1641 rc = -EOPNOTSUPP;
1642 goto exit;
1643 }
1644
1645 srq->rdev = rdev;
1646 srq->qplib_srq.pd = &pd->qplib_pd;
1647 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1648 /* Allocate 1 more than what's provided so posting max doesn't
1649 * mean empty
1650 */
1651 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1652 if (entries > dev_attr->max_srq_wqes + 1)
1653 entries = dev_attr->max_srq_wqes + 1;
1654 srq->qplib_srq.max_wqe = entries;
1655
1656 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1657 /* 128 byte wqe size for SRQ . So use max sges */
1658 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1659 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1660 srq->srq_limit = srq_init_attr->attr.srq_limit;
1661 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1662 nq = &rdev->nq[0];
1663
1664 if (udata) {
1665 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1666 if (rc)
1667 goto fail;
1668 }
1669
1670 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1671 if (rc) {
1672 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1673 goto fail;
1674 }
1675
1676 if (udata) {
1677 struct bnxt_re_srq_resp resp;
1678
1679 resp.srqid = srq->qplib_srq.id;
1680 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1681 if (rc) {
1682 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1683 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1684 &srq->qplib_srq);
1685 goto fail;
1686 }
1687 }
1688 if (nq)
1689 nq->budget++;
1690 atomic_inc(&rdev->srq_count);
1691 spin_lock_init(&srq->lock);
1692
1693 return 0;
1694
1695 fail:
1696 ib_umem_release(srq->umem);
1697 exit:
1698 return rc;
1699 }
1700
bnxt_re_modify_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)1701 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1702 enum ib_srq_attr_mask srq_attr_mask,
1703 struct ib_udata *udata)
1704 {
1705 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1706 ib_srq);
1707 struct bnxt_re_dev *rdev = srq->rdev;
1708 int rc;
1709
1710 switch (srq_attr_mask) {
1711 case IB_SRQ_MAX_WR:
1712 /* SRQ resize is not supported */
1713 return -EINVAL;
1714 case IB_SRQ_LIMIT:
1715 /* Change the SRQ threshold */
1716 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1717 return -EINVAL;
1718
1719 srq->qplib_srq.threshold = srq_attr->srq_limit;
1720 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1721 if (rc) {
1722 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1723 return rc;
1724 }
1725 /* On success, update the shadow */
1726 srq->srq_limit = srq_attr->srq_limit;
1727 /* No need to Build and send response back to udata */
1728 return 0;
1729 default:
1730 ibdev_err(&rdev->ibdev,
1731 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1732 return -EINVAL;
1733 }
1734 }
1735
bnxt_re_query_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr)1736 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1737 {
1738 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1739 ib_srq);
1740 struct bnxt_re_srq tsrq;
1741 struct bnxt_re_dev *rdev = srq->rdev;
1742 int rc;
1743
1744 /* Get live SRQ attr */
1745 tsrq.qplib_srq.id = srq->qplib_srq.id;
1746 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1747 if (rc) {
1748 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1749 return rc;
1750 }
1751 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1752 srq_attr->max_sge = srq->qplib_srq.max_sge;
1753 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1754
1755 return 0;
1756 }
1757
bnxt_re_post_srq_recv(struct ib_srq * ib_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1758 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1759 const struct ib_recv_wr **bad_wr)
1760 {
1761 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1762 ib_srq);
1763 struct bnxt_qplib_swqe wqe;
1764 unsigned long flags;
1765 int rc = 0;
1766
1767 spin_lock_irqsave(&srq->lock, flags);
1768 while (wr) {
1769 /* Transcribe each ib_recv_wr to qplib_swqe */
1770 wqe.num_sge = wr->num_sge;
1771 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1772 wqe.wr_id = wr->wr_id;
1773 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1774
1775 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1776 if (rc) {
1777 *bad_wr = wr;
1778 break;
1779 }
1780 wr = wr->next;
1781 }
1782 spin_unlock_irqrestore(&srq->lock, flags);
1783
1784 return rc;
1785 }
bnxt_re_modify_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp1_qp,int qp_attr_mask)1786 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1787 struct bnxt_re_qp *qp1_qp,
1788 int qp_attr_mask)
1789 {
1790 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1791 int rc = 0;
1792
1793 if (qp_attr_mask & IB_QP_STATE) {
1794 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1795 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1796 }
1797 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1798 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1799 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1800 }
1801
1802 if (qp_attr_mask & IB_QP_QKEY) {
1803 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1804 /* Using a Random QKEY */
1805 qp->qplib_qp.qkey = 0x81818181;
1806 }
1807 if (qp_attr_mask & IB_QP_SQ_PSN) {
1808 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1809 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1810 }
1811
1812 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1813 if (rc)
1814 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1815 return rc;
1816 }
1817
bnxt_re_modify_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_udata * udata)1818 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1819 int qp_attr_mask, struct ib_udata *udata)
1820 {
1821 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1822 struct bnxt_re_dev *rdev = qp->rdev;
1823 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1824 enum ib_qp_state curr_qp_state, new_qp_state;
1825 int rc, entries;
1826 unsigned int flags;
1827 u8 nw_type;
1828
1829 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1830 return -EOPNOTSUPP;
1831
1832 qp->qplib_qp.modify_flags = 0;
1833 if (qp_attr_mask & IB_QP_STATE) {
1834 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1835 new_qp_state = qp_attr->qp_state;
1836 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1837 ib_qp->qp_type, qp_attr_mask)) {
1838 ibdev_err(&rdev->ibdev,
1839 "Invalid attribute mask: %#x specified ",
1840 qp_attr_mask);
1841 ibdev_err(&rdev->ibdev,
1842 "for qpn: %#x type: %#x",
1843 ib_qp->qp_num, ib_qp->qp_type);
1844 ibdev_err(&rdev->ibdev,
1845 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1846 curr_qp_state, new_qp_state);
1847 return -EINVAL;
1848 }
1849 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1850 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1851
1852 if (!qp->sumem &&
1853 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1854 ibdev_dbg(&rdev->ibdev,
1855 "Move QP = %p to flush list\n", qp);
1856 flags = bnxt_re_lock_cqs(qp);
1857 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1858 bnxt_re_unlock_cqs(qp, flags);
1859 }
1860 if (!qp->sumem &&
1861 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1862 ibdev_dbg(&rdev->ibdev,
1863 "Move QP = %p out of flush list\n", qp);
1864 flags = bnxt_re_lock_cqs(qp);
1865 bnxt_qplib_clean_qp(&qp->qplib_qp);
1866 bnxt_re_unlock_cqs(qp, flags);
1867 }
1868 }
1869 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1870 qp->qplib_qp.modify_flags |=
1871 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1872 qp->qplib_qp.en_sqd_async_notify = true;
1873 }
1874 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1875 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1876 qp->qplib_qp.access =
1877 __from_ib_access_flags(qp_attr->qp_access_flags);
1878 /* LOCAL_WRITE access must be set to allow RC receive */
1879 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1880 /* Temp: Set all params on QP as of now */
1881 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1882 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1883 }
1884 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1885 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1886 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1887 }
1888 if (qp_attr_mask & IB_QP_QKEY) {
1889 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1890 qp->qplib_qp.qkey = qp_attr->qkey;
1891 }
1892 if (qp_attr_mask & IB_QP_AV) {
1893 const struct ib_global_route *grh =
1894 rdma_ah_read_grh(&qp_attr->ah_attr);
1895 const struct ib_gid_attr *sgid_attr;
1896 struct bnxt_re_gid_ctx *ctx;
1897
1898 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1899 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1900 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1901 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1902 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1903 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1904 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1905 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1906 sizeof(qp->qplib_qp.ah.dgid.data));
1907 qp->qplib_qp.ah.flow_label = grh->flow_label;
1908 sgid_attr = grh->sgid_attr;
1909 /* Get the HW context of the GID. The reference
1910 * of GID table entry is already taken by the caller.
1911 */
1912 ctx = rdma_read_gid_hw_context(sgid_attr);
1913 qp->qplib_qp.ah.sgid_index = ctx->idx;
1914 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1915 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1916 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1917 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1918 ether_addr_copy(qp->qplib_qp.ah.dmac,
1919 qp_attr->ah_attr.roce.dmac);
1920
1921 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1922 &qp->qplib_qp.smac[0]);
1923 if (rc)
1924 return rc;
1925
1926 nw_type = rdma_gid_attr_network_type(sgid_attr);
1927 switch (nw_type) {
1928 case RDMA_NETWORK_IPV4:
1929 qp->qplib_qp.nw_type =
1930 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1931 break;
1932 case RDMA_NETWORK_IPV6:
1933 qp->qplib_qp.nw_type =
1934 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1935 break;
1936 default:
1937 qp->qplib_qp.nw_type =
1938 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1939 break;
1940 }
1941 }
1942
1943 if (qp_attr_mask & IB_QP_PATH_MTU) {
1944 qp->qplib_qp.modify_flags |=
1945 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1946 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1947 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1948 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1949 qp->qplib_qp.modify_flags |=
1950 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1951 qp->qplib_qp.path_mtu =
1952 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1953 qp->qplib_qp.mtu =
1954 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1955 }
1956
1957 if (qp_attr_mask & IB_QP_TIMEOUT) {
1958 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1959 qp->qplib_qp.timeout = qp_attr->timeout;
1960 }
1961 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1962 qp->qplib_qp.modify_flags |=
1963 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1964 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1965 }
1966 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1967 qp->qplib_qp.modify_flags |=
1968 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1969 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1970 }
1971 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1972 qp->qplib_qp.modify_flags |=
1973 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1974 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1975 }
1976 if (qp_attr_mask & IB_QP_RQ_PSN) {
1977 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1978 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1979 }
1980 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1981 qp->qplib_qp.modify_flags |=
1982 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1983 /* Cap the max_rd_atomic to device max */
1984 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1985 dev_attr->max_qp_rd_atom);
1986 }
1987 if (qp_attr_mask & IB_QP_SQ_PSN) {
1988 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1989 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1990 }
1991 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1992 if (qp_attr->max_dest_rd_atomic >
1993 dev_attr->max_qp_init_rd_atom) {
1994 ibdev_err(&rdev->ibdev,
1995 "max_dest_rd_atomic requested%d is > dev_max%d",
1996 qp_attr->max_dest_rd_atomic,
1997 dev_attr->max_qp_init_rd_atom);
1998 return -EINVAL;
1999 }
2000
2001 qp->qplib_qp.modify_flags |=
2002 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2003 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2004 }
2005 if (qp_attr_mask & IB_QP_CAP) {
2006 qp->qplib_qp.modify_flags |=
2007 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2008 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2009 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2010 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2011 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2012 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2013 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2014 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2015 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2016 (qp_attr->cap.max_inline_data >=
2017 dev_attr->max_inline_data)) {
2018 ibdev_err(&rdev->ibdev,
2019 "Create QP failed - max exceeded");
2020 return -EINVAL;
2021 }
2022 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
2023 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2024 dev_attr->max_qp_wqes + 1);
2025 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2026 qp_attr->cap.max_send_wr;
2027 /*
2028 * Reserving one slot for Phantom WQE. Some application can
2029 * post one extra entry in this case. Allowing this to avoid
2030 * unexpected Queue full condition
2031 */
2032 qp->qplib_qp.sq.q_full_delta -= 1;
2033 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2034 if (qp->qplib_qp.rq.max_wqe) {
2035 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
2036 qp->qplib_qp.rq.max_wqe =
2037 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2038 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2039 qp_attr->cap.max_recv_wr;
2040 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2041 } else {
2042 /* SRQ was used prior, just ignore the RQ caps */
2043 }
2044 }
2045 if (qp_attr_mask & IB_QP_DEST_QPN) {
2046 qp->qplib_qp.modify_flags |=
2047 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2048 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2049 }
2050 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2051 if (rc) {
2052 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2053 return rc;
2054 }
2055 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2056 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2057 return rc;
2058 }
2059
bnxt_re_query_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)2060 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2061 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2062 {
2063 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2064 struct bnxt_re_dev *rdev = qp->rdev;
2065 struct bnxt_qplib_qp *qplib_qp;
2066 int rc;
2067
2068 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2069 if (!qplib_qp)
2070 return -ENOMEM;
2071
2072 qplib_qp->id = qp->qplib_qp.id;
2073 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2074
2075 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2076 if (rc) {
2077 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2078 goto out;
2079 }
2080 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2081 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2082 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2083 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2084 qp_attr->pkey_index = qplib_qp->pkey_index;
2085 qp_attr->qkey = qplib_qp->qkey;
2086 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2087 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2088 qplib_qp->ah.host_sgid_index,
2089 qplib_qp->ah.hop_limit,
2090 qplib_qp->ah.traffic_class);
2091 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2092 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2093 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2094 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2095 qp_attr->timeout = qplib_qp->timeout;
2096 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2097 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2098 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2099 qp_attr->rq_psn = qplib_qp->rq.psn;
2100 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2101 qp_attr->sq_psn = qplib_qp->sq.psn;
2102 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2103 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2104 IB_SIGNAL_REQ_WR;
2105 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2106
2107 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2108 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2109 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2110 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2111 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2112 qp_init_attr->cap = qp_attr->cap;
2113
2114 out:
2115 kfree(qplib_qp);
2116 return rc;
2117 }
2118
2119 /* Routine for sending QP1 packets for RoCE V1 an V2
2120 */
bnxt_re_build_qp1_send_v2(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2121 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2122 const struct ib_send_wr *wr,
2123 struct bnxt_qplib_swqe *wqe,
2124 int payload_size)
2125 {
2126 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2127 ib_ah);
2128 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2129 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2130 struct bnxt_qplib_sge sge;
2131 u8 nw_type;
2132 u16 ether_type;
2133 union ib_gid dgid;
2134 bool is_eth = false;
2135 bool is_vlan = false;
2136 bool is_grh = false;
2137 bool is_udp = false;
2138 u8 ip_version = 0;
2139 u16 vlan_id = 0xFFFF;
2140 void *buf;
2141 int i, rc = 0;
2142
2143 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2144
2145 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2146 if (rc)
2147 return rc;
2148
2149 /* Get network header type for this GID */
2150 nw_type = rdma_gid_attr_network_type(sgid_attr);
2151 switch (nw_type) {
2152 case RDMA_NETWORK_IPV4:
2153 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2154 break;
2155 case RDMA_NETWORK_IPV6:
2156 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2157 break;
2158 default:
2159 nw_type = BNXT_RE_ROCE_V1_PACKET;
2160 break;
2161 }
2162 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2163 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2164 if (is_udp) {
2165 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2166 ip_version = 4;
2167 ether_type = ETH_P_IP;
2168 } else {
2169 ip_version = 6;
2170 ether_type = ETH_P_IPV6;
2171 }
2172 is_grh = false;
2173 } else {
2174 ether_type = ETH_P_IBOE;
2175 is_grh = true;
2176 }
2177
2178 is_eth = true;
2179 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2180
2181 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2182 ip_version, is_udp, 0, &qp->qp1_hdr);
2183
2184 /* ETH */
2185 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2186 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2187
2188 /* For vlan, check the sgid for vlan existence */
2189
2190 if (!is_vlan) {
2191 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2192 } else {
2193 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2194 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2195 }
2196
2197 if (is_grh || (ip_version == 6)) {
2198 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2199 sizeof(sgid_attr->gid));
2200 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2201 sizeof(sgid_attr->gid));
2202 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2203 }
2204
2205 if (ip_version == 4) {
2206 qp->qp1_hdr.ip4.tos = 0;
2207 qp->qp1_hdr.ip4.id = 0;
2208 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2209 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2210
2211 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2212 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2213 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2214 }
2215
2216 if (is_udp) {
2217 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2218 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2219 qp->qp1_hdr.udp.csum = 0;
2220 }
2221
2222 /* BTH */
2223 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2224 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2225 qp->qp1_hdr.immediate_present = 1;
2226 } else {
2227 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2228 }
2229 if (wr->send_flags & IB_SEND_SOLICITED)
2230 qp->qp1_hdr.bth.solicited_event = 1;
2231 /* pad_count */
2232 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2233
2234 /* P_key for QP1 is for all members */
2235 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2236 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2237 qp->qp1_hdr.bth.ack_req = 0;
2238 qp->send_psn++;
2239 qp->send_psn &= BTH_PSN_MASK;
2240 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2241 /* DETH */
2242 /* Use the priviledged Q_Key for QP1 */
2243 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2244 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2245
2246 /* Pack the QP1 to the transmit buffer */
2247 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2248 if (buf) {
2249 ib_ud_header_pack(&qp->qp1_hdr, buf);
2250 for (i = wqe->num_sge; i; i--) {
2251 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2252 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2253 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2254 }
2255
2256 /*
2257 * Max Header buf size for IPV6 RoCE V2 is 86,
2258 * which is same as the QP1 SQ header buffer.
2259 * Header buf size for IPV4 RoCE V2 can be 66.
2260 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2261 * Subtract 20 bytes from QP1 SQ header buf size
2262 */
2263 if (is_udp && ip_version == 4)
2264 sge.size -= 20;
2265 /*
2266 * Max Header buf size for RoCE V1 is 78.
2267 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2268 * Subtract 8 bytes from QP1 SQ header buf size
2269 */
2270 if (!is_udp)
2271 sge.size -= 8;
2272
2273 /* Subtract 4 bytes for non vlan packets */
2274 if (!is_vlan)
2275 sge.size -= 4;
2276
2277 wqe->sg_list[0].addr = sge.addr;
2278 wqe->sg_list[0].lkey = sge.lkey;
2279 wqe->sg_list[0].size = sge.size;
2280 wqe->num_sge++;
2281
2282 } else {
2283 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2284 rc = -ENOMEM;
2285 }
2286 return rc;
2287 }
2288
2289 /* For the MAD layer, it only provides the recv SGE the size of
2290 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2291 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2292 * receive packet (334 bytes) with no VLAN and then copy the GRH
2293 * and the MAD datagram out to the provided SGE.
2294 */
bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp * qp,const struct ib_recv_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2295 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2296 const struct ib_recv_wr *wr,
2297 struct bnxt_qplib_swqe *wqe,
2298 int payload_size)
2299 {
2300 struct bnxt_re_sqp_entries *sqp_entry;
2301 struct bnxt_qplib_sge ref, sge;
2302 struct bnxt_re_dev *rdev;
2303 u32 rq_prod_index;
2304
2305 rdev = qp->rdev;
2306
2307 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2308
2309 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2310 return -ENOMEM;
2311
2312 /* Create 1 SGE to receive the entire
2313 * ethernet packet
2314 */
2315 /* Save the reference from ULP */
2316 ref.addr = wqe->sg_list[0].addr;
2317 ref.lkey = wqe->sg_list[0].lkey;
2318 ref.size = wqe->sg_list[0].size;
2319
2320 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2321
2322 /* SGE 1 */
2323 wqe->sg_list[0].addr = sge.addr;
2324 wqe->sg_list[0].lkey = sge.lkey;
2325 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2326 sge.size -= wqe->sg_list[0].size;
2327
2328 sqp_entry->sge.addr = ref.addr;
2329 sqp_entry->sge.lkey = ref.lkey;
2330 sqp_entry->sge.size = ref.size;
2331 /* Store the wrid for reporting completion */
2332 sqp_entry->wrid = wqe->wr_id;
2333 /* change the wqe->wrid to table index */
2334 wqe->wr_id = rq_prod_index;
2335 return 0;
2336 }
2337
is_ud_qp(struct bnxt_re_qp * qp)2338 static int is_ud_qp(struct bnxt_re_qp *qp)
2339 {
2340 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2341 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2342 }
2343
bnxt_re_build_send_wqe(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2344 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2345 const struct ib_send_wr *wr,
2346 struct bnxt_qplib_swqe *wqe)
2347 {
2348 struct bnxt_re_ah *ah = NULL;
2349
2350 if (is_ud_qp(qp)) {
2351 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2352 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2353 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2354 wqe->send.avid = ah->qplib_ah.id;
2355 }
2356 switch (wr->opcode) {
2357 case IB_WR_SEND:
2358 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2359 break;
2360 case IB_WR_SEND_WITH_IMM:
2361 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2362 wqe->send.imm_data = wr->ex.imm_data;
2363 break;
2364 case IB_WR_SEND_WITH_INV:
2365 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2366 wqe->send.inv_key = wr->ex.invalidate_rkey;
2367 break;
2368 default:
2369 return -EINVAL;
2370 }
2371 if (wr->send_flags & IB_SEND_SIGNALED)
2372 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2373 if (wr->send_flags & IB_SEND_FENCE)
2374 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2375 if (wr->send_flags & IB_SEND_SOLICITED)
2376 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2377 if (wr->send_flags & IB_SEND_INLINE)
2378 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2379
2380 return 0;
2381 }
2382
bnxt_re_build_rdma_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2383 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2384 struct bnxt_qplib_swqe *wqe)
2385 {
2386 switch (wr->opcode) {
2387 case IB_WR_RDMA_WRITE:
2388 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2389 break;
2390 case IB_WR_RDMA_WRITE_WITH_IMM:
2391 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2392 wqe->rdma.imm_data = wr->ex.imm_data;
2393 break;
2394 case IB_WR_RDMA_READ:
2395 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2396 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2397 break;
2398 default:
2399 return -EINVAL;
2400 }
2401 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2402 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2403 if (wr->send_flags & IB_SEND_SIGNALED)
2404 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2405 if (wr->send_flags & IB_SEND_FENCE)
2406 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2407 if (wr->send_flags & IB_SEND_SOLICITED)
2408 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2409 if (wr->send_flags & IB_SEND_INLINE)
2410 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2411
2412 return 0;
2413 }
2414
bnxt_re_build_atomic_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2415 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2416 struct bnxt_qplib_swqe *wqe)
2417 {
2418 switch (wr->opcode) {
2419 case IB_WR_ATOMIC_CMP_AND_SWP:
2420 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2421 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2422 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2423 break;
2424 case IB_WR_ATOMIC_FETCH_AND_ADD:
2425 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2426 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2427 break;
2428 default:
2429 return -EINVAL;
2430 }
2431 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2432 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2433 if (wr->send_flags & IB_SEND_SIGNALED)
2434 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2435 if (wr->send_flags & IB_SEND_FENCE)
2436 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2437 if (wr->send_flags & IB_SEND_SOLICITED)
2438 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2439 return 0;
2440 }
2441
bnxt_re_build_inv_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2442 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2443 struct bnxt_qplib_swqe *wqe)
2444 {
2445 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2446 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2447
2448 /* Need unconditional fence for local invalidate
2449 * opcode to work as expected.
2450 */
2451 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2452
2453 if (wr->send_flags & IB_SEND_SIGNALED)
2454 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2455 if (wr->send_flags & IB_SEND_SOLICITED)
2456 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2457
2458 return 0;
2459 }
2460
bnxt_re_build_reg_wqe(const struct ib_reg_wr * wr,struct bnxt_qplib_swqe * wqe)2461 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2462 struct bnxt_qplib_swqe *wqe)
2463 {
2464 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2465 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2466 int access = wr->access;
2467
2468 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2469 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2470 wqe->frmr.page_list = mr->pages;
2471 wqe->frmr.page_list_len = mr->npages;
2472 wqe->frmr.levels = qplib_frpl->hwq.level;
2473 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2474
2475 /* Need unconditional fence for reg_mr
2476 * opcode to function as expected.
2477 */
2478
2479 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2480
2481 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2482 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2483
2484 if (access & IB_ACCESS_LOCAL_WRITE)
2485 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2486 if (access & IB_ACCESS_REMOTE_READ)
2487 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2488 if (access & IB_ACCESS_REMOTE_WRITE)
2489 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2490 if (access & IB_ACCESS_REMOTE_ATOMIC)
2491 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2492 if (access & IB_ACCESS_MW_BIND)
2493 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2494
2495 wqe->frmr.l_key = wr->key;
2496 wqe->frmr.length = wr->mr->length;
2497 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2498 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2499 wqe->frmr.va = wr->mr->iova;
2500 return 0;
2501 }
2502
bnxt_re_copy_inline_data(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2503 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2504 const struct ib_send_wr *wr,
2505 struct bnxt_qplib_swqe *wqe)
2506 {
2507 /* Copy the inline data to the data field */
2508 u8 *in_data;
2509 u32 i, sge_len;
2510 void *sge_addr;
2511
2512 in_data = wqe->inline_data;
2513 for (i = 0; i < wr->num_sge; i++) {
2514 sge_addr = (void *)(unsigned long)
2515 wr->sg_list[i].addr;
2516 sge_len = wr->sg_list[i].length;
2517
2518 if ((sge_len + wqe->inline_len) >
2519 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2520 ibdev_err(&rdev->ibdev,
2521 "Inline data size requested > supported value");
2522 return -EINVAL;
2523 }
2524 sge_len = wr->sg_list[i].length;
2525
2526 memcpy(in_data, sge_addr, sge_len);
2527 in_data += wr->sg_list[i].length;
2528 wqe->inline_len += wr->sg_list[i].length;
2529 }
2530 return wqe->inline_len;
2531 }
2532
bnxt_re_copy_wr_payload(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2533 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2534 const struct ib_send_wr *wr,
2535 struct bnxt_qplib_swqe *wqe)
2536 {
2537 int payload_sz = 0;
2538
2539 if (wr->send_flags & IB_SEND_INLINE)
2540 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2541 else
2542 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2543 wqe->num_sge);
2544
2545 return payload_sz;
2546 }
2547
bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp * qp)2548 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2549 {
2550 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2551 qp->ib_qp.qp_type == IB_QPT_GSI ||
2552 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2553 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2554 int qp_attr_mask;
2555 struct ib_qp_attr qp_attr;
2556
2557 qp_attr_mask = IB_QP_STATE;
2558 qp_attr.qp_state = IB_QPS_RTS;
2559 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2560 qp->qplib_qp.wqe_cnt = 0;
2561 }
2562 }
2563
bnxt_re_post_send_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_send_wr * wr)2564 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2565 struct bnxt_re_qp *qp,
2566 const struct ib_send_wr *wr)
2567 {
2568 int rc = 0, payload_sz = 0;
2569 unsigned long flags;
2570
2571 spin_lock_irqsave(&qp->sq_lock, flags);
2572 while (wr) {
2573 struct bnxt_qplib_swqe wqe = {};
2574
2575 /* Common */
2576 wqe.num_sge = wr->num_sge;
2577 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2578 ibdev_err(&rdev->ibdev,
2579 "Limit exceeded for Send SGEs");
2580 rc = -EINVAL;
2581 goto bad;
2582 }
2583
2584 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2585 if (payload_sz < 0) {
2586 rc = -EINVAL;
2587 goto bad;
2588 }
2589 wqe.wr_id = wr->wr_id;
2590
2591 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2592
2593 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2594 if (!rc)
2595 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2596 bad:
2597 if (rc) {
2598 ibdev_err(&rdev->ibdev,
2599 "Post send failed opcode = %#x rc = %d",
2600 wr->opcode, rc);
2601 break;
2602 }
2603 wr = wr->next;
2604 }
2605 bnxt_qplib_post_send_db(&qp->qplib_qp);
2606 bnxt_ud_qp_hw_stall_workaround(qp);
2607 spin_unlock_irqrestore(&qp->sq_lock, flags);
2608 return rc;
2609 }
2610
bnxt_re_post_send(struct ib_qp * ib_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)2611 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2612 const struct ib_send_wr **bad_wr)
2613 {
2614 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2615 struct bnxt_qplib_swqe wqe;
2616 int rc = 0, payload_sz = 0;
2617 unsigned long flags;
2618
2619 spin_lock_irqsave(&qp->sq_lock, flags);
2620 while (wr) {
2621 /* House keeping */
2622 memset(&wqe, 0, sizeof(wqe));
2623
2624 /* Common */
2625 wqe.num_sge = wr->num_sge;
2626 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2627 ibdev_err(&qp->rdev->ibdev,
2628 "Limit exceeded for Send SGEs");
2629 rc = -EINVAL;
2630 goto bad;
2631 }
2632
2633 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2634 if (payload_sz < 0) {
2635 rc = -EINVAL;
2636 goto bad;
2637 }
2638 wqe.wr_id = wr->wr_id;
2639
2640 switch (wr->opcode) {
2641 case IB_WR_SEND:
2642 case IB_WR_SEND_WITH_IMM:
2643 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2644 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2645 payload_sz);
2646 if (rc)
2647 goto bad;
2648 wqe.rawqp1.lflags |=
2649 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2650 }
2651 switch (wr->send_flags) {
2652 case IB_SEND_IP_CSUM:
2653 wqe.rawqp1.lflags |=
2654 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2655 break;
2656 default:
2657 break;
2658 }
2659 fallthrough;
2660 case IB_WR_SEND_WITH_INV:
2661 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2662 break;
2663 case IB_WR_RDMA_WRITE:
2664 case IB_WR_RDMA_WRITE_WITH_IMM:
2665 case IB_WR_RDMA_READ:
2666 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2667 break;
2668 case IB_WR_ATOMIC_CMP_AND_SWP:
2669 case IB_WR_ATOMIC_FETCH_AND_ADD:
2670 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2671 break;
2672 case IB_WR_RDMA_READ_WITH_INV:
2673 ibdev_err(&qp->rdev->ibdev,
2674 "RDMA Read with Invalidate is not supported");
2675 rc = -EINVAL;
2676 goto bad;
2677 case IB_WR_LOCAL_INV:
2678 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2679 break;
2680 case IB_WR_REG_MR:
2681 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2682 break;
2683 default:
2684 /* Unsupported WRs */
2685 ibdev_err(&qp->rdev->ibdev,
2686 "WR (%#x) is not supported", wr->opcode);
2687 rc = -EINVAL;
2688 goto bad;
2689 }
2690 if (!rc)
2691 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2692 bad:
2693 if (rc) {
2694 ibdev_err(&qp->rdev->ibdev,
2695 "post_send failed op:%#x qps = %#x rc = %d\n",
2696 wr->opcode, qp->qplib_qp.state, rc);
2697 *bad_wr = wr;
2698 break;
2699 }
2700 wr = wr->next;
2701 }
2702 bnxt_qplib_post_send_db(&qp->qplib_qp);
2703 bnxt_ud_qp_hw_stall_workaround(qp);
2704 spin_unlock_irqrestore(&qp->sq_lock, flags);
2705
2706 return rc;
2707 }
2708
bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_recv_wr * wr)2709 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2710 struct bnxt_re_qp *qp,
2711 const struct ib_recv_wr *wr)
2712 {
2713 struct bnxt_qplib_swqe wqe;
2714 int rc = 0;
2715
2716 memset(&wqe, 0, sizeof(wqe));
2717 while (wr) {
2718 /* House keeping */
2719 memset(&wqe, 0, sizeof(wqe));
2720
2721 /* Common */
2722 wqe.num_sge = wr->num_sge;
2723 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2724 ibdev_err(&rdev->ibdev,
2725 "Limit exceeded for Receive SGEs");
2726 rc = -EINVAL;
2727 break;
2728 }
2729 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2730 wqe.wr_id = wr->wr_id;
2731 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2732
2733 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2734 if (rc)
2735 break;
2736
2737 wr = wr->next;
2738 }
2739 if (!rc)
2740 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2741 return rc;
2742 }
2743
bnxt_re_post_recv(struct ib_qp * ib_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2744 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2745 const struct ib_recv_wr **bad_wr)
2746 {
2747 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2748 struct bnxt_qplib_swqe wqe;
2749 int rc = 0, payload_sz = 0;
2750 unsigned long flags;
2751 u32 count = 0;
2752
2753 spin_lock_irqsave(&qp->rq_lock, flags);
2754 while (wr) {
2755 /* House keeping */
2756 memset(&wqe, 0, sizeof(wqe));
2757
2758 /* Common */
2759 wqe.num_sge = wr->num_sge;
2760 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2761 ibdev_err(&qp->rdev->ibdev,
2762 "Limit exceeded for Receive SGEs");
2763 rc = -EINVAL;
2764 *bad_wr = wr;
2765 break;
2766 }
2767
2768 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2769 wr->num_sge);
2770 wqe.wr_id = wr->wr_id;
2771 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2772
2773 if (ib_qp->qp_type == IB_QPT_GSI &&
2774 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2775 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2776 payload_sz);
2777 if (!rc)
2778 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2779 if (rc) {
2780 *bad_wr = wr;
2781 break;
2782 }
2783
2784 /* Ring DB if the RQEs posted reaches a threshold value */
2785 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2786 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2787 count = 0;
2788 }
2789
2790 wr = wr->next;
2791 }
2792
2793 if (count)
2794 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2795
2796 spin_unlock_irqrestore(&qp->rq_lock, flags);
2797
2798 return rc;
2799 }
2800
2801 /* Completion Queues */
bnxt_re_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)2802 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2803 {
2804 struct bnxt_re_cq *cq;
2805 struct bnxt_qplib_nq *nq;
2806 struct bnxt_re_dev *rdev;
2807
2808 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2809 rdev = cq->rdev;
2810 nq = cq->qplib_cq.nq;
2811
2812 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2813 ib_umem_release(cq->umem);
2814
2815 atomic_dec(&rdev->cq_count);
2816 nq->budget--;
2817 kfree(cq->cql);
2818 return 0;
2819 }
2820
bnxt_re_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct ib_udata * udata)2821 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2822 struct ib_udata *udata)
2823 {
2824 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2825 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2826 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2827 int rc, entries;
2828 int cqe = attr->cqe;
2829 struct bnxt_qplib_nq *nq = NULL;
2830 unsigned int nq_alloc_cnt;
2831
2832 if (attr->flags)
2833 return -EOPNOTSUPP;
2834
2835 /* Validate CQ fields */
2836 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2837 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2838 return -EINVAL;
2839 }
2840
2841 cq->rdev = rdev;
2842 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2843
2844 entries = roundup_pow_of_two(cqe + 1);
2845 if (entries > dev_attr->max_cq_wqes + 1)
2846 entries = dev_attr->max_cq_wqes + 1;
2847
2848 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2849 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2850 if (udata) {
2851 struct bnxt_re_cq_req req;
2852 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2853 udata, struct bnxt_re_ucontext, ib_uctx);
2854 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2855 rc = -EFAULT;
2856 goto fail;
2857 }
2858
2859 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2860 entries * sizeof(struct cq_base),
2861 IB_ACCESS_LOCAL_WRITE);
2862 if (IS_ERR(cq->umem)) {
2863 rc = PTR_ERR(cq->umem);
2864 goto fail;
2865 }
2866 cq->qplib_cq.sg_info.umem = cq->umem;
2867 cq->qplib_cq.dpi = &uctx->dpi;
2868 } else {
2869 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2870 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2871 GFP_KERNEL);
2872 if (!cq->cql) {
2873 rc = -ENOMEM;
2874 goto fail;
2875 }
2876
2877 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2878 }
2879 /*
2880 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2881 * used for getting the NQ index.
2882 */
2883 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2884 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2885 cq->qplib_cq.max_wqe = entries;
2886 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2887 cq->qplib_cq.nq = nq;
2888
2889 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2890 if (rc) {
2891 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2892 goto fail;
2893 }
2894
2895 cq->ib_cq.cqe = entries;
2896 cq->cq_period = cq->qplib_cq.period;
2897 nq->budget++;
2898
2899 atomic_inc(&rdev->cq_count);
2900 spin_lock_init(&cq->cq_lock);
2901
2902 if (udata) {
2903 struct bnxt_re_cq_resp resp;
2904
2905 resp.cqid = cq->qplib_cq.id;
2906 resp.tail = cq->qplib_cq.hwq.cons;
2907 resp.phase = cq->qplib_cq.period;
2908 resp.rsvd = 0;
2909 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2910 if (rc) {
2911 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2912 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2913 goto c2fail;
2914 }
2915 }
2916
2917 return 0;
2918
2919 c2fail:
2920 ib_umem_release(cq->umem);
2921 fail:
2922 kfree(cq->cql);
2923 return rc;
2924 }
2925
__req_to_ib_wc_status(u8 qstatus)2926 static u8 __req_to_ib_wc_status(u8 qstatus)
2927 {
2928 switch (qstatus) {
2929 case CQ_REQ_STATUS_OK:
2930 return IB_WC_SUCCESS;
2931 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2932 return IB_WC_BAD_RESP_ERR;
2933 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2934 return IB_WC_LOC_LEN_ERR;
2935 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2936 return IB_WC_LOC_QP_OP_ERR;
2937 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2938 return IB_WC_LOC_PROT_ERR;
2939 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2940 return IB_WC_GENERAL_ERR;
2941 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2942 return IB_WC_REM_INV_REQ_ERR;
2943 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2944 return IB_WC_REM_ACCESS_ERR;
2945 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2946 return IB_WC_REM_OP_ERR;
2947 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2948 return IB_WC_RNR_RETRY_EXC_ERR;
2949 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2950 return IB_WC_RETRY_EXC_ERR;
2951 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2952 return IB_WC_WR_FLUSH_ERR;
2953 default:
2954 return IB_WC_GENERAL_ERR;
2955 }
2956 return 0;
2957 }
2958
__rawqp1_to_ib_wc_status(u8 qstatus)2959 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2960 {
2961 switch (qstatus) {
2962 case CQ_RES_RAWETH_QP1_STATUS_OK:
2963 return IB_WC_SUCCESS;
2964 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2965 return IB_WC_LOC_ACCESS_ERR;
2966 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2967 return IB_WC_LOC_LEN_ERR;
2968 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2969 return IB_WC_LOC_PROT_ERR;
2970 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2971 return IB_WC_LOC_QP_OP_ERR;
2972 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2973 return IB_WC_GENERAL_ERR;
2974 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2975 return IB_WC_WR_FLUSH_ERR;
2976 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2977 return IB_WC_WR_FLUSH_ERR;
2978 default:
2979 return IB_WC_GENERAL_ERR;
2980 }
2981 }
2982
__rc_to_ib_wc_status(u8 qstatus)2983 static u8 __rc_to_ib_wc_status(u8 qstatus)
2984 {
2985 switch (qstatus) {
2986 case CQ_RES_RC_STATUS_OK:
2987 return IB_WC_SUCCESS;
2988 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2989 return IB_WC_LOC_ACCESS_ERR;
2990 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2991 return IB_WC_LOC_LEN_ERR;
2992 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2993 return IB_WC_LOC_PROT_ERR;
2994 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2995 return IB_WC_LOC_QP_OP_ERR;
2996 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2997 return IB_WC_GENERAL_ERR;
2998 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2999 return IB_WC_REM_INV_REQ_ERR;
3000 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3001 return IB_WC_WR_FLUSH_ERR;
3002 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3003 return IB_WC_WR_FLUSH_ERR;
3004 default:
3005 return IB_WC_GENERAL_ERR;
3006 }
3007 }
3008
bnxt_re_process_req_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3009 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3010 {
3011 switch (cqe->type) {
3012 case BNXT_QPLIB_SWQE_TYPE_SEND:
3013 wc->opcode = IB_WC_SEND;
3014 break;
3015 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3016 wc->opcode = IB_WC_SEND;
3017 wc->wc_flags |= IB_WC_WITH_IMM;
3018 break;
3019 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3020 wc->opcode = IB_WC_SEND;
3021 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3022 break;
3023 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3024 wc->opcode = IB_WC_RDMA_WRITE;
3025 break;
3026 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3027 wc->opcode = IB_WC_RDMA_WRITE;
3028 wc->wc_flags |= IB_WC_WITH_IMM;
3029 break;
3030 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3031 wc->opcode = IB_WC_RDMA_READ;
3032 break;
3033 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3034 wc->opcode = IB_WC_COMP_SWAP;
3035 break;
3036 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3037 wc->opcode = IB_WC_FETCH_ADD;
3038 break;
3039 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3040 wc->opcode = IB_WC_LOCAL_INV;
3041 break;
3042 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3043 wc->opcode = IB_WC_REG_MR;
3044 break;
3045 default:
3046 wc->opcode = IB_WC_SEND;
3047 break;
3048 }
3049
3050 wc->status = __req_to_ib_wc_status(cqe->status);
3051 }
3052
bnxt_re_check_packet_type(u16 raweth_qp1_flags,u16 raweth_qp1_flags2)3053 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3054 u16 raweth_qp1_flags2)
3055 {
3056 bool is_ipv6 = false, is_ipv4 = false;
3057
3058 /* raweth_qp1_flags Bit 9-6 indicates itype */
3059 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3060 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3061 return -1;
3062
3063 if (raweth_qp1_flags2 &
3064 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3065 raweth_qp1_flags2 &
3066 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3067 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3068 (raweth_qp1_flags2 &
3069 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3070 (is_ipv6 = true) : (is_ipv4 = true);
3071 return ((is_ipv6) ?
3072 BNXT_RE_ROCEV2_IPV6_PACKET :
3073 BNXT_RE_ROCEV2_IPV4_PACKET);
3074 } else {
3075 return BNXT_RE_ROCE_V1_PACKET;
3076 }
3077 }
3078
bnxt_re_to_ib_nw_type(int nw_type)3079 static int bnxt_re_to_ib_nw_type(int nw_type)
3080 {
3081 u8 nw_hdr_type = 0xFF;
3082
3083 switch (nw_type) {
3084 case BNXT_RE_ROCE_V1_PACKET:
3085 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3086 break;
3087 case BNXT_RE_ROCEV2_IPV4_PACKET:
3088 nw_hdr_type = RDMA_NETWORK_IPV4;
3089 break;
3090 case BNXT_RE_ROCEV2_IPV6_PACKET:
3091 nw_hdr_type = RDMA_NETWORK_IPV6;
3092 break;
3093 }
3094 return nw_hdr_type;
3095 }
3096
bnxt_re_is_loopback_packet(struct bnxt_re_dev * rdev,void * rq_hdr_buf)3097 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3098 void *rq_hdr_buf)
3099 {
3100 u8 *tmp_buf = NULL;
3101 struct ethhdr *eth_hdr;
3102 u16 eth_type;
3103 bool rc = false;
3104
3105 tmp_buf = (u8 *)rq_hdr_buf;
3106 /*
3107 * If dest mac is not same as I/F mac, this could be a
3108 * loopback address or multicast address, check whether
3109 * it is a loopback packet
3110 */
3111 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3112 tmp_buf += 4;
3113 /* Check the ether type */
3114 eth_hdr = (struct ethhdr *)tmp_buf;
3115 eth_type = ntohs(eth_hdr->h_proto);
3116 switch (eth_type) {
3117 case ETH_P_IBOE:
3118 rc = true;
3119 break;
3120 case ETH_P_IP:
3121 case ETH_P_IPV6: {
3122 u32 len;
3123 struct udphdr *udp_hdr;
3124
3125 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3126 sizeof(struct ipv6hdr));
3127 tmp_buf += sizeof(struct ethhdr) + len;
3128 udp_hdr = (struct udphdr *)tmp_buf;
3129 if (ntohs(udp_hdr->dest) ==
3130 ROCE_V2_UDP_DPORT)
3131 rc = true;
3132 break;
3133 }
3134 default:
3135 break;
3136 }
3137 }
3138
3139 return rc;
3140 }
3141
bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp * gsi_qp,struct bnxt_qplib_cqe * cqe)3142 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3143 struct bnxt_qplib_cqe *cqe)
3144 {
3145 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3146 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3147 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3148 struct bnxt_re_ah *gsi_sah;
3149 struct ib_send_wr *swr;
3150 struct ib_ud_wr udwr;
3151 struct ib_recv_wr rwr;
3152 int pkt_type = 0;
3153 u32 tbl_idx;
3154 void *rq_hdr_buf;
3155 dma_addr_t rq_hdr_buf_map;
3156 dma_addr_t shrq_hdr_buf_map;
3157 u32 offset = 0;
3158 u32 skip_bytes = 0;
3159 struct ib_sge s_sge[2];
3160 struct ib_sge r_sge[2];
3161 int rc;
3162
3163 memset(&udwr, 0, sizeof(udwr));
3164 memset(&rwr, 0, sizeof(rwr));
3165 memset(&s_sge, 0, sizeof(s_sge));
3166 memset(&r_sge, 0, sizeof(r_sge));
3167
3168 swr = &udwr.wr;
3169 tbl_idx = cqe->wr_id;
3170
3171 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3172 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3173 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3174 tbl_idx);
3175
3176 /* Shadow QP header buffer */
3177 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3178 tbl_idx);
3179 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3180
3181 /* Store this cqe */
3182 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3183 sqp_entry->qp1_qp = gsi_qp;
3184
3185 /* Find packet type from the cqe */
3186
3187 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3188 cqe->raweth_qp1_flags2);
3189 if (pkt_type < 0) {
3190 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3191 return -EINVAL;
3192 }
3193
3194 /* Adjust the offset for the user buffer and post in the rq */
3195
3196 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3197 offset = 20;
3198
3199 /*
3200 * QP1 loopback packet has 4 bytes of internal header before
3201 * ether header. Skip these four bytes.
3202 */
3203 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3204 skip_bytes = 4;
3205
3206 /* First send SGE . Skip the ether header*/
3207 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3208 + skip_bytes;
3209 s_sge[0].lkey = 0xFFFFFFFF;
3210 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3211 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3212
3213 /* Second Send SGE */
3214 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3215 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3216 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3217 s_sge[1].addr += 8;
3218 s_sge[1].lkey = 0xFFFFFFFF;
3219 s_sge[1].length = 256;
3220
3221 /* First recv SGE */
3222
3223 r_sge[0].addr = shrq_hdr_buf_map;
3224 r_sge[0].lkey = 0xFFFFFFFF;
3225 r_sge[0].length = 40;
3226
3227 r_sge[1].addr = sqp_entry->sge.addr + offset;
3228 r_sge[1].lkey = sqp_entry->sge.lkey;
3229 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3230
3231 /* Create receive work request */
3232 rwr.num_sge = 2;
3233 rwr.sg_list = r_sge;
3234 rwr.wr_id = tbl_idx;
3235 rwr.next = NULL;
3236
3237 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3238 if (rc) {
3239 ibdev_err(&rdev->ibdev,
3240 "Failed to post Rx buffers to shadow QP");
3241 return -ENOMEM;
3242 }
3243
3244 swr->num_sge = 2;
3245 swr->sg_list = s_sge;
3246 swr->wr_id = tbl_idx;
3247 swr->opcode = IB_WR_SEND;
3248 swr->next = NULL;
3249 gsi_sah = rdev->gsi_ctx.gsi_sah;
3250 udwr.ah = &gsi_sah->ib_ah;
3251 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3252 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3253
3254 /* post data received in the send queue */
3255 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3256 }
3257
bnxt_re_process_res_rawqp1_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3258 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3259 struct bnxt_qplib_cqe *cqe)
3260 {
3261 wc->opcode = IB_WC_RECV;
3262 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3263 wc->wc_flags |= IB_WC_GRH;
3264 }
3265
bnxt_re_check_if_vlan_valid(struct bnxt_re_dev * rdev,u16 vlan_id)3266 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3267 u16 vlan_id)
3268 {
3269 /*
3270 * Check if the vlan is configured in the host. If not configured, it
3271 * can be a transparent VLAN. So dont report the vlan id.
3272 */
3273 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3274 htons(ETH_P_8021Q), vlan_id))
3275 return false;
3276 return true;
3277 }
3278
bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe * orig_cqe,u16 * vid,u8 * sl)3279 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3280 u16 *vid, u8 *sl)
3281 {
3282 bool ret = false;
3283 u32 metadata;
3284 u16 tpid;
3285
3286 metadata = orig_cqe->raweth_qp1_metadata;
3287 if (orig_cqe->raweth_qp1_flags2 &
3288 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3289 tpid = ((metadata &
3290 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3291 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3292 if (tpid == ETH_P_8021Q) {
3293 *vid = metadata &
3294 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3295 *sl = (metadata &
3296 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3297 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3298 ret = true;
3299 }
3300 }
3301
3302 return ret;
3303 }
3304
bnxt_re_process_res_rc_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3305 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3306 struct bnxt_qplib_cqe *cqe)
3307 {
3308 wc->opcode = IB_WC_RECV;
3309 wc->status = __rc_to_ib_wc_status(cqe->status);
3310
3311 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3312 wc->wc_flags |= IB_WC_WITH_IMM;
3313 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3314 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3315 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3316 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3317 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3318 }
3319
bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp * gsi_sqp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3320 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3321 struct ib_wc *wc,
3322 struct bnxt_qplib_cqe *cqe)
3323 {
3324 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3325 struct bnxt_re_qp *gsi_qp = NULL;
3326 struct bnxt_qplib_cqe *orig_cqe = NULL;
3327 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3328 int nw_type;
3329 u32 tbl_idx;
3330 u16 vlan_id;
3331 u8 sl;
3332
3333 tbl_idx = cqe->wr_id;
3334
3335 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3336 gsi_qp = sqp_entry->qp1_qp;
3337 orig_cqe = &sqp_entry->cqe;
3338
3339 wc->wr_id = sqp_entry->wrid;
3340 wc->byte_len = orig_cqe->length;
3341 wc->qp = &gsi_qp->ib_qp;
3342
3343 wc->ex.imm_data = orig_cqe->immdata;
3344 wc->src_qp = orig_cqe->src_qp;
3345 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3346 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3347 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3348 wc->vlan_id = vlan_id;
3349 wc->sl = sl;
3350 wc->wc_flags |= IB_WC_WITH_VLAN;
3351 }
3352 }
3353 wc->port_num = 1;
3354 wc->vendor_err = orig_cqe->status;
3355
3356 wc->opcode = IB_WC_RECV;
3357 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3358 wc->wc_flags |= IB_WC_GRH;
3359
3360 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3361 orig_cqe->raweth_qp1_flags2);
3362 if (nw_type >= 0) {
3363 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3364 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3365 }
3366 }
3367
bnxt_re_process_res_ud_wc(struct bnxt_re_qp * qp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3368 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3369 struct ib_wc *wc,
3370 struct bnxt_qplib_cqe *cqe)
3371 {
3372 struct bnxt_re_dev *rdev;
3373 u16 vlan_id = 0;
3374 u8 nw_type;
3375
3376 rdev = qp->rdev;
3377 wc->opcode = IB_WC_RECV;
3378 wc->status = __rc_to_ib_wc_status(cqe->status);
3379
3380 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3381 wc->wc_flags |= IB_WC_WITH_IMM;
3382 /* report only on GSI QP for Thor */
3383 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3384 wc->wc_flags |= IB_WC_GRH;
3385 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3386 wc->wc_flags |= IB_WC_WITH_SMAC;
3387 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3388 vlan_id = (cqe->cfa_meta & 0xFFF);
3389 }
3390 /* Mark only if vlan_id is non zero */
3391 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3392 wc->vlan_id = vlan_id;
3393 wc->wc_flags |= IB_WC_WITH_VLAN;
3394 }
3395 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3396 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3397 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3398 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3399 }
3400
3401 }
3402
send_phantom_wqe(struct bnxt_re_qp * qp)3403 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3404 {
3405 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3406 unsigned long flags;
3407 int rc = 0;
3408
3409 spin_lock_irqsave(&qp->sq_lock, flags);
3410
3411 rc = bnxt_re_bind_fence_mw(lib_qp);
3412 if (!rc) {
3413 lib_qp->sq.phantom_wqe_cnt++;
3414 ibdev_dbg(&qp->rdev->ibdev,
3415 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3416 lib_qp->id, lib_qp->sq.hwq.prod,
3417 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3418 lib_qp->sq.phantom_wqe_cnt);
3419 }
3420
3421 spin_unlock_irqrestore(&qp->sq_lock, flags);
3422 return rc;
3423 }
3424
bnxt_re_poll_cq(struct ib_cq * ib_cq,int num_entries,struct ib_wc * wc)3425 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3426 {
3427 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3428 struct bnxt_re_qp *qp, *sh_qp;
3429 struct bnxt_qplib_cqe *cqe;
3430 int i, ncqe, budget;
3431 struct bnxt_qplib_q *sq;
3432 struct bnxt_qplib_qp *lib_qp;
3433 u32 tbl_idx;
3434 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3435 unsigned long flags;
3436
3437 spin_lock_irqsave(&cq->cq_lock, flags);
3438 budget = min_t(u32, num_entries, cq->max_cql);
3439 num_entries = budget;
3440 if (!cq->cql) {
3441 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3442 goto exit;
3443 }
3444 cqe = &cq->cql[0];
3445 while (budget) {
3446 lib_qp = NULL;
3447 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3448 if (lib_qp) {
3449 sq = &lib_qp->sq;
3450 if (sq->send_phantom) {
3451 qp = container_of(lib_qp,
3452 struct bnxt_re_qp, qplib_qp);
3453 if (send_phantom_wqe(qp) == -ENOMEM)
3454 ibdev_err(&cq->rdev->ibdev,
3455 "Phantom failed! Scheduled to send again\n");
3456 else
3457 sq->send_phantom = false;
3458 }
3459 }
3460 if (ncqe < budget)
3461 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3462 cqe + ncqe,
3463 budget - ncqe);
3464
3465 if (!ncqe)
3466 break;
3467
3468 for (i = 0; i < ncqe; i++, cqe++) {
3469 /* Transcribe each qplib_wqe back to ib_wc */
3470 memset(wc, 0, sizeof(*wc));
3471
3472 wc->wr_id = cqe->wr_id;
3473 wc->byte_len = cqe->length;
3474 qp = container_of
3475 ((struct bnxt_qplib_qp *)
3476 (unsigned long)(cqe->qp_handle),
3477 struct bnxt_re_qp, qplib_qp);
3478 wc->qp = &qp->ib_qp;
3479 wc->ex.imm_data = cqe->immdata;
3480 wc->src_qp = cqe->src_qp;
3481 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3482 wc->port_num = 1;
3483 wc->vendor_err = cqe->status;
3484
3485 switch (cqe->opcode) {
3486 case CQ_BASE_CQE_TYPE_REQ:
3487 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3488 if (sh_qp &&
3489 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3490 /* Handle this completion with
3491 * the stored completion
3492 */
3493 memset(wc, 0, sizeof(*wc));
3494 continue;
3495 }
3496 bnxt_re_process_req_wc(wc, cqe);
3497 break;
3498 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3499 if (!cqe->status) {
3500 int rc = 0;
3501
3502 rc = bnxt_re_process_raw_qp_pkt_rx
3503 (qp, cqe);
3504 if (!rc) {
3505 memset(wc, 0, sizeof(*wc));
3506 continue;
3507 }
3508 cqe->status = -1;
3509 }
3510 /* Errors need not be looped back.
3511 * But change the wr_id to the one
3512 * stored in the table
3513 */
3514 tbl_idx = cqe->wr_id;
3515 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3516 wc->wr_id = sqp_entry->wrid;
3517 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3518 break;
3519 case CQ_BASE_CQE_TYPE_RES_RC:
3520 bnxt_re_process_res_rc_wc(wc, cqe);
3521 break;
3522 case CQ_BASE_CQE_TYPE_RES_UD:
3523 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3524 if (sh_qp &&
3525 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3526 /* Handle this completion with
3527 * the stored completion
3528 */
3529 if (cqe->status) {
3530 continue;
3531 } else {
3532 bnxt_re_process_res_shadow_qp_wc
3533 (qp, wc, cqe);
3534 break;
3535 }
3536 }
3537 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3538 break;
3539 default:
3540 ibdev_err(&cq->rdev->ibdev,
3541 "POLL CQ : type 0x%x not handled",
3542 cqe->opcode);
3543 continue;
3544 }
3545 wc++;
3546 budget--;
3547 }
3548 }
3549 exit:
3550 spin_unlock_irqrestore(&cq->cq_lock, flags);
3551 return num_entries - budget;
3552 }
3553
bnxt_re_req_notify_cq(struct ib_cq * ib_cq,enum ib_cq_notify_flags ib_cqn_flags)3554 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3555 enum ib_cq_notify_flags ib_cqn_flags)
3556 {
3557 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3558 int type = 0, rc = 0;
3559 unsigned long flags;
3560
3561 spin_lock_irqsave(&cq->cq_lock, flags);
3562 /* Trigger on the very next completion */
3563 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3564 type = DBC_DBC_TYPE_CQ_ARMALL;
3565 /* Trigger on the next solicited completion */
3566 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3567 type = DBC_DBC_TYPE_CQ_ARMSE;
3568
3569 /* Poll to see if there are missed events */
3570 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3571 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3572 rc = 1;
3573 goto exit;
3574 }
3575 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3576
3577 exit:
3578 spin_unlock_irqrestore(&cq->cq_lock, flags);
3579 return rc;
3580 }
3581
3582 /* Memory Regions */
bnxt_re_get_dma_mr(struct ib_pd * ib_pd,int mr_access_flags)3583 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3584 {
3585 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3586 struct bnxt_re_dev *rdev = pd->rdev;
3587 struct bnxt_re_mr *mr;
3588 int rc;
3589
3590 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3591 if (!mr)
3592 return ERR_PTR(-ENOMEM);
3593
3594 mr->rdev = rdev;
3595 mr->qplib_mr.pd = &pd->qplib_pd;
3596 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3597 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3598
3599 /* Allocate and register 0 as the address */
3600 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3601 if (rc)
3602 goto fail;
3603
3604 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3605 mr->qplib_mr.total_size = -1; /* Infinte length */
3606 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3607 PAGE_SIZE);
3608 if (rc)
3609 goto fail_mr;
3610
3611 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3612 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3613 IB_ACCESS_REMOTE_ATOMIC))
3614 mr->ib_mr.rkey = mr->ib_mr.lkey;
3615 atomic_inc(&rdev->mr_count);
3616
3617 return &mr->ib_mr;
3618
3619 fail_mr:
3620 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3621 fail:
3622 kfree(mr);
3623 return ERR_PTR(rc);
3624 }
3625
bnxt_re_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)3626 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3627 {
3628 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3629 struct bnxt_re_dev *rdev = mr->rdev;
3630 int rc;
3631
3632 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3633 if (rc) {
3634 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3635 return rc;
3636 }
3637
3638 if (mr->pages) {
3639 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3640 &mr->qplib_frpl);
3641 kfree(mr->pages);
3642 mr->npages = 0;
3643 mr->pages = NULL;
3644 }
3645 ib_umem_release(mr->ib_umem);
3646
3647 kfree(mr);
3648 atomic_dec(&rdev->mr_count);
3649 return rc;
3650 }
3651
bnxt_re_set_page(struct ib_mr * ib_mr,u64 addr)3652 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3653 {
3654 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3655
3656 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3657 return -ENOMEM;
3658
3659 mr->pages[mr->npages++] = addr;
3660 return 0;
3661 }
3662
bnxt_re_map_mr_sg(struct ib_mr * ib_mr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)3663 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3664 unsigned int *sg_offset)
3665 {
3666 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3667
3668 mr->npages = 0;
3669 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3670 }
3671
bnxt_re_alloc_mr(struct ib_pd * ib_pd,enum ib_mr_type type,u32 max_num_sg)3672 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3673 u32 max_num_sg)
3674 {
3675 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3676 struct bnxt_re_dev *rdev = pd->rdev;
3677 struct bnxt_re_mr *mr = NULL;
3678 int rc;
3679
3680 if (type != IB_MR_TYPE_MEM_REG) {
3681 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3682 return ERR_PTR(-EINVAL);
3683 }
3684 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3685 return ERR_PTR(-EINVAL);
3686
3687 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3688 if (!mr)
3689 return ERR_PTR(-ENOMEM);
3690
3691 mr->rdev = rdev;
3692 mr->qplib_mr.pd = &pd->qplib_pd;
3693 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3694 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3695
3696 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3697 if (rc)
3698 goto bail;
3699
3700 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3701 mr->ib_mr.rkey = mr->ib_mr.lkey;
3702
3703 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3704 if (!mr->pages) {
3705 rc = -ENOMEM;
3706 goto fail;
3707 }
3708 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3709 &mr->qplib_frpl, max_num_sg);
3710 if (rc) {
3711 ibdev_err(&rdev->ibdev,
3712 "Failed to allocate HW FR page list");
3713 goto fail_mr;
3714 }
3715
3716 atomic_inc(&rdev->mr_count);
3717 return &mr->ib_mr;
3718
3719 fail_mr:
3720 kfree(mr->pages);
3721 fail:
3722 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3723 bail:
3724 kfree(mr);
3725 return ERR_PTR(rc);
3726 }
3727
bnxt_re_alloc_mw(struct ib_pd * ib_pd,enum ib_mw_type type,struct ib_udata * udata)3728 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3729 struct ib_udata *udata)
3730 {
3731 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3732 struct bnxt_re_dev *rdev = pd->rdev;
3733 struct bnxt_re_mw *mw;
3734 int rc;
3735
3736 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3737 if (!mw)
3738 return ERR_PTR(-ENOMEM);
3739 mw->rdev = rdev;
3740 mw->qplib_mw.pd = &pd->qplib_pd;
3741
3742 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3743 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3744 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3745 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3746 if (rc) {
3747 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3748 goto fail;
3749 }
3750 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3751
3752 atomic_inc(&rdev->mw_count);
3753 return &mw->ib_mw;
3754
3755 fail:
3756 kfree(mw);
3757 return ERR_PTR(rc);
3758 }
3759
bnxt_re_dealloc_mw(struct ib_mw * ib_mw)3760 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3761 {
3762 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3763 struct bnxt_re_dev *rdev = mw->rdev;
3764 int rc;
3765
3766 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3767 if (rc) {
3768 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3769 return rc;
3770 }
3771
3772 kfree(mw);
3773 atomic_dec(&rdev->mw_count);
3774 return rc;
3775 }
3776
3777 /* uverbs */
bnxt_re_reg_user_mr(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int mr_access_flags,struct ib_udata * udata)3778 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3779 u64 virt_addr, int mr_access_flags,
3780 struct ib_udata *udata)
3781 {
3782 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3783 struct bnxt_re_dev *rdev = pd->rdev;
3784 struct bnxt_re_mr *mr;
3785 struct ib_umem *umem;
3786 unsigned long page_size;
3787 int umem_pgs, rc;
3788
3789 if (length > BNXT_RE_MAX_MR_SIZE) {
3790 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3791 length, BNXT_RE_MAX_MR_SIZE);
3792 return ERR_PTR(-ENOMEM);
3793 }
3794
3795 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3796 if (!mr)
3797 return ERR_PTR(-ENOMEM);
3798
3799 mr->rdev = rdev;
3800 mr->qplib_mr.pd = &pd->qplib_pd;
3801 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3802 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3803
3804 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3805 if (rc) {
3806 ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3807 goto free_mr;
3808 }
3809 /* The fixed portion of the rkey is the same as the lkey */
3810 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3811
3812 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3813 if (IS_ERR(umem)) {
3814 ibdev_err(&rdev->ibdev, "Failed to get umem");
3815 rc = -EFAULT;
3816 goto free_mrw;
3817 }
3818 mr->ib_umem = umem;
3819
3820 mr->qplib_mr.va = virt_addr;
3821 page_size = ib_umem_find_best_pgsz(
3822 umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
3823 if (!page_size) {
3824 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3825 rc = -EFAULT;
3826 goto free_umem;
3827 }
3828 mr->qplib_mr.total_size = length;
3829
3830 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
3831 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
3832 umem_pgs, page_size);
3833 if (rc) {
3834 ibdev_err(&rdev->ibdev, "Failed to register user MR");
3835 goto free_umem;
3836 }
3837
3838 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3839 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3840 atomic_inc(&rdev->mr_count);
3841
3842 return &mr->ib_mr;
3843 free_umem:
3844 ib_umem_release(umem);
3845 free_mrw:
3846 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3847 free_mr:
3848 kfree(mr);
3849 return ERR_PTR(rc);
3850 }
3851
bnxt_re_alloc_ucontext(struct ib_ucontext * ctx,struct ib_udata * udata)3852 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3853 {
3854 struct ib_device *ibdev = ctx->device;
3855 struct bnxt_re_ucontext *uctx =
3856 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3857 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3858 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3859 struct bnxt_re_uctx_resp resp = {};
3860 u32 chip_met_rev_num = 0;
3861 int rc;
3862
3863 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3864
3865 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3866 ibdev_dbg(ibdev, " is different from the device %d ",
3867 BNXT_RE_ABI_VERSION);
3868 return -EPERM;
3869 }
3870
3871 uctx->rdev = rdev;
3872
3873 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3874 if (!uctx->shpg) {
3875 rc = -ENOMEM;
3876 goto fail;
3877 }
3878 spin_lock_init(&uctx->sh_lock);
3879
3880 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3881 chip_met_rev_num = rdev->chip_ctx->chip_num;
3882 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3883 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3884 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3885 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3886 resp.chip_id0 = chip_met_rev_num;
3887 /*Temp, Use xa_alloc instead */
3888 resp.dev_id = rdev->en_dev->pdev->devfn;
3889 resp.max_qp = rdev->qplib_ctx.qpc_count;
3890 resp.pg_size = PAGE_SIZE;
3891 resp.cqe_sz = sizeof(struct cq_base);
3892 resp.max_cqd = dev_attr->max_cq_wqes;
3893
3894 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
3895 resp.mode = rdev->chip_ctx->modes.wqe_mode;
3896
3897 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3898 if (rc) {
3899 ibdev_err(ibdev, "Failed to copy user context");
3900 rc = -EFAULT;
3901 goto cfail;
3902 }
3903
3904 return 0;
3905 cfail:
3906 free_page((unsigned long)uctx->shpg);
3907 uctx->shpg = NULL;
3908 fail:
3909 return rc;
3910 }
3911
bnxt_re_dealloc_ucontext(struct ib_ucontext * ib_uctx)3912 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3913 {
3914 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3915 struct bnxt_re_ucontext,
3916 ib_uctx);
3917
3918 struct bnxt_re_dev *rdev = uctx->rdev;
3919
3920 if (uctx->shpg)
3921 free_page((unsigned long)uctx->shpg);
3922
3923 if (uctx->dpi.dbr) {
3924 /* Free DPI only if this is the first PD allocated by the
3925 * application and mark the context dpi as NULL
3926 */
3927 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3928 &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3929 uctx->dpi.dbr = NULL;
3930 }
3931 }
3932
3933 /* Helper function to mmap the virtual memory from user app */
bnxt_re_mmap(struct ib_ucontext * ib_uctx,struct vm_area_struct * vma)3934 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3935 {
3936 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3937 struct bnxt_re_ucontext,
3938 ib_uctx);
3939 struct bnxt_re_dev *rdev = uctx->rdev;
3940 u64 pfn;
3941
3942 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3943 return -EINVAL;
3944
3945 if (vma->vm_pgoff) {
3946 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3947 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3948 PAGE_SIZE, vma->vm_page_prot)) {
3949 ibdev_err(&rdev->ibdev, "Failed to map DPI");
3950 return -EAGAIN;
3951 }
3952 } else {
3953 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3954 if (remap_pfn_range(vma, vma->vm_start,
3955 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3956 ibdev_err(&rdev->ibdev, "Failed to map shared page");
3957 return -EAGAIN;
3958 }
3959 }
3960
3961 return 0;
3962 }
3963