1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START 0
21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE SZ_1K
27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE SZ_1K
29
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35
36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
37
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
39
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
49
50 struct otx2_mbox_dev {
51 void *mbase; /* This dev's mbox region */
52 void *hwbase;
53 spinlock_t mbox_lock;
54 u16 msg_size; /* Total msg size to be sent */
55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
56 u16 num_msgs; /* No of msgs sent or waiting for response */
57 u16 msgs_acked; /* No of msgs for which response is received */
58 };
59
60 struct otx2_mbox {
61 struct pci_dev *pdev;
62 void *hwbase; /* Mbox region advertised by HW */
63 void *reg_base;/* CSR base for this dev */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
68 u16 rx_size; /* Size of Rx region */
69 u16 tx_size; /* Size of Tx region */
70 u16 ndevs; /* The number of peers */
71 struct otx2_mbox_dev *dev;
72 };
73
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 u64 msg_size; /* Total msgs size embedded */
77 u16 num_msgs; /* No of msgs embedded */
78 };
79
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 u16 pcifunc; /* Who's sending this msg */
83 u16 id; /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 u16 sig; /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 u16 ver; /* Version of msg's structure for this ID */
89 u16 next_msgoff; /* Offset of next msg within mailbox region */
90 int rc; /* Msg process'ed response code */
91 };
92
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99
100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
101 struct pci_dev *pdev, void __force *reg_base,
102 int direction, int ndevs, unsigned long *bmap);
103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
107 int size, int size_rsp);
108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
109 struct mbox_msghdr *msg);
110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
112 u16 pcifunc, u16 id);
113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
114 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
116 int devid, int size)
117 {
118 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
119 }
120
121 /* Mailbox message types */
122 #define MBOX_MSG_MASK 0xFFFF
123 #define MBOX_MSG_INVALID 0xFFFE
124 #define MBOX_MSG_MAX 0xFFFF
125
126 #define MBOX_MESSAGES \
127 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
128 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
129 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
130 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
131 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
132 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
133 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
134 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
135 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
136 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
137 msg_rsp) \
138 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
139 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
140 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
141 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
142 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
143 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
144 cgx_mac_addr_set_or_get) \
145 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
146 cgx_mac_addr_set_or_get) \
147 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
148 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
149 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
150 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
151 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
152 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
153 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
154 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
155 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
156 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
157 cgx_pause_frm_cfg) \
158 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
159 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
160 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
161 cgx_mac_addr_add_rsp) \
162 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
163 msg_rsp) \
164 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
165 cgx_max_dmac_entries_get_rsp) \
166 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
167 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
168 cgx_set_link_mode_rsp) \
169 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
170 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
171 cgx_features_info_msg) \
172 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
173 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
174 msg_rsp) \
175 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
176 cgx_mac_addr_update_rsp) \
177 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
178 cgx_pfc_rsp) \
179 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
180 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
181 npa_lf_alloc_req, npa_lf_alloc_rsp) \
182 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
183 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
184 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
185 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
186 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
187 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
188 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
189 msg_rsp) \
190 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
191 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
192 cpt_rd_wr_reg_msg) \
193 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
194 cpt_inline_ipsec_cfg_msg, msg_rsp) \
195 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
196 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
197 msg_rsp) \
198 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
199 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
200 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
201 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
202 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
203 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
204 npc_mcam_alloc_entry_rsp) \
205 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
206 npc_mcam_free_entry_req, msg_rsp) \
207 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
208 npc_mcam_write_entry_req, msg_rsp) \
209 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
210 npc_mcam_ena_dis_entry_req, msg_rsp) \
211 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
212 npc_mcam_ena_dis_entry_req, msg_rsp) \
213 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
214 npc_mcam_shift_entry_rsp) \
215 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
216 npc_mcam_alloc_counter_req, \
217 npc_mcam_alloc_counter_rsp) \
218 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
219 npc_mcam_oper_counter_req, msg_rsp) \
220 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
221 npc_mcam_unmap_counter_req, msg_rsp) \
222 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
223 npc_mcam_oper_counter_req, msg_rsp) \
224 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
225 npc_mcam_oper_counter_req, \
226 npc_mcam_oper_counter_rsp) \
227 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
228 npc_mcam_alloc_and_write_entry_req, \
229 npc_mcam_alloc_and_write_entry_rsp) \
230 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
231 msg_req, npc_get_kex_cfg_rsp) \
232 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
233 npc_install_flow_req, npc_install_flow_rsp) \
234 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
235 npc_delete_flow_req, npc_delete_flow_rsp) \
236 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
237 npc_mcam_read_entry_req, \
238 npc_mcam_read_entry_rsp) \
239 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
240 npc_set_pkind, msg_rsp) \
241 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
242 msg_req, npc_mcam_read_base_rule_rsp) \
243 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
244 npc_mcam_get_stats_req, \
245 npc_mcam_get_stats_rsp) \
246 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
247 npc_get_field_hash_info_req, \
248 npc_get_field_hash_info_rsp) \
249 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
250 npc_get_field_status_req, \
251 npc_get_field_status_rsp) \
252 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
253 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
254 nix_lf_alloc_req, nix_lf_alloc_rsp) \
255 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
256 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
257 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
258 hwctx_disable_req, msg_rsp) \
259 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
260 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
261 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
262 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
263 nix_txschq_config) \
264 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
265 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
266 nix_vtag_config_rsp) \
267 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
268 nix_rss_flowkey_cfg, \
269 nix_rss_flowkey_cfg_rsp) \
270 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
271 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
272 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
273 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
274 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
275 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
276 nix_mark_format_cfg, \
277 nix_mark_format_cfg_rsp) \
278 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
279 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
280 nix_lso_format_cfg, \
281 nix_lso_format_cfg_rsp) \
282 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
283 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
284 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
285 nix_bp_cfg_rsp) \
286 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
287 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
288 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
289 nix_inline_ipsec_cfg, msg_rsp) \
290 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
291 nix_inline_ipsec_lf_cfg, msg_rsp) \
292 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
293 nix_cn10k_aq_enq_rsp) \
294 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
295 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
296 nix_bandprof_alloc_rsp) \
297 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
298 msg_rsp) \
299 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
300 nix_bandprof_get_hwinfo_rsp) \
301 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
302 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
303 mcs_alloc_rsrc_rsp) \
304 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
305 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
306 msg_rsp) \
307 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
308 msg_rsp) \
309 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
310 msg_rsp) \
311 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
312 msg_rsp) \
313 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
314 msg_rsp) \
315 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
316 msg_rsp) \
317 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
318 msg_rsp) \
319 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
320 msg_rsp) \
321 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
322 msg_rsp) \
323 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
324 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
325 mcs_flowid_stats) \
326 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
327 mcs_secy_stats) \
328 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
329 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
330 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
331 mcs_port_stats) \
332 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
333 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
334 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
335 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
336 msg_rsp) \
337 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
338 mcs_alloc_ctrl_pkt_rule_req, \
339 mcs_alloc_ctrl_pkt_rule_rsp) \
340 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
341 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
342 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
343 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
344 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
345 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
346 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
347 mcs_port_cfg_get_rsp) \
348 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
349 mcs_custom_tag_cfg_get_req, \
350 mcs_custom_tag_cfg_get_rsp)
351
352 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
353 #define MBOX_UP_CGX_MESSAGES \
354 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
355
356 #define MBOX_UP_CPT_MESSAGES \
357 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
358
359 #define MBOX_UP_MCS_MESSAGES \
360 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
361
362 enum {
363 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
364 MBOX_MESSAGES
365 MBOX_UP_CGX_MESSAGES
366 MBOX_UP_CPT_MESSAGES
367 MBOX_UP_MCS_MESSAGES
368 #undef M
369 };
370
371 /* Mailbox message formats */
372
373 #define RVU_DEFAULT_PF_FUNC 0xFFFF
374
375 /* Generic request msg used for those mbox messages which
376 * don't send any data in the request.
377 */
378 struct msg_req {
379 struct mbox_msghdr hdr;
380 };
381
382 /* Generic response msg used an ack or response for those mbox
383 * messages which don't have a specific rsp msg format.
384 */
385 struct msg_rsp {
386 struct mbox_msghdr hdr;
387 };
388
389 /* RVU mailbox error codes
390 * Range 256 - 300.
391 */
392 enum rvu_af_status {
393 RVU_INVALID_VF_ID = -256,
394 };
395
396 struct ready_msg_rsp {
397 struct mbox_msghdr hdr;
398 u16 sclk_freq; /* SCLK frequency (in MHz) */
399 u16 rclk_freq; /* RCLK frequency (in MHz) */
400 };
401
402 /* Structure for requesting resource provisioning.
403 * 'modify' flag to be used when either requesting more
404 * or to detach partial of a certain resource type.
405 * Rest of the fields specify how many of what type to
406 * be attached.
407 * To request LFs from two blocks of same type this mailbox
408 * can be sent twice as below:
409 * struct rsrc_attach *attach;
410 * .. Allocate memory for message ..
411 * attach->cptlfs = 3; <3 LFs from CPT0>
412 * .. Send message ..
413 * .. Allocate memory for message ..
414 * attach->modify = 1;
415 * attach->cpt_blkaddr = BLKADDR_CPT1;
416 * attach->cptlfs = 2; <2 LFs from CPT1>
417 * .. Send message ..
418 */
419 struct rsrc_attach {
420 struct mbox_msghdr hdr;
421 u8 modify:1;
422 u8 npalf:1;
423 u8 nixlf:1;
424 u16 sso;
425 u16 ssow;
426 u16 timlfs;
427 u16 cptlfs;
428 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
429 };
430
431 /* Structure for relinquishing resources.
432 * 'partial' flag to be used when relinquishing all resources
433 * but only of a certain type. If not set, all resources of all
434 * types provisioned to the RVU function will be detached.
435 */
436 struct rsrc_detach {
437 struct mbox_msghdr hdr;
438 u8 partial:1;
439 u8 npalf:1;
440 u8 nixlf:1;
441 u8 sso:1;
442 u8 ssow:1;
443 u8 timlfs:1;
444 u8 cptlfs:1;
445 };
446
447 /* Number of resources available to the caller.
448 * In reply to MBOX_MSG_FREE_RSRC_CNT.
449 */
450 struct free_rsrcs_rsp {
451 struct mbox_msghdr hdr;
452 u16 schq[NIX_TXSCH_LVL_CNT];
453 u16 sso;
454 u16 tim;
455 u16 ssow;
456 u16 cpt;
457 u8 npa;
458 u8 nix;
459 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
460 u8 nix1;
461 u8 cpt1;
462 u8 ree0;
463 u8 ree1;
464 };
465
466 #define MSIX_VECTOR_INVALID 0xFFFF
467 #define MAX_RVU_BLKLF_CNT 256
468
469 struct msix_offset_rsp {
470 struct mbox_msghdr hdr;
471 u16 npa_msixoff;
472 u16 nix_msixoff;
473 u16 sso;
474 u16 ssow;
475 u16 timlfs;
476 u16 cptlfs;
477 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
478 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
479 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
480 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
481 u16 cpt1_lfs;
482 u16 ree0_lfs;
483 u16 ree1_lfs;
484 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
485 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
486 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
487 };
488
489 struct get_hw_cap_rsp {
490 struct mbox_msghdr hdr;
491 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
492 u8 nix_shaping; /* Is shaping and coloring supported */
493 u8 npc_hash_extract; /* Is hash extract supported */
494 };
495
496 /* CGX mbox message formats */
497
498 struct cgx_stats_rsp {
499 struct mbox_msghdr hdr;
500 #define CGX_RX_STATS_COUNT 9
501 #define CGX_TX_STATS_COUNT 18
502 u64 rx_stats[CGX_RX_STATS_COUNT];
503 u64 tx_stats[CGX_TX_STATS_COUNT];
504 };
505
506 struct cgx_fec_stats_rsp {
507 struct mbox_msghdr hdr;
508 u64 fec_corr_blks;
509 u64 fec_uncorr_blks;
510 };
511 /* Structure for requesting the operation for
512 * setting/getting mac address in the CGX interface
513 */
514 struct cgx_mac_addr_set_or_get {
515 struct mbox_msghdr hdr;
516 u8 mac_addr[ETH_ALEN];
517 u32 index;
518 };
519
520 /* Structure for requesting the operation to
521 * add DMAC filter entry into CGX interface
522 */
523 struct cgx_mac_addr_add_req {
524 struct mbox_msghdr hdr;
525 u8 mac_addr[ETH_ALEN];
526 };
527
528 /* Structure for response against the operation to
529 * add DMAC filter entry into CGX interface
530 */
531 struct cgx_mac_addr_add_rsp {
532 struct mbox_msghdr hdr;
533 u32 index;
534 };
535
536 /* Structure for requesting the operation to
537 * delete DMAC filter entry from CGX interface
538 */
539 struct cgx_mac_addr_del_req {
540 struct mbox_msghdr hdr;
541 u32 index;
542 };
543
544 /* Structure for response against the operation to
545 * get maximum supported DMAC filter entries
546 */
547 struct cgx_max_dmac_entries_get_rsp {
548 struct mbox_msghdr hdr;
549 u32 max_dmac_filters;
550 };
551
552 struct cgx_link_user_info {
553 uint64_t link_up:1;
554 uint64_t full_duplex:1;
555 uint64_t lmac_type_id:4;
556 uint64_t speed:20; /* speed in Mbps */
557 uint64_t an:1; /* AN supported or not */
558 uint64_t fec:2; /* FEC type if enabled else 0 */
559 #define LMACTYPE_STR_LEN 16
560 char lmac_type[LMACTYPE_STR_LEN];
561 };
562
563 struct cgx_link_info_msg {
564 struct mbox_msghdr hdr;
565 struct cgx_link_user_info link_info;
566 };
567
568 struct cgx_pause_frm_cfg {
569 struct mbox_msghdr hdr;
570 u8 set;
571 /* set = 1 if the request is to config pause frames */
572 /* set = 0 if the request is to fetch pause frames config */
573 u8 rx_pause;
574 u8 tx_pause;
575 };
576
577 enum fec_type {
578 OTX2_FEC_NONE,
579 OTX2_FEC_BASER,
580 OTX2_FEC_RS,
581 OTX2_FEC_STATS_CNT = 2,
582 OTX2_FEC_OFF,
583 };
584
585 struct fec_mode {
586 struct mbox_msghdr hdr;
587 int fec;
588 };
589
590 struct sfp_eeprom_s {
591 #define SFP_EEPROM_SIZE 256
592 u16 sff_id;
593 u8 buf[SFP_EEPROM_SIZE];
594 u64 reserved;
595 };
596
597 struct phy_s {
598 struct {
599 u64 can_change_mod_type:1;
600 u64 mod_type:1;
601 u64 has_fec_stats:1;
602 } misc;
603 struct fec_stats_s {
604 u32 rsfec_corr_cws;
605 u32 rsfec_uncorr_cws;
606 u32 brfec_corr_blks;
607 u32 brfec_uncorr_blks;
608 } fec_stats;
609 };
610
611 struct cgx_lmac_fwdata_s {
612 u16 rw_valid;
613 u64 supported_fec;
614 u64 supported_an;
615 u64 supported_link_modes;
616 /* only applicable if AN is supported */
617 u64 advertised_fec;
618 u64 advertised_link_modes;
619 /* Only applicable if SFP/QSFP slot is present */
620 struct sfp_eeprom_s sfp_eeprom;
621 struct phy_s phy;
622 #define LMAC_FWDATA_RESERVED_MEM 1021
623 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
624 };
625
626 struct cgx_fw_data {
627 struct mbox_msghdr hdr;
628 struct cgx_lmac_fwdata_s fwdata;
629 };
630
631 struct cgx_set_link_mode_args {
632 u32 speed;
633 u8 duplex;
634 u8 an;
635 u8 ports;
636 u64 mode;
637 };
638
639 struct cgx_set_link_mode_req {
640 #define AUTONEG_UNKNOWN 0xff
641 struct mbox_msghdr hdr;
642 struct cgx_set_link_mode_args args;
643 };
644
645 struct cgx_set_link_mode_rsp {
646 struct mbox_msghdr hdr;
647 int status;
648 };
649
650 struct cgx_mac_addr_reset_req {
651 struct mbox_msghdr hdr;
652 u32 index;
653 };
654
655 struct cgx_mac_addr_update_req {
656 struct mbox_msghdr hdr;
657 u8 mac_addr[ETH_ALEN];
658 u32 index;
659 };
660
661 struct cgx_mac_addr_update_rsp {
662 struct mbox_msghdr hdr;
663 u32 index;
664 };
665
666 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
667 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
668 /* flow control from physical link higig2 messages */
669 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
670 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
671 #define RVU_MAC_VERSION BIT_ULL(4)
672 #define RVU_MAC_CGX BIT_ULL(5)
673 #define RVU_MAC_RPM BIT_ULL(6)
674
675 struct cgx_features_info_msg {
676 struct mbox_msghdr hdr;
677 u64 lmac_features;
678 };
679
680 struct rpm_stats_rsp {
681 struct mbox_msghdr hdr;
682 #define RPM_RX_STATS_COUNT 43
683 #define RPM_TX_STATS_COUNT 34
684 u64 rx_stats[RPM_RX_STATS_COUNT];
685 u64 tx_stats[RPM_TX_STATS_COUNT];
686 };
687
688 struct cgx_pfc_cfg {
689 struct mbox_msghdr hdr;
690 u8 rx_pause;
691 u8 tx_pause;
692 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
693 };
694
695 struct cgx_pfc_rsp {
696 struct mbox_msghdr hdr;
697 u8 rx_pause;
698 u8 tx_pause;
699 };
700
701 /* NPA mbox message formats */
702
703 struct npc_set_pkind {
704 struct mbox_msghdr hdr;
705 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
706 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
707 u64 mode;
708 #define PKIND_TX BIT_ULL(0)
709 #define PKIND_RX BIT_ULL(1)
710 u8 dir;
711 u8 pkind; /* valid only in case custom flag */
712 u8 var_len_off; /* Offset of custom header length field.
713 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
714 */
715 u8 var_len_off_mask; /* Mask for length with in offset */
716 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
717 };
718
719 /* NPA mbox message formats */
720
721 /* NPA mailbox error codes
722 * Range 301 - 400.
723 */
724 enum npa_af_status {
725 NPA_AF_ERR_PARAM = -301,
726 NPA_AF_ERR_AQ_FULL = -302,
727 NPA_AF_ERR_AQ_ENQUEUE = -303,
728 NPA_AF_ERR_AF_LF_INVALID = -304,
729 NPA_AF_ERR_AF_LF_ALLOC = -305,
730 NPA_AF_ERR_LF_RESET = -306,
731 };
732
733 /* For NPA LF context alloc and init */
734 struct npa_lf_alloc_req {
735 struct mbox_msghdr hdr;
736 int node;
737 int aura_sz; /* No of auras */
738 u32 nr_pools; /* No of pools */
739 u64 way_mask;
740 };
741
742 struct npa_lf_alloc_rsp {
743 struct mbox_msghdr hdr;
744 u32 stack_pg_ptrs; /* No of ptrs per stack page */
745 u32 stack_pg_bytes; /* Size of stack page */
746 u16 qints; /* NPA_AF_CONST::QINTS */
747 u8 cache_lines; /*BATCH ALLOC DMA */
748 };
749
750 /* NPA AQ enqueue msg */
751 struct npa_aq_enq_req {
752 struct mbox_msghdr hdr;
753 u32 aura_id;
754 u8 ctype;
755 u8 op;
756 union {
757 /* Valid when op == WRITE/INIT and ctype == AURA.
758 * LF fills the pool_id in aura.pool_addr. AF will translate
759 * the pool_id to pool context pointer.
760 */
761 struct npa_aura_s aura;
762 /* Valid when op == WRITE/INIT and ctype == POOL */
763 struct npa_pool_s pool;
764 };
765 /* Mask data when op == WRITE (1=write, 0=don't write) */
766 union {
767 /* Valid when op == WRITE and ctype == AURA */
768 struct npa_aura_s aura_mask;
769 /* Valid when op == WRITE and ctype == POOL */
770 struct npa_pool_s pool_mask;
771 };
772 };
773
774 struct npa_aq_enq_rsp {
775 struct mbox_msghdr hdr;
776 union {
777 /* Valid when op == READ and ctype == AURA */
778 struct npa_aura_s aura;
779 /* Valid when op == READ and ctype == POOL */
780 struct npa_pool_s pool;
781 };
782 };
783
784 /* Disable all contexts of type 'ctype' */
785 struct hwctx_disable_req {
786 struct mbox_msghdr hdr;
787 u8 ctype;
788 };
789
790 /* NIX mbox message formats */
791
792 /* NIX mailbox error codes
793 * Range 401 - 500.
794 */
795 enum nix_af_status {
796 NIX_AF_ERR_PARAM = -401,
797 NIX_AF_ERR_AQ_FULL = -402,
798 NIX_AF_ERR_AQ_ENQUEUE = -403,
799 NIX_AF_ERR_AF_LF_INVALID = -404,
800 NIX_AF_ERR_AF_LF_ALLOC = -405,
801 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
802 NIX_AF_ERR_TLX_INVALID = -407,
803 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
804 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
805 NIX_AF_ERR_FRS_INVALID = -410,
806 NIX_AF_ERR_RX_LINK_INVALID = -411,
807 NIX_AF_INVAL_TXSCHQ_CFG = -412,
808 NIX_AF_SMQ_FLUSH_FAILED = -413,
809 NIX_AF_ERR_LF_RESET = -414,
810 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
811 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
812 NIX_AF_ERR_MARK_CFG_FAIL = -417,
813 NIX_AF_ERR_LSO_CFG_FAIL = -418,
814 NIX_AF_INVAL_NPA_PF_FUNC = -419,
815 NIX_AF_INVAL_SSO_PF_FUNC = -420,
816 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
817 NIX_AF_ERR_RX_VTAG_INUSE = -422,
818 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
819 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
820 NIX_AF_ERR_INVALID_NIXBLK = -425,
821 NIX_AF_ERR_INVALID_BANDPROF = -426,
822 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
823 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
824 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
825 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
826 NIX_AF_ERR_LINK_CREDITS = -431,
827 };
828
829 /* For NIX RX vtag action */
830 enum nix_rx_vtag0_type {
831 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
832 NIX_AF_LFX_RX_VTAG_TYPE1,
833 NIX_AF_LFX_RX_VTAG_TYPE2,
834 NIX_AF_LFX_RX_VTAG_TYPE3,
835 NIX_AF_LFX_RX_VTAG_TYPE4,
836 NIX_AF_LFX_RX_VTAG_TYPE5,
837 NIX_AF_LFX_RX_VTAG_TYPE6,
838 NIX_AF_LFX_RX_VTAG_TYPE7,
839 };
840
841 /* For NIX LF context alloc and init */
842 struct nix_lf_alloc_req {
843 struct mbox_msghdr hdr;
844 int node;
845 u32 rq_cnt; /* No of receive queues */
846 u32 sq_cnt; /* No of send queues */
847 u32 cq_cnt; /* No of completion queues */
848 u8 xqe_sz;
849 u16 rss_sz;
850 u8 rss_grps;
851 u16 npa_func;
852 u16 sso_func;
853 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
854 u64 way_mask;
855 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
856 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
857 u64 flags;
858 };
859
860 struct nix_lf_alloc_rsp {
861 struct mbox_msghdr hdr;
862 u16 sqb_size;
863 u16 rx_chan_base;
864 u16 tx_chan_base;
865 u8 rx_chan_cnt; /* total number of RX channels */
866 u8 tx_chan_cnt; /* total number of TX channels */
867 u8 lso_tsov4_idx;
868 u8 lso_tsov6_idx;
869 u8 mac_addr[ETH_ALEN];
870 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
871 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
872 u16 cints; /* NIX_AF_CONST2::CINTS */
873 u16 qints; /* NIX_AF_CONST2::QINTS */
874 u8 cgx_links; /* No. of CGX links present in HW */
875 u8 lbk_links; /* No. of LBK links present in HW */
876 u8 sdp_links; /* No. of SDP links present in HW */
877 u8 tx_link; /* Transmit channel link number */
878 };
879
880 struct nix_lf_free_req {
881 struct mbox_msghdr hdr;
882 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
883 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
884 u64 flags;
885 };
886
887 /* CN10K NIX AQ enqueue msg */
888 struct nix_cn10k_aq_enq_req {
889 struct mbox_msghdr hdr;
890 u32 qidx;
891 u8 ctype;
892 u8 op;
893 union {
894 struct nix_cn10k_rq_ctx_s rq;
895 struct nix_cn10k_sq_ctx_s sq;
896 struct nix_cq_ctx_s cq;
897 struct nix_rsse_s rss;
898 struct nix_rx_mce_s mce;
899 struct nix_bandprof_s prof;
900 };
901 union {
902 struct nix_cn10k_rq_ctx_s rq_mask;
903 struct nix_cn10k_sq_ctx_s sq_mask;
904 struct nix_cq_ctx_s cq_mask;
905 struct nix_rsse_s rss_mask;
906 struct nix_rx_mce_s mce_mask;
907 struct nix_bandprof_s prof_mask;
908 };
909 };
910
911 struct nix_cn10k_aq_enq_rsp {
912 struct mbox_msghdr hdr;
913 union {
914 struct nix_cn10k_rq_ctx_s rq;
915 struct nix_cn10k_sq_ctx_s sq;
916 struct nix_cq_ctx_s cq;
917 struct nix_rsse_s rss;
918 struct nix_rx_mce_s mce;
919 struct nix_bandprof_s prof;
920 };
921 };
922
923 /* NIX AQ enqueue msg */
924 struct nix_aq_enq_req {
925 struct mbox_msghdr hdr;
926 u32 qidx;
927 u8 ctype;
928 u8 op;
929 union {
930 struct nix_rq_ctx_s rq;
931 struct nix_sq_ctx_s sq;
932 struct nix_cq_ctx_s cq;
933 struct nix_rsse_s rss;
934 struct nix_rx_mce_s mce;
935 u64 prof;
936 };
937 union {
938 struct nix_rq_ctx_s rq_mask;
939 struct nix_sq_ctx_s sq_mask;
940 struct nix_cq_ctx_s cq_mask;
941 struct nix_rsse_s rss_mask;
942 struct nix_rx_mce_s mce_mask;
943 u64 prof_mask;
944 };
945 };
946
947 struct nix_aq_enq_rsp {
948 struct mbox_msghdr hdr;
949 union {
950 struct nix_rq_ctx_s rq;
951 struct nix_sq_ctx_s sq;
952 struct nix_cq_ctx_s cq;
953 struct nix_rsse_s rss;
954 struct nix_rx_mce_s mce;
955 struct nix_bandprof_s prof;
956 };
957 };
958
959 /* Tx scheduler/shaper mailbox messages */
960
961 #define MAX_TXSCHQ_PER_FUNC 128
962
963 struct nix_txsch_alloc_req {
964 struct mbox_msghdr hdr;
965 /* Scheduler queue count request at each level */
966 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
967 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
968 };
969
970 struct nix_txsch_alloc_rsp {
971 struct mbox_msghdr hdr;
972 /* Scheduler queue count allocated at each level */
973 u16 schq_contig[NIX_TXSCH_LVL_CNT];
974 u16 schq[NIX_TXSCH_LVL_CNT];
975 /* Scheduler queue list allocated at each level */
976 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
977 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
978 u8 aggr_level; /* Traffic aggregation scheduler level */
979 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
980 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
981 };
982
983 struct nix_txsch_free_req {
984 struct mbox_msghdr hdr;
985 #define TXSCHQ_FREE_ALL BIT_ULL(0)
986 u16 flags;
987 /* Scheduler queue level to be freed */
988 u16 schq_lvl;
989 /* List of scheduler queues to be freed */
990 u16 schq;
991 };
992
993 struct nix_txschq_config {
994 struct mbox_msghdr hdr;
995 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
996 u8 read;
997 #define TXSCHQ_IDX_SHIFT 16
998 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
999 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1000 u8 num_regs;
1001 #define MAX_REGS_PER_MBOX_MSG 20
1002 u64 reg[MAX_REGS_PER_MBOX_MSG];
1003 u64 regval[MAX_REGS_PER_MBOX_MSG];
1004 /* All 0's => overwrite with new value */
1005 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1006 };
1007
1008 struct nix_vtag_config {
1009 struct mbox_msghdr hdr;
1010 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1011 u8 vtag_size;
1012 /* cfg_type is '0' for tx vlan cfg
1013 * cfg_type is '1' for rx vlan cfg
1014 */
1015 u8 cfg_type;
1016 union {
1017 /* valid when cfg_type is '0' */
1018 struct {
1019 u64 vtag0;
1020 u64 vtag1;
1021
1022 /* cfg_vtag0 & cfg_vtag1 fields are valid
1023 * when free_vtag0 & free_vtag1 are '0's.
1024 */
1025 /* cfg_vtag0 = 1 to configure vtag0 */
1026 u8 cfg_vtag0 :1;
1027 /* cfg_vtag1 = 1 to configure vtag1 */
1028 u8 cfg_vtag1 :1;
1029
1030 /* vtag0_idx & vtag1_idx are only valid when
1031 * both cfg_vtag0 & cfg_vtag1 are '0's,
1032 * these fields are used along with free_vtag0
1033 * & free_vtag1 to free the nix lf's tx_vlan
1034 * configuration.
1035 *
1036 * Denotes the indices of tx_vtag def registers
1037 * that needs to be cleared and freed.
1038 */
1039 int vtag0_idx;
1040 int vtag1_idx;
1041
1042 /* free_vtag0 & free_vtag1 fields are valid
1043 * when cfg_vtag0 & cfg_vtag1 are '0's.
1044 */
1045 /* free_vtag0 = 1 clears vtag0 configuration
1046 * vtag0_idx denotes the index to be cleared.
1047 */
1048 u8 free_vtag0 :1;
1049 /* free_vtag1 = 1 clears vtag1 configuration
1050 * vtag1_idx denotes the index to be cleared.
1051 */
1052 u8 free_vtag1 :1;
1053 } tx;
1054
1055 /* valid when cfg_type is '1' */
1056 struct {
1057 /* rx vtag type index, valid values are in 0..7 range */
1058 u8 vtag_type;
1059 /* rx vtag strip */
1060 u8 strip_vtag :1;
1061 /* rx vtag capture */
1062 u8 capture_vtag :1;
1063 } rx;
1064 };
1065 };
1066
1067 struct nix_vtag_config_rsp {
1068 struct mbox_msghdr hdr;
1069 int vtag0_idx;
1070 int vtag1_idx;
1071 /* Indices of tx_vtag def registers used to configure
1072 * tx vtag0 & vtag1 headers, these indices are valid
1073 * when nix_vtag_config mbox requested for vtag0 and/
1074 * or vtag1 configuration.
1075 */
1076 };
1077
1078 struct nix_rss_flowkey_cfg {
1079 struct mbox_msghdr hdr;
1080 int mcam_index; /* MCAM entry index to modify */
1081 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1082 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1083 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1084 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1085 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1086 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1087 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1088 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1089 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1090 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1091 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1092 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1093 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1094 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1095 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1096 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1097 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1098 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1099 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1100 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1101 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1102 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1103 u32 flowkey_cfg; /* Flowkey types selected */
1104 u8 group; /* RSS context or group */
1105 };
1106
1107 struct nix_rss_flowkey_cfg_rsp {
1108 struct mbox_msghdr hdr;
1109 u8 alg_idx; /* Selected algo index */
1110 };
1111
1112 struct nix_set_mac_addr {
1113 struct mbox_msghdr hdr;
1114 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1115 };
1116
1117 struct nix_get_mac_addr_rsp {
1118 struct mbox_msghdr hdr;
1119 u8 mac_addr[ETH_ALEN];
1120 };
1121
1122 struct nix_mark_format_cfg {
1123 struct mbox_msghdr hdr;
1124 u8 offset;
1125 u8 y_mask;
1126 u8 y_val;
1127 u8 r_mask;
1128 u8 r_val;
1129 };
1130
1131 struct nix_mark_format_cfg_rsp {
1132 struct mbox_msghdr hdr;
1133 u8 mark_format_idx;
1134 };
1135
1136 struct nix_rx_mode {
1137 struct mbox_msghdr hdr;
1138 #define NIX_RX_MODE_UCAST BIT(0)
1139 #define NIX_RX_MODE_PROMISC BIT(1)
1140 #define NIX_RX_MODE_ALLMULTI BIT(2)
1141 #define NIX_RX_MODE_USE_MCE BIT(3)
1142 u16 mode;
1143 };
1144
1145 struct nix_rx_cfg {
1146 struct mbox_msghdr hdr;
1147 #define NIX_RX_OL3_VERIFY BIT(0)
1148 #define NIX_RX_OL4_VERIFY BIT(1)
1149 u8 len_verify; /* Outer L3/L4 len check */
1150 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1151 u8 csum_verify; /* Outer L4 checksum verification */
1152 };
1153
1154 struct nix_frs_cfg {
1155 struct mbox_msghdr hdr;
1156 u8 update_smq; /* Update SMQ's min/max lens */
1157 u8 update_minlen; /* Set minlen also */
1158 u8 sdp_link; /* Set SDP RX link */
1159 u16 maxlen;
1160 u16 minlen;
1161 };
1162
1163 struct nix_lso_format_cfg {
1164 struct mbox_msghdr hdr;
1165 u64 field_mask;
1166 #define NIX_LSO_FIELD_MAX 8
1167 u64 fields[NIX_LSO_FIELD_MAX];
1168 };
1169
1170 struct nix_lso_format_cfg_rsp {
1171 struct mbox_msghdr hdr;
1172 u8 lso_format_idx;
1173 };
1174
1175 struct nix_bp_cfg_req {
1176 struct mbox_msghdr hdr;
1177 u16 chan_base; /* Starting channel number */
1178 u8 chan_cnt; /* Number of channels */
1179 u8 bpid_per_chan;
1180 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1181 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1182 };
1183
1184 /* PF can be mapped to either CGX or LBK interface,
1185 * so maximum 64 channels are possible.
1186 */
1187 #define NIX_MAX_BPID_CHAN 64
1188 struct nix_bp_cfg_rsp {
1189 struct mbox_msghdr hdr;
1190 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1191 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1192 };
1193
1194 /* Global NIX inline IPSec configuration */
1195 struct nix_inline_ipsec_cfg {
1196 struct mbox_msghdr hdr;
1197 u32 cpt_credit;
1198 struct {
1199 u8 egrp;
1200 u8 opcode;
1201 u16 param1;
1202 u16 param2;
1203 } gen_cfg;
1204 struct {
1205 u16 cpt_pf_func;
1206 u8 cpt_slot;
1207 } inst_qsel;
1208 u8 enable;
1209 };
1210
1211 /* Per NIX LF inline IPSec configuration */
1212 struct nix_inline_ipsec_lf_cfg {
1213 struct mbox_msghdr hdr;
1214 u64 sa_base_addr;
1215 struct {
1216 u32 tag_const;
1217 u16 lenm1_max;
1218 u8 sa_pow2_size;
1219 u8 tt;
1220 } ipsec_cfg0;
1221 struct {
1222 u32 sa_idx_max;
1223 u8 sa_idx_w;
1224 } ipsec_cfg1;
1225 u8 enable;
1226 };
1227
1228 struct nix_hw_info {
1229 struct mbox_msghdr hdr;
1230 u16 rsvs16;
1231 u16 max_mtu;
1232 u16 min_mtu;
1233 u32 rpm_dwrr_mtu;
1234 u32 sdp_dwrr_mtu;
1235 u64 rsvd[16]; /* Add reserved fields for future expansion */
1236 };
1237
1238 struct nix_bandprof_alloc_req {
1239 struct mbox_msghdr hdr;
1240 /* Count of profiles needed per layer */
1241 u16 prof_count[BAND_PROF_NUM_LAYERS];
1242 };
1243
1244 struct nix_bandprof_alloc_rsp {
1245 struct mbox_msghdr hdr;
1246 u16 prof_count[BAND_PROF_NUM_LAYERS];
1247
1248 /* There is no need to allocate morethan 1 bandwidth profile
1249 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1250 * profiles to 64 per PF_FUNC.
1251 */
1252 #define MAX_BANDPROF_PER_PFFUNC 64
1253 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1254 };
1255
1256 struct nix_bandprof_free_req {
1257 struct mbox_msghdr hdr;
1258 u8 free_all;
1259 u16 prof_count[BAND_PROF_NUM_LAYERS];
1260 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1261 };
1262
1263 struct nix_bandprof_get_hwinfo_rsp {
1264 struct mbox_msghdr hdr;
1265 u16 prof_count[BAND_PROF_NUM_LAYERS];
1266 u32 policer_timeunit;
1267 };
1268
1269 /* NPC mbox message structs */
1270
1271 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1272 #define NPC_MCAM_INVALID_MAP 0xFFFF
1273
1274 /* NPC mailbox error codes
1275 * Range 701 - 800.
1276 */
1277 enum npc_af_status {
1278 NPC_MCAM_INVALID_REQ = -701,
1279 NPC_MCAM_ALLOC_DENIED = -702,
1280 NPC_MCAM_ALLOC_FAILED = -703,
1281 NPC_MCAM_PERM_DENIED = -704,
1282 NPC_FLOW_INTF_INVALID = -707,
1283 NPC_FLOW_CHAN_INVALID = -708,
1284 NPC_FLOW_NO_NIXLF = -709,
1285 NPC_FLOW_NOT_SUPPORTED = -710,
1286 NPC_FLOW_VF_PERM_DENIED = -711,
1287 NPC_FLOW_VF_NOT_INIT = -712,
1288 NPC_FLOW_VF_OVERLAP = -713,
1289 };
1290
1291 struct npc_mcam_alloc_entry_req {
1292 struct mbox_msghdr hdr;
1293 #define NPC_MAX_NONCONTIG_ENTRIES 256
1294 u8 contig; /* Contiguous entries ? */
1295 #define NPC_MCAM_ANY_PRIO 0
1296 #define NPC_MCAM_LOWER_PRIO 1
1297 #define NPC_MCAM_HIGHER_PRIO 2
1298 u8 priority; /* Lower or higher w.r.t ref_entry */
1299 u16 ref_entry;
1300 u16 count; /* Number of entries requested */
1301 };
1302
1303 struct npc_mcam_alloc_entry_rsp {
1304 struct mbox_msghdr hdr;
1305 u16 entry; /* Entry allocated or start index if contiguous.
1306 * Invalid incase of non-contiguous.
1307 */
1308 u16 count; /* Number of entries allocated */
1309 u16 free_count; /* Number of entries available */
1310 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1311 };
1312
1313 struct npc_mcam_free_entry_req {
1314 struct mbox_msghdr hdr;
1315 u16 entry; /* Entry index to be freed */
1316 u8 all; /* If all entries allocated to this PFVF to be freed */
1317 };
1318
1319 struct mcam_entry {
1320 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1321 u64 kw[NPC_MAX_KWS_IN_KEY];
1322 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1323 u64 action;
1324 u64 vtag_action;
1325 };
1326
1327 struct npc_mcam_write_entry_req {
1328 struct mbox_msghdr hdr;
1329 struct mcam_entry entry_data;
1330 u16 entry; /* MCAM entry to write this match key */
1331 u16 cntr; /* Counter for this MCAM entry */
1332 u8 intf; /* Rx or Tx interface */
1333 u8 enable_entry;/* Enable this MCAM entry ? */
1334 u8 set_cntr; /* Set counter for this entry ? */
1335 };
1336
1337 /* Enable/Disable a given entry */
1338 struct npc_mcam_ena_dis_entry_req {
1339 struct mbox_msghdr hdr;
1340 u16 entry;
1341 };
1342
1343 struct npc_mcam_shift_entry_req {
1344 struct mbox_msghdr hdr;
1345 #define NPC_MCAM_MAX_SHIFTS 64
1346 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1347 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1348 u16 shift_count; /* Number of entries to shift */
1349 };
1350
1351 struct npc_mcam_shift_entry_rsp {
1352 struct mbox_msghdr hdr;
1353 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1354 };
1355
1356 struct npc_mcam_alloc_counter_req {
1357 struct mbox_msghdr hdr;
1358 u8 contig; /* Contiguous counters ? */
1359 #define NPC_MAX_NONCONTIG_COUNTERS 64
1360 u16 count; /* Number of counters requested */
1361 };
1362
1363 struct npc_mcam_alloc_counter_rsp {
1364 struct mbox_msghdr hdr;
1365 u16 cntr; /* Counter allocated or start index if contiguous.
1366 * Invalid incase of non-contiguous.
1367 */
1368 u16 count; /* Number of counters allocated */
1369 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1370 };
1371
1372 struct npc_mcam_oper_counter_req {
1373 struct mbox_msghdr hdr;
1374 u16 cntr; /* Free a counter or clear/fetch it's stats */
1375 };
1376
1377 struct npc_mcam_oper_counter_rsp {
1378 struct mbox_msghdr hdr;
1379 u64 stat; /* valid only while fetching counter's stats */
1380 };
1381
1382 struct npc_mcam_unmap_counter_req {
1383 struct mbox_msghdr hdr;
1384 u16 cntr;
1385 u16 entry; /* Entry and counter to be unmapped */
1386 u8 all; /* Unmap all entries using this counter ? */
1387 };
1388
1389 struct npc_mcam_alloc_and_write_entry_req {
1390 struct mbox_msghdr hdr;
1391 struct mcam_entry entry_data;
1392 u16 ref_entry;
1393 u8 priority; /* Lower or higher w.r.t ref_entry */
1394 u8 intf; /* Rx or Tx interface */
1395 u8 enable_entry;/* Enable this MCAM entry ? */
1396 u8 alloc_cntr; /* Allocate counter and map ? */
1397 };
1398
1399 struct npc_mcam_alloc_and_write_entry_rsp {
1400 struct mbox_msghdr hdr;
1401 u16 entry;
1402 u16 cntr;
1403 };
1404
1405 struct npc_get_kex_cfg_rsp {
1406 struct mbox_msghdr hdr;
1407 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1408 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1409 #define NPC_MAX_INTF 2
1410 #define NPC_MAX_LID 8
1411 #define NPC_MAX_LT 16
1412 #define NPC_MAX_LD 2
1413 #define NPC_MAX_LFL 16
1414 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1415 u64 kex_ld_flags[NPC_MAX_LD];
1416 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1417 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1418 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1419 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1420 #define MKEX_NAME_LEN 128
1421 u8 mkex_pfl_name[MKEX_NAME_LEN];
1422 };
1423
1424 struct flow_msg {
1425 unsigned char dmac[6];
1426 unsigned char smac[6];
1427 __be16 etype;
1428 __be16 vlan_etype;
1429 __be16 vlan_tci;
1430 union {
1431 __be32 ip4src;
1432 __be32 ip6src[4];
1433 };
1434 union {
1435 __be32 ip4dst;
1436 __be32 ip6dst[4];
1437 };
1438 u8 tos;
1439 u8 ip_ver;
1440 u8 ip_proto;
1441 u8 tc;
1442 __be16 sport;
1443 __be16 dport;
1444 };
1445
1446 struct npc_install_flow_req {
1447 struct mbox_msghdr hdr;
1448 struct flow_msg packet;
1449 struct flow_msg mask;
1450 u64 features;
1451 u16 entry;
1452 u16 channel;
1453 u16 chan_mask;
1454 u8 intf;
1455 u8 set_cntr; /* If counter is available set counter for this entry ? */
1456 u8 default_rule;
1457 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1458 u16 vf;
1459 /* action */
1460 u32 index;
1461 u16 match_id;
1462 u8 flow_key_alg;
1463 u8 op;
1464 /* vtag rx action */
1465 u8 vtag0_type;
1466 u8 vtag0_valid;
1467 u8 vtag1_type;
1468 u8 vtag1_valid;
1469 /* vtag tx action */
1470 u16 vtag0_def;
1471 u8 vtag0_op;
1472 u16 vtag1_def;
1473 u8 vtag1_op;
1474 /* old counter value */
1475 u16 cntr_val;
1476 };
1477
1478 struct npc_install_flow_rsp {
1479 struct mbox_msghdr hdr;
1480 int counter; /* negative if no counter else counter number */
1481 };
1482
1483 struct npc_delete_flow_req {
1484 struct mbox_msghdr hdr;
1485 u16 entry;
1486 u16 start;/*Disable range of entries */
1487 u16 end;
1488 u8 all; /* PF + VFs */
1489 };
1490
1491 struct npc_delete_flow_rsp {
1492 struct mbox_msghdr hdr;
1493 u16 cntr_val;
1494 };
1495
1496 struct npc_mcam_read_entry_req {
1497 struct mbox_msghdr hdr;
1498 u16 entry; /* MCAM entry to read */
1499 };
1500
1501 struct npc_mcam_read_entry_rsp {
1502 struct mbox_msghdr hdr;
1503 struct mcam_entry entry_data;
1504 u8 intf;
1505 u8 enable;
1506 };
1507
1508 struct npc_mcam_read_base_rule_rsp {
1509 struct mbox_msghdr hdr;
1510 struct mcam_entry entry;
1511 };
1512
1513 struct npc_mcam_get_stats_req {
1514 struct mbox_msghdr hdr;
1515 u16 entry; /* mcam entry */
1516 };
1517
1518 struct npc_mcam_get_stats_rsp {
1519 struct mbox_msghdr hdr;
1520 u64 stat; /* counter stats */
1521 u8 stat_ena; /* enabled */
1522 };
1523
1524 struct npc_get_field_hash_info_req {
1525 struct mbox_msghdr hdr;
1526 u8 intf;
1527 };
1528
1529 struct npc_get_field_hash_info_rsp {
1530 struct mbox_msghdr hdr;
1531 u64 secret_key[3];
1532 #define NPC_MAX_HASH 2
1533 #define NPC_MAX_HASH_MASK 2
1534 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1535 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1536 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1537 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1538 };
1539
1540 enum ptp_op {
1541 PTP_OP_ADJFINE = 0,
1542 PTP_OP_GET_CLOCK = 1,
1543 PTP_OP_GET_TSTMP = 2,
1544 PTP_OP_SET_THRESH = 3,
1545 PTP_OP_EXTTS_ON = 4,
1546 };
1547
1548 struct ptp_req {
1549 struct mbox_msghdr hdr;
1550 u8 op;
1551 s64 scaled_ppm;
1552 u64 thresh;
1553 int extts_on;
1554 };
1555
1556 struct ptp_rsp {
1557 struct mbox_msghdr hdr;
1558 u64 clk;
1559 };
1560
1561 struct npc_get_field_status_req {
1562 struct mbox_msghdr hdr;
1563 u8 intf;
1564 u8 field;
1565 };
1566
1567 struct npc_get_field_status_rsp {
1568 struct mbox_msghdr hdr;
1569 u8 enable;
1570 };
1571
1572 struct set_vf_perm {
1573 struct mbox_msghdr hdr;
1574 u16 vf;
1575 #define RESET_VF_PERM BIT_ULL(0)
1576 #define VF_TRUSTED BIT_ULL(1)
1577 u64 flags;
1578 };
1579
1580 struct lmtst_tbl_setup_req {
1581 struct mbox_msghdr hdr;
1582 u64 dis_sched_early_comp :1;
1583 u64 sch_ena :1;
1584 u64 dis_line_pref :1;
1585 u64 ssow_pf_func :13;
1586 u16 base_pcifunc;
1587 u8 use_local_lmt_region;
1588 u64 lmt_iova;
1589 u64 rsvd[4];
1590 };
1591
1592 /* CPT mailbox error codes
1593 * Range 901 - 1000.
1594 */
1595 enum cpt_af_status {
1596 CPT_AF_ERR_PARAM = -901,
1597 CPT_AF_ERR_GRP_INVALID = -902,
1598 CPT_AF_ERR_LF_INVALID = -903,
1599 CPT_AF_ERR_ACCESS_DENIED = -904,
1600 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1601 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1602 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1603 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1604 };
1605
1606 /* CPT mbox message formats */
1607 struct cpt_rd_wr_reg_msg {
1608 struct mbox_msghdr hdr;
1609 u64 reg_offset;
1610 u64 *ret_val;
1611 u64 val;
1612 u8 is_write;
1613 int blkaddr;
1614 };
1615
1616 struct cpt_lf_alloc_req_msg {
1617 struct mbox_msghdr hdr;
1618 u16 nix_pf_func;
1619 u16 sso_pf_func;
1620 u16 eng_grpmsk;
1621 int blkaddr;
1622 };
1623
1624 #define CPT_INLINE_INBOUND 0
1625 #define CPT_INLINE_OUTBOUND 1
1626
1627 /* Mailbox message request format for CPT IPsec
1628 * inline inbound and outbound configuration.
1629 */
1630 struct cpt_inline_ipsec_cfg_msg {
1631 struct mbox_msghdr hdr;
1632 u8 enable;
1633 u8 slot;
1634 u8 dir;
1635 u8 sso_pf_func_ovrd;
1636 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1637 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1638 };
1639
1640 /* Mailbox message request and response format for CPT stats. */
1641 struct cpt_sts_req {
1642 struct mbox_msghdr hdr;
1643 u8 blkaddr;
1644 };
1645
1646 struct cpt_sts_rsp {
1647 struct mbox_msghdr hdr;
1648 u64 inst_req_pc;
1649 u64 inst_lat_pc;
1650 u64 rd_req_pc;
1651 u64 rd_lat_pc;
1652 u64 rd_uc_pc;
1653 u64 active_cycles_pc;
1654 u64 ctx_mis_pc;
1655 u64 ctx_hit_pc;
1656 u64 ctx_aop_pc;
1657 u64 ctx_aop_lat_pc;
1658 u64 ctx_ifetch_pc;
1659 u64 ctx_ifetch_lat_pc;
1660 u64 ctx_ffetch_pc;
1661 u64 ctx_ffetch_lat_pc;
1662 u64 ctx_wback_pc;
1663 u64 ctx_wback_lat_pc;
1664 u64 ctx_psh_pc;
1665 u64 ctx_psh_lat_pc;
1666 u64 ctx_err;
1667 u64 ctx_enc_id;
1668 u64 ctx_flush_timer;
1669 u64 rxc_time;
1670 u64 rxc_time_cfg;
1671 u64 rxc_active_sts;
1672 u64 rxc_zombie_sts;
1673 u64 busy_sts_ae;
1674 u64 free_sts_ae;
1675 u64 busy_sts_se;
1676 u64 free_sts_se;
1677 u64 busy_sts_ie;
1678 u64 free_sts_ie;
1679 u64 exe_err_info;
1680 u64 cptclk_cnt;
1681 u64 diag;
1682 u64 rxc_dfrg;
1683 u64 x2p_link_cfg0;
1684 u64 x2p_link_cfg1;
1685 };
1686
1687 /* Mailbox message request format to configure reassembly timeout. */
1688 struct cpt_rxc_time_cfg_req {
1689 struct mbox_msghdr hdr;
1690 int blkaddr;
1691 u32 step;
1692 u16 zombie_thres;
1693 u16 zombie_limit;
1694 u16 active_thres;
1695 u16 active_limit;
1696 };
1697
1698 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1699 struct cpt_inst_lmtst_req {
1700 struct mbox_msghdr hdr;
1701 u64 inst[8];
1702 u64 rsvd;
1703 };
1704
1705 struct sdp_node_info {
1706 /* Node to which this PF belons to */
1707 u8 node_id;
1708 u8 max_vfs;
1709 u8 num_pf_rings;
1710 u8 pf_srn;
1711 #define SDP_MAX_VFS 128
1712 u8 vf_rings[SDP_MAX_VFS];
1713 };
1714
1715 struct sdp_chan_info_msg {
1716 struct mbox_msghdr hdr;
1717 struct sdp_node_info info;
1718 };
1719
1720 struct sdp_get_chan_info_msg {
1721 struct mbox_msghdr hdr;
1722 u16 chan_base;
1723 u16 num_chan;
1724 };
1725
1726 /* CGX mailbox error codes
1727 * Range 1101 - 1200.
1728 */
1729 enum cgx_af_status {
1730 LMAC_AF_ERR_INVALID_PARAM = -1101,
1731 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1732 LMAC_AF_ERR_PERM_DENIED = -1103,
1733 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1734 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1735 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1736 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1737 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1738 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1739 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1740 };
1741
1742 enum mcs_direction {
1743 MCS_RX,
1744 MCS_TX,
1745 };
1746
1747 enum mcs_rsrc_type {
1748 MCS_RSRC_TYPE_FLOWID,
1749 MCS_RSRC_TYPE_SECY,
1750 MCS_RSRC_TYPE_SC,
1751 MCS_RSRC_TYPE_SA,
1752 };
1753
1754 struct mcs_alloc_rsrc_req {
1755 struct mbox_msghdr hdr;
1756 u8 rsrc_type;
1757 u8 rsrc_cnt; /* Resources count */
1758 u8 mcs_id; /* MCS block ID */
1759 u8 dir; /* Macsec ingress or egress side */
1760 u8 all; /* Allocate all resource type one each */
1761 u64 rsvd;
1762 };
1763
1764 struct mcs_alloc_rsrc_rsp {
1765 struct mbox_msghdr hdr;
1766 u8 flow_ids[128]; /* Index of reserved entries */
1767 u8 secy_ids[128];
1768 u8 sc_ids[128];
1769 u8 sa_ids[256];
1770 u8 rsrc_type;
1771 u8 rsrc_cnt; /* No of entries reserved */
1772 u8 mcs_id;
1773 u8 dir;
1774 u8 all;
1775 u8 rsvd[256]; /* reserved fields for future expansion */
1776 };
1777
1778 struct mcs_free_rsrc_req {
1779 struct mbox_msghdr hdr;
1780 u8 rsrc_id; /* Index of the entry to be freed */
1781 u8 rsrc_type;
1782 u8 mcs_id;
1783 u8 dir;
1784 u8 all; /* Free all the cam resources */
1785 u64 rsvd;
1786 };
1787
1788 struct mcs_flowid_entry_write_req {
1789 struct mbox_msghdr hdr;
1790 u64 data[4];
1791 u64 mask[4];
1792 u64 sci; /* CNF10K-B for tx_secy_mem_map */
1793 u8 flow_id;
1794 u8 secy_id; /* secyid for which flowid is mapped */
1795 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1796 u8 ena; /* Enable tcam entry */
1797 u8 ctrl_pkt;
1798 u8 mcs_id;
1799 u8 dir;
1800 u64 rsvd;
1801 };
1802
1803 struct mcs_secy_plcy_write_req {
1804 struct mbox_msghdr hdr;
1805 u64 plcy;
1806 u8 secy_id;
1807 u8 mcs_id;
1808 u8 dir;
1809 u64 rsvd;
1810 };
1811
1812 /* RX SC_CAM mapping */
1813 struct mcs_rx_sc_cam_write_req {
1814 struct mbox_msghdr hdr;
1815 u64 sci; /* SCI */
1816 u64 secy_id; /* secy index mapped to SC */
1817 u8 sc_id; /* SC CAM entry index */
1818 u8 mcs_id;
1819 u64 rsvd;
1820 };
1821
1822 struct mcs_sa_plcy_write_req {
1823 struct mbox_msghdr hdr;
1824 u64 plcy[2][9]; /* Support 2 SA policy */
1825 u8 sa_index[2];
1826 u8 sa_cnt;
1827 u8 mcs_id;
1828 u8 dir;
1829 u64 rsvd;
1830 };
1831
1832 struct mcs_tx_sc_sa_map {
1833 struct mbox_msghdr hdr;
1834 u8 sa_index0;
1835 u8 sa_index1;
1836 u8 rekey_ena;
1837 u8 sa_index0_vld;
1838 u8 sa_index1_vld;
1839 u8 tx_sa_active;
1840 u64 sectag_sci;
1841 u8 sc_id; /* used as index for SA_MEM_MAP */
1842 u8 mcs_id;
1843 u64 rsvd;
1844 };
1845
1846 struct mcs_rx_sc_sa_map {
1847 struct mbox_msghdr hdr;
1848 u8 sa_index;
1849 u8 sa_in_use;
1850 u8 sc_id;
1851 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
1852 u8 mcs_id;
1853 u64 rsvd;
1854 };
1855
1856 struct mcs_flowid_ena_dis_entry {
1857 struct mbox_msghdr hdr;
1858 u8 flow_id;
1859 u8 ena;
1860 u8 mcs_id;
1861 u8 dir;
1862 u64 rsvd;
1863 };
1864
1865 struct mcs_pn_table_write_req {
1866 struct mbox_msghdr hdr;
1867 u64 next_pn;
1868 u8 pn_id;
1869 u8 mcs_id;
1870 u8 dir;
1871 u64 rsvd;
1872 };
1873
1874 struct mcs_hw_info {
1875 struct mbox_msghdr hdr;
1876 u8 num_mcs_blks; /* Number of MCS blocks */
1877 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
1878 u8 secy_entries; /* RX/TX SECY entries per mcs block */
1879 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
1880 u16 sa_entries; /* PN table entries = SA entries */
1881 u64 rsvd[16];
1882 };
1883
1884 struct mcs_set_active_lmac {
1885 struct mbox_msghdr hdr;
1886 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
1887 u8 mcs_id;
1888 u16 chan_base; /* MCS channel base */
1889 u64 rsvd;
1890 };
1891
1892 struct mcs_set_lmac_mode {
1893 struct mbox_msghdr hdr;
1894 u8 mode; /* 1:Bypass 0:Operational */
1895 u8 lmac_id;
1896 u8 mcs_id;
1897 u64 rsvd;
1898 };
1899
1900 struct mcs_port_reset_req {
1901 struct mbox_msghdr hdr;
1902 u8 reset;
1903 u8 mcs_id;
1904 u8 port_id;
1905 u64 rsvd;
1906 };
1907
1908 struct mcs_port_cfg_set_req {
1909 struct mbox_msghdr hdr;
1910 u8 cstm_tag_rel_mode_sel;
1911 u8 custom_hdr_enb;
1912 u8 fifo_skid;
1913 u8 port_mode;
1914 u8 port_id;
1915 u8 mcs_id;
1916 u64 rsvd;
1917 };
1918
1919 struct mcs_port_cfg_get_req {
1920 struct mbox_msghdr hdr;
1921 u8 port_id;
1922 u8 mcs_id;
1923 u64 rsvd;
1924 };
1925
1926 struct mcs_port_cfg_get_rsp {
1927 struct mbox_msghdr hdr;
1928 u8 cstm_tag_rel_mode_sel;
1929 u8 custom_hdr_enb;
1930 u8 fifo_skid;
1931 u8 port_mode;
1932 u8 port_id;
1933 u8 mcs_id;
1934 u64 rsvd;
1935 };
1936
1937 struct mcs_custom_tag_cfg_get_req {
1938 struct mbox_msghdr hdr;
1939 u8 mcs_id;
1940 u8 dir;
1941 u64 rsvd;
1942 };
1943
1944 struct mcs_custom_tag_cfg_get_rsp {
1945 struct mbox_msghdr hdr;
1946 u16 cstm_etype[8];
1947 u8 cstm_indx[8];
1948 u8 cstm_etype_en;
1949 u8 mcs_id;
1950 u8 dir;
1951 u64 rsvd;
1952 };
1953
1954 /* MCS mailbox error codes
1955 * Range 1201 - 1300.
1956 */
1957 enum mcs_af_status {
1958 MCS_AF_ERR_INVALID_MCSID = -1201,
1959 MCS_AF_ERR_NOT_MAPPED = -1202,
1960 };
1961
1962 struct mcs_set_pn_threshold {
1963 struct mbox_msghdr hdr;
1964 u64 threshold;
1965 u8 xpn; /* '1' for setting xpn threshold */
1966 u8 mcs_id;
1967 u8 dir;
1968 u64 rsvd;
1969 };
1970
1971 enum mcs_ctrl_pkt_rulew_type {
1972 MCS_CTRL_PKT_RULE_TYPE_ETH,
1973 MCS_CTRL_PKT_RULE_TYPE_DA,
1974 MCS_CTRL_PKT_RULE_TYPE_RANGE,
1975 MCS_CTRL_PKT_RULE_TYPE_COMBO,
1976 MCS_CTRL_PKT_RULE_TYPE_MAC,
1977 };
1978
1979 struct mcs_alloc_ctrl_pkt_rule_req {
1980 struct mbox_msghdr hdr;
1981 u8 rule_type;
1982 u8 mcs_id; /* MCS block ID */
1983 u8 dir; /* Macsec ingress or egress side */
1984 u64 rsvd;
1985 };
1986
1987 struct mcs_alloc_ctrl_pkt_rule_rsp {
1988 struct mbox_msghdr hdr;
1989 u8 rule_idx;
1990 u8 rule_type;
1991 u8 mcs_id;
1992 u8 dir;
1993 u64 rsvd;
1994 };
1995
1996 struct mcs_free_ctrl_pkt_rule_req {
1997 struct mbox_msghdr hdr;
1998 u8 rule_idx;
1999 u8 rule_type;
2000 u8 mcs_id;
2001 u8 dir;
2002 u8 all;
2003 u64 rsvd;
2004 };
2005
2006 struct mcs_ctrl_pkt_rule_write_req {
2007 struct mbox_msghdr hdr;
2008 u64 data0;
2009 u64 data1;
2010 u64 data2;
2011 u8 rule_idx;
2012 u8 rule_type;
2013 u8 mcs_id;
2014 u8 dir;
2015 u64 rsvd;
2016 };
2017
2018 struct mcs_stats_req {
2019 struct mbox_msghdr hdr;
2020 u8 id;
2021 u8 mcs_id;
2022 u8 dir;
2023 u64 rsvd;
2024 };
2025
2026 struct mcs_flowid_stats {
2027 struct mbox_msghdr hdr;
2028 u64 tcam_hit_cnt;
2029 u64 rsvd;
2030 };
2031
2032 struct mcs_secy_stats {
2033 struct mbox_msghdr hdr;
2034 u64 ctl_pkt_bcast_cnt;
2035 u64 ctl_pkt_mcast_cnt;
2036 u64 ctl_pkt_ucast_cnt;
2037 u64 ctl_octet_cnt;
2038 u64 unctl_pkt_bcast_cnt;
2039 u64 unctl_pkt_mcast_cnt;
2040 u64 unctl_pkt_ucast_cnt;
2041 u64 unctl_octet_cnt;
2042 /* Valid only for RX */
2043 u64 octet_decrypted_cnt;
2044 u64 octet_validated_cnt;
2045 u64 pkt_port_disabled_cnt;
2046 u64 pkt_badtag_cnt;
2047 u64 pkt_nosa_cnt;
2048 u64 pkt_nosaerror_cnt;
2049 u64 pkt_tagged_ctl_cnt;
2050 u64 pkt_untaged_cnt;
2051 u64 pkt_ctl_cnt; /* CN10K-B */
2052 u64 pkt_notag_cnt; /* CNF10K-B */
2053 /* Valid only for TX */
2054 u64 octet_encrypted_cnt;
2055 u64 octet_protected_cnt;
2056 u64 pkt_noactivesa_cnt;
2057 u64 pkt_toolong_cnt;
2058 u64 pkt_untagged_cnt;
2059 u64 rsvd[4];
2060 };
2061
2062 struct mcs_port_stats {
2063 struct mbox_msghdr hdr;
2064 u64 tcam_miss_cnt;
2065 u64 parser_err_cnt;
2066 u64 preempt_err_cnt; /* CNF10K-B */
2067 u64 sectag_insert_err_cnt;
2068 u64 rsvd[4];
2069 };
2070
2071 /* Only for CN10K-B */
2072 struct mcs_sa_stats {
2073 struct mbox_msghdr hdr;
2074 /* RX */
2075 u64 pkt_invalid_cnt;
2076 u64 pkt_nosaerror_cnt;
2077 u64 pkt_notvalid_cnt;
2078 u64 pkt_ok_cnt;
2079 u64 pkt_nosa_cnt;
2080 /* TX */
2081 u64 pkt_encrypt_cnt;
2082 u64 pkt_protected_cnt;
2083 u64 rsvd[4];
2084 };
2085
2086 struct mcs_sc_stats {
2087 struct mbox_msghdr hdr;
2088 /* RX */
2089 u64 hit_cnt;
2090 u64 pkt_invalid_cnt;
2091 u64 pkt_late_cnt;
2092 u64 pkt_notvalid_cnt;
2093 u64 pkt_unchecked_cnt;
2094 u64 pkt_delay_cnt; /* CNF10K-B */
2095 u64 pkt_ok_cnt; /* CNF10K-B */
2096 u64 octet_decrypt_cnt; /* CN10K-B */
2097 u64 octet_validate_cnt; /* CN10K-B */
2098 /* TX */
2099 u64 pkt_encrypt_cnt;
2100 u64 pkt_protected_cnt;
2101 u64 octet_encrypt_cnt; /* CN10K-B */
2102 u64 octet_protected_cnt; /* CN10K-B */
2103 u64 rsvd[4];
2104 };
2105
2106 struct mcs_clear_stats {
2107 struct mbox_msghdr hdr;
2108 #define MCS_FLOWID_STATS 0
2109 #define MCS_SECY_STATS 1
2110 #define MCS_SC_STATS 2
2111 #define MCS_SA_STATS 3
2112 #define MCS_PORT_STATS 4
2113 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2114 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2115 u8 mcs_id;
2116 u8 dir;
2117 u8 all; /* All resources stats mapped to PF are cleared */
2118 };
2119
2120 struct mcs_intr_cfg {
2121 struct mbox_msghdr hdr;
2122 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2123 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2124 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2125 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2126 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2127 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2128 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2129 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2130 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2131 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2132 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2133 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2134 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2135 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2136 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2137 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2138 u64 intr_mask; /* Interrupt enable mask */
2139 u8 mcs_id;
2140 u8 lmac_id;
2141 u64 rsvd;
2142 };
2143
2144 struct mcs_intr_info {
2145 struct mbox_msghdr hdr;
2146 u64 intr_mask;
2147 int sa_id;
2148 u8 mcs_id;
2149 u8 lmac_id;
2150 u64 rsvd;
2151 };
2152
2153 #endif /* MBOX_H */
2154